Filipriec
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6f27f98a38
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final uml
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2025-11-25 17:45:39 +01:00 |
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Filipriec
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a61b808176
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finalized plantuml
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2025-11-25 15:19:06 +01:00 |
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Filipriec
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4ff73644c6
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uml
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2025-11-25 15:10:25 +01:00 |
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Filipriec
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f6d83a0acc
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updated lock file
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2025-11-25 07:56:51 +01:00 |
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Filipriec
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3e2ad6eb7d
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timing uml diagrams added
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2025-11-24 09:41:46 +01:00 |
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Priec
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6d694c840b
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cleanup
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2025-11-24 00:21:58 +01:00 |
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Priec
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522236e20c
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removed redundant code
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2025-11-23 23:12:32 +01:00 |
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Priec
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804dc66a4b
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sampling only in the middle
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2025-11-23 22:16:36 +01:00 |
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Priec
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9451bc5ae9
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timer HAL
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2025-11-23 21:44:01 +01:00 |
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Priec
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e5e4d13ff6
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prod1
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2025-11-23 21:02:36 +01:00 |
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Priec
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d0ddea119d
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Add global target ignore
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2025-11-23 16:24:28 +01:00 |
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Priec
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348c4e63d9
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library now fully functional and working
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2025-11-23 16:01:01 +01:00 |
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Priec
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3218714d8c
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software uart lib errors fixed
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2025-11-23 15:54:20 +01:00 |
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Priec
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4097ce1c7a
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software uart is now a library
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2025-11-23 15:48:54 +01:00 |
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Priec
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685067a75f
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jsut minor changes, UNTESTED DMA TIMER CHANGE
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2025-11-20 13:28:09 +01:00 |
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Priec
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179bec6ed6
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finished and fully functional
v1.9.0
|
2025-11-19 23:30:55 +01:00 |
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Priec
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8e1c2ec29f
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time to do final merge
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2025-11-19 21:46:07 +01:00 |
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Priec
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e569fbc39d
|
dma used to transfer Tx
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2025-11-19 21:41:08 +01:00 |
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Priec
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24d1da44aa
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working at the baud rate 600
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2025-11-19 21:12:41 +01:00 |
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Priec
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ef56483016
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improved parsing of software uart
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2025-11-19 20:40:13 +01:00 |
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Priec
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de4e04787b
|
max frequency fixed it all
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2025-11-19 20:28:24 +01:00 |
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Priec
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78c85c7982
|
tweaked parameters, storing before increasing frequencies
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2025-11-19 19:43:10 +01:00 |
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Priec
|
bf34ff1bcb
|
faster and smarter DMA
|
2025-11-19 18:48:09 +01:00 |
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Priec
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e2378cd436
|
working with DMA at 9600
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2025-11-19 18:32:18 +01:00 |
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Priec
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110ddc0dcf
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working, overhead is down a bit
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2025-11-19 17:50:33 +01:00 |
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Priec
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0cd40eb5e2
|
uart rx working fully
|
2025-11-19 15:59:14 +01:00 |
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Priec
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46486a6e74
|
working data catch
|
2025-11-19 14:51:42 +01:00 |
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Priec
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89ee552da3
|
working only at 600 baud, we are reading data of the pin in the interrupt
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2025-11-19 14:41:39 +01:00 |
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Priec
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28d041873c
|
starting fresh again 1d rx bez dma
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2025-11-19 13:03:28 +01:00 |
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Priec
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2ef75c319d
|
working buffer transfer, lets build from in here
|
2025-11-19 12:56:47 +01:00 |
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Priec
|
da2f011682
|
1d needs to be builded again from scratch
|
2025-11-19 12:51:45 +01:00 |
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Priec
|
b339b34e4d
|
toggling bit and reading it now works properly well
|
2025-11-19 12:11:19 +01:00 |
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Priec
|
9c26a0ca81
|
not working interrupt via tim7 to read data
|
2025-11-19 11:57:28 +01:00 |
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Priec
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c5bee53a30
|
toggle in the interrupt is working
|
2025-11-19 11:39:55 +01:00 |
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Priec
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7a8a308620
|
now im reading proper buffer
|
2025-11-18 23:23:33 +01:00 |
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Priec
|
516309aed2
|
proper printing of the pipe_int tx_pipe
|
2025-11-18 22:56:28 +01:00 |
|
Filipriec
|
45df1e87e4
|
testing, not owrking 1d yet
|
2025-11-18 19:39:51 +01:00 |
|
Filipriec
|
0a0ff0f38a
|
debugging more
|
2025-11-18 16:55:42 +01:00 |
|
Filipriec
|
1909497403
|
hopefuly working CPU transfer to bsrr
|
2025-11-18 13:36:07 +01:00 |
|
Priec
|
c01a908b25
|
cpu polling instead of dma
|
2025-11-18 10:29:29 +01:00 |
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Priec
|
c0bc36bec2
|
rx bez dma ready for testing
|
2025-11-18 10:12:02 +01:00 |
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Priec
|
66c4741afa
|
blbosti
|
2025-11-18 09:20:57 +01:00 |
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Priec
|
fa343624e7
|
tx stale nefunguje
|
2025-11-12 23:37:32 +01:00 |
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Priec
|
66521896b3
|
moving things around, time to debug crap out of it
|
2025-11-12 19:07:00 +01:00 |
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Priec
|
a0c30894ee
|
better registers for Rx
|
2025-11-12 18:54:42 +01:00 |
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Priec
|
16c66ee1ff
|
final debug
|
2025-11-12 18:22:07 +01:00 |
|
Priec
|
8c6f703de9
|
bridge between usart1 and usart2
|
2025-11-12 17:33:34 +01:00 |
|
Priec
|
05662a45d0
|
there is some bug
|
2025-11-12 16:07:59 +01:00 |
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Priec
|
829cff872f
|
using correct pipes now
|
2025-11-12 14:15:33 +01:00 |
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Priec
|
2fb198ceb8
|
fully built, time to make it work
|
2025-11-12 13:03:17 +01:00 |
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