Filipriec 4ff73644c6 uml

2025-11-25 15:10:25 +01:00

dma_gpio

restored Rx ring properly well with the dma_gpio2 initialized

2025-11-10 18:11:28 +01:00

dma_gpio2

priec - filip user

2025-11-11 22:08:59 +01:00

hal_adc

…

hal_rng

…

hal_test

…

semestralka_1

there is some bug

2025-11-12 16:07:59 +01:00

semestralka_1_2hwuart_internal

1d needs to be builded again from scratch

2025-11-19 12:51:45 +01:00

semestralka_1_connected

jsut minor changes, UNTESTED DMA TIMER CHANGE

2025-11-20 13:28:09 +01:00

semestralka_1_final_crate/software_uart

uml

2025-11-25 15:10:25 +01:00

semestralka_1_final_lib

cleanup

2025-11-24 00:21:58 +01:00

semestralka_1b_rx

tx stale nefunguje

2025-11-12 23:37:32 +01:00

semestralka_1c_tx

blbosti

2025-11-18 09:20:57 +01:00

semestralka_1d_rx_bez_dma

working, overhead is down a bit

2025-11-19 17:50:33 +01:00

semestralka_1e_tx_bez_dma

working at the baud rate 600

2025-11-19 21:12:41 +01:00

semestralka_1f_rx_bez_dma_toggle

debugging more

2025-11-18 16:55:42 +01:00

semestralka_1g_empty_toggle

toggle in the interrupt is working

2025-11-19 11:39:55 +01:00

semestralka_1h_empty_toggle_read

toggling bit and reading it now works properly well

2025-11-19 12:11:19 +01:00

semestralka_1i_rx_dma

improved parsing of software uart

2025-11-19 20:40:13 +01:00

semestralka_1j_tx_dma

finished and fully functional

2025-11-19 23:30:55 +01:00

time_meas

…

usart_async_buffered

…

usart_async_buffered_generalized

…

usart_async_buffered_generalized2

moved properly

2025-10-31 13:19:54 +01:00

usart_async_dma

…

usart_blocking

…

.gitignore

Add global target ignore

2025-11-23 16:24:28 +01:00

datasheet.txt

ready for dma implemenatation

2025-10-29 22:48:36 +01:00

flake.lock

…

flake.nix

blbosti

2025-11-18 09:20:57 +01:00

pinout1.png

DMA working

2025-10-29 23:23:20 +01:00

pinout2.png

DMA working

2025-10-29 23:23:20 +01:00

Description

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46 MiB

Languages

Rust 97%

Makefile 2.5%

Nix 0.5%