filipriec/stm32_rust
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

better registers for Rx

Browse Source
This commit is contained in:
Priec
2025-11-12 18:54:42 +01:00
parent 16c66ee1ff
commit a0c30894ee
3 changed files with 25 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

35
semestralka_1b/src/bin/main.rs
View File

@@ -103,13 +103,15 @@ async fn main(spawner: Spawner) {
// Safe one-time init from StaticCell
let sw_rx_ring: &mut [u8; RX_RING_BYTES] = SW_RX_RING.init([0; RX_RING_BYTES]);
let sw_tx_ring: &mut [u32; TX_RING_BYTES] = SW_TX_RING.init([0; TX_RING_BYTES]);
spawner.spawn(rx_dma_task(p.GPDMA1_CH1, sw_rx_ring, &PIPE_SW_RX).unwrap());
// let sw_tx_ring: &mut [u32; TX_RING_BYTES] = SW_TX_RING.init([0; TX_RING_BYTES]);
let gpioc_idr = embassy_stm32::pac::GPIOC.idr().as_ptr() as *mut u8; // POZOR C REGISTER
spawner.spawn(rx_dma_task(p.GPDMA1_CH1, gpioc_idr, sw_rx_ring, &PIPE_SW_RX).unwrap());
// Create and start the TX DMA ring in main.
let bsrr_ptr = embassy_stm32::pac::GPIOA.bsrr().as_ptr() as *mut u32;
let bsrr_ptr = embassy_stm32::pac::GPIOB.bsrr().as_ptr() as *mut u32; // POZOR B REGISTER
// let odr_ptr = embassy_stm32::pac::GPIOA.odr().as_ptr() as *mut u32; // NEEDS DECODE CHANGE
spawner.spawn(tx_dma_task(p.GPDMA1_CH0, bsrr_ptr, sw_tx_ring, &PIPE_SW_TX).unwrap());
// spawner.spawn(tx_dma_task(p.GPDMA1_CH0, bsrr_ptr, sw_tx_ring, &PIPE_SW_TX).unwrap());
// EDN OF SOFTWARE UART
@@ -121,23 +123,24 @@ async fn main(spawner: Spawner) {
// Timer::after(Duration::from_millis(100)).await;
// info!("tick end");
let n1 = PIPE_HW_RX.read(&mut buf).await;
if n1 > 0 {
info!("PC received: {:a}", &buf[..n1]);
let _ = PIPE_SW_TX.write(&buf[..n1]).await;
info!("SW UART TX sent echo: {:a}", &buf[..n1]);
}
yield_now().await;
// let n1 = PIPE_HW_RX.read(&mut buf).await;
// if n1 > 0 {
// info!("PC received: {:a}", &buf[..n1]);
// let _ = PIPE_SW_TX.write(&buf[..n1]).await;
// info!("SW UART TX sent echo: {:a}", &buf[..n1]);
// }
// yield_now().await;
let n2 = PIPE_SW_RX.read(&mut buf).await;
if n2 > 0 {
info!("SW UART RX received: {:a}", &buf[..n2]);
info!("SW UART RX pipe: {:a}", &buf[..n2]);
}
yield_now().await;
if Instant::now().duration_since(last_yield) >= yield_period {
yield_now().await;
last_yield = Instant::now();
}
// if Instant::now().duration_since(last_yield) >= yield_period {
// yield_now().await;
// last_yield = Instant::now();
// }
}
}

6
semestralka_1b/src/config.rs
View File

@@ -4,8 +4,10 @@ use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::pipe::Pipe;
pub const BAUD: u32 = 9_600;
pub const TX_PIN_BIT: u8 = 2; // PA2
pub const RX_PIN_BIT: u8 = 3; // PA3
// pub const TX_PIN_BIT: u8 = 2; // PA2
// pub const RX_PIN_BIT: u8 = 3; // PA3
pub const TX_PIN_BIT: u8 = 0; // PB2
pub const RX_PIN_BIT: u8 = 3; // PC3
pub const TX_OVERSAMPLE: u16 = 1;
pub const RX_OVERSAMPLE: u16 = 16;

5
semestralka_1b/src/software_uart/gpio_dma_uart_rx.rs
View File

@@ -23,17 +23,16 @@ pub const TIM7_UP_REQ: Request = 5;
#[task]
pub async fn rx_dma_task(
ch: Peri<'static, GPDMA1_CH1>,
register: *mut u8,
ring: &'static mut [u8],
pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
) {
let gpioa_idr = embassy_stm32::pac::GPIOA.idr().as_ptr() as *mut u8;
let mut opts = TransferOptions::default();
opts.half_transfer_ir = true;
opts.complete_transfer_ir = true;
// SAFETY: ring is exclusive to this task
let mut rx = unsafe { ReadableRingBuffer::new(ch, TIM7_UP_REQ, gpioa_idr, ring, opts) };
let mut rx = unsafe { ReadableRingBuffer::new(ch, TIM7_UP_REQ, register, ring, opts) };
rx.start();
let mut raw_chunk = [0u8; 256];