-
c60f8db3c8
moves
master
Priec
2025-12-16 00:39:51 +01:00
-
4c7d9af29a
moved handler
Priec
2025-12-15 16:46:10 +01:00
-
88341314dd
cleaning up
Priec
2025-12-15 16:16:46 +01:00
-
053cba171d
sleep
Priec
2025-12-14 15:16:24 +01:00
-
20dfdbc335
wake up pin working for the wake up
Priec
2025-12-14 14:33:01 +01:00
-
f4ca3071f0
exti gpio wake up
Priec
2025-12-14 12:50:21 +01:00
-
bbddc7cf9c
detection of the stop0-2
Priec
2025-12-14 12:01:19 +01:00
-
49cc8dcc71
stop0 working
Priec
2025-12-14 11:56:09 +01:00
-
58561ec392
dumb changes didnt do anything
Priec
2025-12-13 22:31:49 +01:00
-
f36a9fd9e2
scuffed uart print
Priec
2025-12-13 00:55:30 +01:00
-
2c9433cb84
implementation of stops and reorganization of the codebase
Priec
2025-12-12 22:25:36 +01:00
-
72a731abef
stop3 working properly well
Filipriec
2025-12-09 16:02:09 +01:00
-
55398e8459
moved uart to init file, now main is purely about low power modes and sleeps
Priec
2025-12-03 23:03:56 +01:00
-
e2afb2f2f0
redesign
Priec
2025-12-03 23:02:36 +01:00
-
7184ce9898
working uart trigger of standby
Priec
2025-12-03 22:23:41 +01:00
-
c7a74df023
working uart but not waking after sleep
Priec
2025-12-03 21:41:45 +01:00
-
3ebbd97760
improvements to semestralka 2
Priec
2025-12-03 20:20:34 +01:00
-
68d13ebbbc
sram2 standby working
Priec
2025-12-03 18:33:07 +01:00
-
434e2b3d21
shutdown added
Priec
2025-12-03 17:57:10 +01:00
-
33543099c2
split the wakeup now, properly working
Priec
2025-12-03 16:52:30 +01:00
-
9be1d514fb
ready for feature based split
Priec
2025-12-03 13:36:56 +01:00
-
9ab8f94f92
standby from C HAL is working
Priec
2025-12-03 13:05:13 +01:00
-
60d1ae9a45
blinking working
Priec
2025-12-03 11:40:19 +01:00
-
b44ede04cb
not working, fix at home, init hal from C was removed
Filipriec
2025-12-02 18:00:49 +01:00
-
ab932d1698
hal working
Filipriec
2025-12-02 15:40:13 +01:00
-
af781eb1f8
added C hal into the project successfuly
Filipriec
2025-12-02 13:44:47 +01:00
-
f7063f877d
working buffered hardware uart from previous project is now on
Priec
2025-11-29 19:30:13 +01:00
-
9c7f67b071
template for semestralka2
Priec
2025-11-28 19:28:31 +01:00
-
6f27f98a38
final uml
Filipriec
2025-11-25 17:45:39 +01:00
-
a61b808176
finalized plantuml
Filipriec
2025-11-25 15:19:06 +01:00
-
4ff73644c6
uml
Filipriec
2025-11-25 15:10:25 +01:00
-
f6d83a0acc
updated lock file
Filipriec
2025-11-25 07:56:51 +01:00
-
3e2ad6eb7d
timing uml diagrams added
Filipriec
2025-11-24 09:41:46 +01:00
-
6d694c840b
cleanup
Priec
2025-11-24 00:21:58 +01:00
-
522236e20c
removed redundant code
Priec
2025-11-23 23:12:32 +01:00
-
804dc66a4b
sampling only in the middle
Priec
2025-11-23 22:16:36 +01:00
-
9451bc5ae9
timer HAL
Priec
2025-11-23 21:44:01 +01:00
-
e5e4d13ff6
prod1
Priec
2025-11-23 21:02:36 +01:00
-
d0ddea119d
Add global target ignore
Priec
2025-11-23 16:24:28 +01:00
-
348c4e63d9
library now fully functional and working
Priec
2025-11-23 16:01:01 +01:00
-
3218714d8c
software uart lib errors fixed
Priec
2025-11-23 15:54:20 +01:00
-
4097ce1c7a
software uart is now a library
Priec
2025-11-23 15:48:54 +01:00
-
685067a75f
jsut minor changes, UNTESTED DMA TIMER CHANGE
Priec
2025-11-20 13:28:09 +01:00
-
179bec6ed6
finished and fully functional
v1.9.0
Priec
2025-11-19 23:30:55 +01:00
-
8e1c2ec29f
time to do final merge
Priec
2025-11-19 21:46:07 +01:00
-
e569fbc39d
dma used to transfer Tx
Priec
2025-11-19 21:41:08 +01:00
-
24d1da44aa
working at the baud rate 600
Priec
2025-11-19 21:12:41 +01:00
-
ef56483016
improved parsing of software uart
Priec
2025-11-19 20:40:13 +01:00
-
de4e04787b
max frequency fixed it all
Priec
2025-11-19 20:28:24 +01:00
-
78c85c7982
tweaked parameters, storing before increasing frequencies
Priec
2025-11-19 19:43:10 +01:00
-
bf34ff1bcb
faster and smarter DMA
Priec
2025-11-19 18:48:09 +01:00
-
e2378cd436
working with DMA at 9600
Priec
2025-11-19 18:32:18 +01:00
-
110ddc0dcf
working, overhead is down a bit
Priec
2025-11-19 17:50:33 +01:00
-
0cd40eb5e2
uart rx working fully
Priec
2025-11-19 15:59:14 +01:00
-
46486a6e74
working data catch
Priec
2025-11-19 14:51:42 +01:00
-
89ee552da3
working only at 600 baud, we are reading data of the pin in the interrupt
Priec
2025-11-19 14:41:39 +01:00
-
28d041873c
starting fresh again 1d rx bez dma
Priec
2025-11-19 13:03:28 +01:00
-
2ef75c319d
working buffer transfer, lets build from in here
Priec
2025-11-19 12:56:47 +01:00
-
da2f011682
1d needs to be builded again from scratch
Priec
2025-11-19 12:51:45 +01:00
-
b339b34e4d
toggling bit and reading it now works properly well
Priec
2025-11-19 12:11:19 +01:00
-
9c26a0ca81
not working interrupt via tim7 to read data
Priec
2025-11-19 11:57:28 +01:00
-
c5bee53a30
toggle in the interrupt is working
Priec
2025-11-19 11:39:55 +01:00
-
7a8a308620
now im reading proper buffer
Priec
2025-11-18 23:23:33 +01:00
-
516309aed2
proper printing of the pipe_int tx_pipe
Priec
2025-11-18 22:56:28 +01:00
-
45df1e87e4
testing, not owrking 1d yet
Filipriec
2025-11-18 19:39:51 +01:00
-
0a0ff0f38a
debugging more
Filipriec
2025-11-18 16:55:42 +01:00
-
1909497403
hopefuly working CPU transfer to bsrr
Filipriec
2025-11-18 13:36:07 +01:00
-
c01a908b25
cpu polling instead of dma
Priec
2025-11-18 10:29:29 +01:00
-
c0bc36bec2
rx bez dma ready for testing
Priec
2025-11-18 10:12:02 +01:00
-
66c4741afa
blbosti
Priec
2025-11-18 09:20:57 +01:00
-
fa343624e7
tx stale nefunguje
Priec
2025-11-12 23:37:32 +01:00
-
66521896b3
moving things around, time to debug crap out of it
Priec
2025-11-12 19:07:00 +01:00
-
a0c30894ee
better registers for Rx
Priec
2025-11-12 18:54:42 +01:00
-
16c66ee1ff
final debug
Priec
2025-11-12 18:22:07 +01:00
-
8c6f703de9
bridge between usart1 and usart2
Priec
2025-11-12 17:33:34 +01:00
-
05662a45d0
there is some bug
Priec
2025-11-12 16:07:59 +01:00
-
829cff872f
using correct pipes now
Priec
2025-11-12 14:15:33 +01:00
-
2fb198ceb8
fully built, time to make it work
Priec
2025-11-12 13:03:17 +01:00
-
2a97cbbd38
forgotten
Priec
2025-11-11 23:34:48 +01:00
-
a35d1df67f
small naming conventions
Priec
2025-11-11 23:30:03 +01:00
-
c1d0fa9d04
i can read HW uart in the terminal via info
Priec
2025-11-11 22:34:16 +01:00
-
347d10fb27
priec - filip user
Priec
2025-11-11 22:08:59 +01:00
-
19536dde78
compiled hw and sw uart in semestralka
working_dma
Filipriec
2025-11-11 21:39:46 +01:00
-
17c205f23b
adding hardware uart
Filipriec
2025-11-11 17:16:18 +01:00
-
c738fabac7
software rx and tx are now using data, transmitting on the Tx and receiving on the Rx side
Filipriec
2025-11-11 16:15:59 +01:00
-
bc68e30ead
its a separate task now
Filipriec
2025-11-11 16:03:46 +01:00
-
541173bfcb
semestralka joinig all worlds together
Filipriec
2025-11-11 15:51:37 +01:00
-
25c6d3d265
restored Rx ring properly well with the dma_gpio2 initialized
Filipriec
2025-11-10 18:11:28 +01:00
-
f4e59d977b
revert this commit its only to make it work on the notebook
Filipriec
2025-11-10 17:40:23 +01:00
-
fa6b217bc4
working with the dma library
Priec
2025-11-09 21:24:58 +01:00
-
ef98b7e4e9
fixing and working nonstop without timout
Priec
2025-11-09 19:29:49 +01:00
-
6620f9ad2b
working write immidiate
Priec
2025-11-07 21:23:31 +01:00
-
3a2c65f16b
hardfault fixed
dma_pingpong
Priec
2025-11-07 20:04:20 +01:00
-
dd978ec65c
compiled ping pong buffer setup
Filipriec
2025-11-07 19:23:00 +01:00
-
3930716ac3
clean code
Filipriec
2025-11-07 19:22:46 +01:00
-
-
f2fda10c7a
Tx only does not work
not_working_dmaLLI_write_exact
Priec
2025-11-05 21:03:30 +01:00
-
f7fdd72d7f
timer stuff, yield now added, still hard fault error
Priec
2025-11-05 16:38:26 +01:00
-
41c31f6b2a
only improvements
Priec
2025-11-05 14:45:36 +01:00
-
d57d16935d
compiled, config in src/config, but i get hardfault crash at runtime
Priec
2025-11-05 09:44:41 +01:00
-
44f154e289
comment
Filipriec
2025-11-04 22:00:34 +01:00