filipriec/stm32_rust
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  • 416fdb0e7f unused pipe master v1.1.0 Priec 2026-05-28 09:13:09 +02:00
  • a514098d00 level in enum Priec 2026-05-28 08:09:27 +02:00
  • ec72b2dc8f fix pokial 0 a 1 je predefinovana pouzivatelom Priec 2026-05-28 08:02:12 +02:00
  • 8c95b3343d cargo fmt + max size of a payload at send Priec 2026-05-28 07:57:25 +02:00
  • ddef3db5fb pin level agnostic v2sem.sem2 Priec 2026-05-28 07:47:54 +02:00
  • 6334c95e05 final working Priec 2026-05-23 00:14:01 +02:00
  • 92d69e875a manchester is also working now Priec 2026-05-22 23:20:22 +02:00
  • 6dae8c727a nrz and nrzi are working right now Priec 2026-05-22 21:40:58 +02:00
  • cb99c9b89b builded Filipriec 2026-05-18 14:01:51 +02:00
  • c7d790f474 send receive nrz working Priec 2026-05-18 00:04:46 +02:00
  • a93965eccf polish: Priec 2026-05-17 23:09:21 +02:00
  • 22b3b2307d redesign of sent data Priec 2026-05-17 22:47:31 +02:00
  • 5399983dfb split the codebase Priec 2026-05-17 16:26:33 +02:00
  • 34b10426c2 input via exti Priec 2026-05-16 19:15:23 +02:00
  • 89ad23b3a0 trash. not working yet Filipriec 2026-05-12 22:14:02 +02:00
  • d0fd820434 ticker instead of timer Filipriec 2026-05-12 09:35:41 +02:00
  • 8cbd43bc3a send pipe Priec 2026-05-12 00:11:30 +02:00
  • 86032fc821 2sem_2 Filipriec 2026-05-10 14:45:53 +02:00
  • 6992b46ed5 updated flake and sem2 Filipriec 2026-04-28 14:49:48 +02:00
  • 7bd4d6acac working Filipriec 2026-03-10 16:05:32 +01:00
  • 9e90cc7295 hotovka? Filipriec 2026-03-10 15:15:00 +01:00
  • 8d8d3b3341 2 spi Filipriec 2026-03-10 14:03:54 +01:00
  • bdb46a89c1 CMM working now Filipriec 2026-03-03 18:02:57 +01:00
  • 07c0e9501a working without cc Filipriec 2026-03-03 17:57:35 +01:00
  • 9feffc8152 working magnetometer Filipriec 2026-03-03 17:53:40 +01:00
  • 3ba1a3afae needs redesign Filipriec 2026-03-03 16:10:22 +01:00
  • cfc31e428e 2semester hodina 2 Filipriec 2026-03-03 15:47:50 +01:00
  • fae99273c2 2 sem Filipriec 2026-03-03 13:14:56 +01:00
  • adc4d6f29e async working Filipriec 2026-02-24 16:35:30 +01:00
  • 88f2ec3ae9 blocking to async now Filipriec 2026-02-24 15:29:59 +01:00
  • 1b4ddcaf6c druhy semester a nieco s frekvenciou CPU Filipriec 2026-02-24 14:43:50 +01:00
  • c60f8db3c8 moves Priec 2025-12-16 00:39:51 +01:00
  • 4c7d9af29a moved handler Priec 2025-12-15 16:46:10 +01:00
  • 88341314dd cleaning up Priec 2025-12-15 16:16:46 +01:00
  • 053cba171d sleep Priec 2025-12-14 15:16:24 +01:00
  • 20dfdbc335 wake up pin working for the wake up Priec 2025-12-14 14:33:01 +01:00
  • f4ca3071f0 exti gpio wake up Priec 2025-12-14 12:50:21 +01:00
  • bbddc7cf9c detection of the stop0-2 Priec 2025-12-14 12:01:19 +01:00
  • 49cc8dcc71 stop0 working Priec 2025-12-14 11:56:09 +01:00
  • 58561ec392 dumb changes didnt do anything Priec 2025-12-13 22:31:49 +01:00
  • f36a9fd9e2 scuffed uart print Priec 2025-12-13 00:55:30 +01:00
  • 2c9433cb84 implementation of stops and reorganization of the codebase Priec 2025-12-12 22:25:36 +01:00
  • 72a731abef stop3 working properly well Filipriec 2025-12-09 16:02:09 +01:00
  • 55398e8459 moved uart to init file, now main is purely about low power modes and sleeps Priec 2025-12-03 23:03:56 +01:00
  • e2afb2f2f0 redesign Priec 2025-12-03 23:02:36 +01:00
  • 7184ce9898 working uart trigger of standby Priec 2025-12-03 22:23:41 +01:00
  • c7a74df023 working uart but not waking after sleep Priec 2025-12-03 21:41:45 +01:00
  • 3ebbd97760 improvements to semestralka 2 Priec 2025-12-03 20:20:34 +01:00
  • 68d13ebbbc sram2 standby working Priec 2025-12-03 18:33:07 +01:00
  • 434e2b3d21 shutdown added Priec 2025-12-03 17:57:10 +01:00
  • 33543099c2 split the wakeup now, properly working Priec 2025-12-03 16:52:30 +01:00
  • 9be1d514fb ready for feature based split Priec 2025-12-03 13:36:56 +01:00
  • 9ab8f94f92 standby from C HAL is working Priec 2025-12-03 13:05:13 +01:00
  • 60d1ae9a45 blinking working Priec 2025-12-03 11:40:19 +01:00
  • b44ede04cb not working, fix at home, init hal from C was removed Filipriec 2025-12-02 18:00:49 +01:00
  • ab932d1698 hal working Filipriec 2025-12-02 15:40:13 +01:00
  • af781eb1f8 added C hal into the project successfuly Filipriec 2025-12-02 13:44:47 +01:00
  • f7063f877d working buffered hardware uart from previous project is now on Priec 2025-11-29 19:30:13 +01:00
  • 9c7f67b071 template for semestralka2 Priec 2025-11-28 19:28:31 +01:00
  • 6f27f98a38 final uml Filipriec 2025-11-25 17:45:39 +01:00
  • a61b808176 finalized plantuml Filipriec 2025-11-25 15:19:06 +01:00
  • 4ff73644c6 uml Filipriec 2025-11-25 15:10:25 +01:00
  • f6d83a0acc updated lock file Filipriec 2025-11-25 07:56:51 +01:00
  • 3e2ad6eb7d timing uml diagrams added Filipriec 2025-11-24 09:41:46 +01:00
  • 6d694c840b cleanup Priec 2025-11-24 00:21:58 +01:00
  • 522236e20c removed redundant code Priec 2025-11-23 23:12:32 +01:00
  • 804dc66a4b sampling only in the middle Priec 2025-11-23 22:16:36 +01:00
  • 9451bc5ae9 timer HAL Priec 2025-11-23 21:44:01 +01:00
  • e5e4d13ff6 prod1 Priec 2025-11-23 21:02:36 +01:00
  • d0ddea119d Add global target ignore Priec 2025-11-23 16:24:28 +01:00
  • 348c4e63d9 library now fully functional and working Priec 2025-11-23 16:01:01 +01:00
  • 3218714d8c software uart lib errors fixed Priec 2025-11-23 15:54:20 +01:00
  • 4097ce1c7a software uart is now a library Priec 2025-11-23 15:48:54 +01:00
  • 685067a75f jsut minor changes, UNTESTED DMA TIMER CHANGE Priec 2025-11-20 13:28:09 +01:00
  • 179bec6ed6 finished and fully functional v1.9.0 Priec 2025-11-19 23:30:55 +01:00
  • 8e1c2ec29f time to do final merge Priec 2025-11-19 21:46:07 +01:00
  • e569fbc39d dma used to transfer Tx Priec 2025-11-19 21:41:08 +01:00
  • 24d1da44aa working at the baud rate 600 Priec 2025-11-19 21:12:41 +01:00
  • ef56483016 improved parsing of software uart Priec 2025-11-19 20:40:13 +01:00
  • de4e04787b max frequency fixed it all Priec 2025-11-19 20:28:24 +01:00
  • 78c85c7982 tweaked parameters, storing before increasing frequencies Priec 2025-11-19 19:43:10 +01:00
  • bf34ff1bcb faster and smarter DMA Priec 2025-11-19 18:48:09 +01:00
  • e2378cd436 working with DMA at 9600 Priec 2025-11-19 18:32:18 +01:00
  • 110ddc0dcf working, overhead is down a bit Priec 2025-11-19 17:50:33 +01:00
  • 0cd40eb5e2 uart rx working fully Priec 2025-11-19 15:59:14 +01:00
  • 46486a6e74 working data catch Priec 2025-11-19 14:51:42 +01:00
  • 89ee552da3 working only at 600 baud, we are reading data of the pin in the interrupt Priec 2025-11-19 14:41:39 +01:00
  • 28d041873c starting fresh again 1d rx bez dma Priec 2025-11-19 13:03:28 +01:00
  • 2ef75c319d working buffer transfer, lets build from in here Priec 2025-11-19 12:56:47 +01:00
  • da2f011682 1d needs to be builded again from scratch Priec 2025-11-19 12:51:45 +01:00
  • b339b34e4d toggling bit and reading it now works properly well Priec 2025-11-19 12:11:19 +01:00
  • 9c26a0ca81 not working interrupt via tim7 to read data Priec 2025-11-19 11:57:28 +01:00
  • c5bee53a30 toggle in the interrupt is working Priec 2025-11-19 11:39:55 +01:00
  • 7a8a308620 now im reading proper buffer Priec 2025-11-18 23:23:33 +01:00
  • 516309aed2 proper printing of the pipe_int tx_pipe Priec 2025-11-18 22:56:28 +01:00
  • 45df1e87e4 testing, not owrking 1d yet Filipriec 2025-11-18 19:39:51 +01:00
  • 0a0ff0f38a debugging more Filipriec 2025-11-18 16:55:42 +01:00
  • 1909497403 hopefuly working CPU transfer to bsrr Filipriec 2025-11-18 13:36:07 +01:00
  • c01a908b25 cpu polling instead of dma Priec 2025-11-18 10:29:29 +01:00
  • c0bc36bec2 rx bez dma ready for testing Priec 2025-11-18 10:12:02 +01:00