wake up pin working for the wake up

.gitignore

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 *.pdf
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+**/target/
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dma_gpio2/Cargo.lock

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 embedded-graphics = "0.8.1"

external_led_blinky/.cargo/config.toml

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external_led_blinky/LICENSE-APACHE

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+5. Submission of Contributions. Unless You explicitly state otherwise,
+   any Contribution intentionally submitted for inclusion in the Work
+   by You to the Licensor shall be under the terms and conditions of
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+   Notwithstanding the above, nothing herein shall supersede or modify
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+   PARTICULAR PURPOSE. You are solely responsible for determining the
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+   risks associated with Your exercise of permissions under this License.
+
+8. Limitation of Liability. In no event and under no legal theory,
+   whether in tort (including negligence), contract, or otherwise,
+   unless required by applicable law (such as deliberate and grossly
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+   and charge a fee for, acceptance of support, warranty, indemnity,
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+   defend, and hold each Contributor harmless for any liability
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+   of your accepting any such warranty or additional liability.
+
+END OF TERMS AND CONDITIONS
+
+APPENDIX: How to apply the Apache License to your work.
+
+   To apply the Apache License to your work, attach the following
+   boilerplate notice, with the fields enclosed by brackets "[]"
+   replaced with your own identifying information. (Don't include
+   the brackets!)  The text should be enclosed in the appropriate
+   comment syntax for the file format. We also recommend that a
+   file or class name and description of purpose be included on the
+   same "printed page" as the copyright notice for easier
+   identification within third-party archives.
+
+Copyright [yyyy] [name of copyright owner]
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
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+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.

external_led_blinky/LICENSE-MIT

@@ -0,0 +1,23 @@
+Permission is hereby granted, free of charge, to any
+person obtaining a copy of this software and associated
+documentation files (the "Software"), to deal in the
+Software without restriction, including without
+limitation the rights to use, copy, modify, merge,
+publish, distribute, sublicense, and/or sell copies of
+the Software, and to permit persons to whom the Software
+is furnished to do so, subject to the following
+conditions:
+
+The above copyright notice and this permission notice
+shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
+ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
+IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.

external_led_blinky/Makefile

@@ -0,0 +1,20 @@
+TARGET = thumbv8m.main-none-eabihf
+CHIP = STM32U575ZI
+BIN = main
+MODE ?= release
+ELF = target/$(TARGET)/$(MODE)/$(BIN)
+PROBE = probe-rs
+
+.PHONY: all build flash empty
+
+all: build flash
+
+build:
+	cargo build --target $(TARGET) --$(MODE)
+
+flash: build
+	$(PROBE) run --chip $(CHIP) $(ELF)
+
+empty:
+	$(PROBE) erase --chip $(CHIP)
+

external_led_blinky/README.md

@@ -0,0 +1,232 @@
+# `app-template`
+
+> Quickly set up a [`probe-rs`] + [`defmt`] + [`flip-link`] embedded project
+
+[`probe-rs`]: https://crates.io/crates/probe-rs
+[`defmt`]: https://github.com/knurling-rs/defmt
+[`flip-link`]: https://github.com/knurling-rs/flip-link
+
+## Dependencies
+
+### 1. `flip-link`:
+
+```bash
+cargo install flip-link
+```
+
+### 2. `probe-rs`:
+
+Install probe-rs by following the instructions at <https://probe.rs/docs/getting-started/installation/>.
+
+### 3. [`cargo-generate`]:
+
+```bash
+cargo install cargo-generate
+```
+
+[`cargo-generate`]: https://crates.io/crates/cargo-generate
+
+> *Note:* You can also just clone this repository instead of using `cargo-generate`, but this involves additional manual adjustments.
+
+## Setup
+
+### 1. Initialize the project template
+
+```bash
+cargo generate \
+    --git https://github.com/knurling-rs/app-template \
+    --branch main \
+    --name my-app
+```
+
+If you look into your new `my-app` folder, you'll find that there are a few `TODO`s in the files marking the properties you need to set.
+
+Let's walk through them together now.
+
+### 2. Set `probe-rs` chip
+
+Pick a chip from ` probe-rs chip list` and enter it into `.cargo/config.toml`.
+
+If, for example, you have a nRF52840 Development Kit as used in one of [our exercises], replace `{{chip}}` with `nRF52840_xxAA`.
+
+[our workshops]: https://rust-exercises.ferrous-systems.com
+
+```diff
+ # .cargo/config.toml
+-runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format=oneline"]
++runner = ["probe-rs", "run", "--chip", "nRF52840_xxAA", "--log-format=oneline"]
+```
+
+### 3. Adjust the compilation target
+
+In `.cargo/config.toml`, pick the right compilation target for your board.
+
+```diff
+ # .cargo/config.toml
+ [build]
+-target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
+-# target = "thumbv7m-none-eabi"    # Cortex-M3
+-# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
+-# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
++target = "thumbv7em-none-eabihf" # Cortex-M4F (with FPU)
+```
+
+Add the target with `rustup`.
+
+```bash
+rustup target add thumbv7em-none-eabihf
+```
+
+### 4. Add a HAL as a dependency
+
+In `Cargo.toml`, list the Hardware Abstraction Layer (HAL) for your board as a dependency.
+
+For the nRF52840 you'll want to use the [`nrf52840-hal`].
+
+[`nrf52840-hal`]: https://crates.io/crates/nrf52840-hal
+
+```diff
+ # Cargo.toml
+ [dependencies]
+-# some-hal = "1.2.3"
++nrf52840-hal = "0.14.0"
+```
+
+⚠️ Note for RP2040 users ⚠️
+
+You will need to not just specify the `rp-hal` HAL, but a BSP (board support crate) which includes a second stage bootloader. Please find a list of available BSPs [here](https://github.com/rp-rs/rp-hal-boards#packages).
+
+### 5. Import your HAL
+
+Now that you have selected a HAL, fix the HAL import in `src/lib.rs`
+
+```diff
+ // my-app/src/lib.rs
+-// use some_hal as _; // memory layout
++use nrf52840_hal as _; // memory layout
+```
+
+### (6. Get a linker script)
+
+Some HAL crates require that you manually copy over a file called `memory.x` from the HAL to the root of your project. For nrf52840-hal, this is done automatically so no action is needed. For other HAL crates, see their documentation on where to find an example file.
+
+The `memory.x` file should look something like:
+
+```text
+MEMORY
+{
+  FLASH : ORIGIN = 0x00000000, LENGTH = 1024K
+  RAM   : ORIGIN = 0x20000000, LENGTH = 256K
+}
+```
+
+The `memory.x` file is included in the `cortex-m-rt` linker script `link.x`, and so `link.x` is the one you should tell `rustc` to use (see the `.cargo/config.toml` file where we do that).
+
+### 7. Run!
+
+You are now all set to `cargo-run` your first `defmt`-powered application!
+There are some examples in the `src/bin` directory.
+
+Start by `cargo run`-ning `my-app/src/bin/hello.rs`:
+
+```console
+$ # `rb` is an alias for `run --bin`
+$ cargo rb hello
+    Finished `dev` profile [optimized + debuginfo] target(s) in 0.01s
+     Running `probe-rs run --chip nrf52840_xxaa --log-format=oneline target/thumbv6m-none-eabi/debug/hello`
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.79 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+Hello, world!
+
+$ echo $?
+0
+```
+
+If you're running out of memory (`flip-link` bails with an overflow error), you can decrease the size of the device memory buffer by setting the `DEFMT_RTT_BUFFER_SIZE` environment variable. The default value is 1024 bytes, and powers of two should be used for optimal performance:
+
+```console
+$ DEFMT_RTT_BUFFER_SIZE=64 cargo rb hello
+```
+
+### (8. Set `rust-analyzer.linkedProjects`)
+
+If you are using [rust-analyzer] with VS Code for IDE-like features you can add following configuration to your `.vscode/settings.json` to make it work transparently across workspaces. Find the details of this option in the [RA docs].
+
+```json
+{
+    "rust-analyzer.linkedProjects": [
+        "Cargo.toml",
+        "firmware/Cargo.toml",
+    ]
+}
+```
+
+[RA docs]: https://rust-analyzer.github.io/manual.html#configuration
+[rust-analyzer]: https://rust-analyzer.github.io/
+
+## Running tests
+
+The template comes configured for running unit tests and integration tests on the target.
+
+Unit tests reside in the library crate and can test private API; the initial set of unit tests are in `src/lib.rs`.
+`cargo test --lib` will run those unit tests.
+
+```console
+$ cargo test --lib
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.15s
+     Running unittests src/lib.rs (target/thumbv6m-none-eabi/debug/deps/example-2b0d0e25d141bf57)
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.99 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.33 KiB/s (took 1s)                                                                                                                        Finished in 1.10s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Integration tests reside in the `tests` directory; the initial set of integration tests are in `tests/integration.rs`.
+`cargo test --test integration` will run those integration tests.
+Note that the argument of the `--test` flag must match the name of the test file in the `tests` directory.
+
+```console
+$ cargo test --test integration
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.10s
+     Running tests/integration.rs (target/thumbv6m-none-eabi/debug/deps/integration-aaaff41151f6a722)
+      Erasing ✔ 100% [####################]   8.00 KiB @  16.03 KiB/s (took 0s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Note that to add a new test file to the `tests` directory you also need to add a new `[[test]]` section to `Cargo.toml`.
+
+To run all the tests via `cargo test` the tests need to be explicitly disabled for all the existing binary targets.
+See `Cargo.toml` for details on how to do this.
+
+## Support
+
+`app-template` is part of the [Knurling] project, [Ferrous Systems]' effort at
+improving tooling used to develop for embedded systems.
+
+If you think that our work is useful, consider sponsoring it via [GitHub
+Sponsors].
+
+## License
+
+Licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+  http://www.apache.org/licenses/LICENSE-2.0)
+
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+### Contribution
+
+Unless you explicitly state otherwise, any contribution intentionally submitted
+for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
+licensed as above, without any additional terms or conditions.
+
+[Knurling]: https://knurling.ferrous-systems.com
+[Ferrous Systems]: https://ferrous-systems.com/
+[GitHub Sponsors]: https://github.com/sponsors/knurling-rs

external_led_blinky/src/bin/main.rs

@@ -0,0 +1,24 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_stm32::gpio::{Level, Output, Speed};
+use embassy_time::{Duration, Timer};
+use embassy_stm32::init;
+use embassy_stm32::Config;
+use panic_halt as _;
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = init(Config::default());
+
+    let mut output_pin = Output::new(p.PA3, Level::Low, Speed::Low);
+    let mut _artificial_ground = Output::new(p.PB0, Level::Low, Speed::Low);
+
+    loop {
+        output_pin.set_high();
+        Timer::after(Duration::from_millis(500)).await;
+        // output_pin.set_low();
+        Timer::after(Duration::from_millis(500)).await;
+    }
+}

external_led_blinky/src/lib.rs

@@ -0,0 +1 @@
+#![no_std]

flake.nix

@@ -59,6 +59,7 @@
         echo "cargo flash --release --chip STM32U575ZI"
 	echo "cargo run --bin main"
 	echo "probe-rs run --chip STM32U575ZITxQ target/thumbv8m.main-none-eabihf/release/main"
+	echo "probe-rs erase --chip STM32U575ZITxQ"
 	echo "target/**/build/embassy-stm32-*/out/_generated.rs"
       '';
     };

hal_test/src/bin/main.rs

@@ -13,7 +13,7 @@ async fn main(_spawner: Spawner) {
     let p = init(Config::default());
 
     // The user LED on NUCLEO-U575ZI-Q is typically on port B, pin 0 (verify silkscreen)
-    let mut led = Output::new(p.PB0, Level::Low, Speed::Low);
+    let mut led = Output::new(p.PB14, Level::Low, Speed::Low);
 
     loop {
         led.set_high();

semestralka_1/Cargo.lock

@@ -166,6 +166,15 @@ dependencies = [
  "syn 2.0.107",
 ]
 
+[[package]]
+name = "cortex-m-semihosting"
+version = "0.5.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "c23234600452033cc77e4b761e740e02d2c4168e11dbf36ab14a0f58973592b0"
+dependencies = [
+ "cortex-m",
+]
+
 [[package]]
 name = "critical-section"
 version = "1.2.0"
@@ -258,6 +267,29 @@ dependencies = [
  "defmt 1.0.1",
 ]
 
+[[package]]
+name = "defmt-test"
+version = "0.4.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "24076cc7203c365e7febfcec15d6667a9ef780bd2c5fd3b2a197400df78f299b"
+dependencies = [
+ "cortex-m-rt",
+ "cortex-m-semihosting",
+ "defmt 1.0.1",
+ "defmt-test-macros",
+]
+
+[[package]]
+name = "defmt-test-macros"
+version = "0.3.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "fe5520fd36862f281c026abeaab153ebbc001717c29a9b8e5ba9704d8f3a879d"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn 2.0.107",
+]
+
 [[package]]
 name = "dma_gpio"
 version = "0.1.0"
@@ -266,6 +298,7 @@ dependencies = [
  "cortex-m-rt",
  "defmt 1.0.1",
  "defmt-rtt",
+ "defmt-test",
  "embassy-executor",
  "embassy-futures",
  "embassy-hal-internal",

semestralka_1/Cargo.toml

@@ -29,3 +29,18 @@ defmt = "1.0.1"
 static_cell = "2.1.1"
 embedded-io = "0.6.1"
 embedded-io-async = "0.6.1"
+
+[dev-dependencies]
+defmt-test = "0.4.0"
+
+[[test]]
+name = "uart_emulation"
+harness = false
+
+[lib]
+test = false
+
+[[bin]]
+name = "main"
+path = "src/bin/main.rs"
+test = false

semestralka_1/src/bin/main.rs

@@ -5,16 +5,16 @@
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_time::Instant;
+use embassy_executor::task;
 use embassy_stm32::dma::Request;
 use embassy_stm32::gpio::{Input, Output, Level, Pull, Speed};
-use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
 use dma_gpio::software_uart::{
     dma_timer::{init_tim6_for_uart, init_tim7_for_uart},
     gpio_dma_uart_rx::rx_dma_task,
     debug::dump_tim6_regs,
 };
 use dma_gpio::config::{BAUD, RX_OVERSAMPLE, TX_OVERSAMPLE};
-use dma_gpio::config::{TX_RING_BYTES, RX_RING_BYTES, PIPE_RX_SIZE};
+use dma_gpio::config::{TX_RING_BYTES, RX_RING_BYTES};
 use dma_gpio::software_uart::gpio_dma_uart_tx::tx_dma_task;
 use static_cell::StaticCell;
 use embassy_futures::yield_now;
@@ -23,6 +23,8 @@ use dma_gpio::hw_uart_pc::driver::uart_task;
 use embassy_stm32::usart::{BufferedUart, Config, BufferedInterruptHandler};
 use embassy_stm32::peripherals;
 use embassy_stm32::bind_interrupts;
+use dma_gpio::config::{PIPE_HW_TX, PIPE_HW_RX, PIPE_SW_TX, PIPE_SW_RX};
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
 use {defmt_rtt as _, panic_probe as _};
 
 bind_interrupts!(struct Irqs {
@@ -31,9 +33,8 @@ bind_interrupts!(struct Irqs {
 
 // Software uart
 pub const TIM6_UP_REQ: Request = 4;
-static PIPE_RX: Pipe<CriticalSectionRawMutex, PIPE_RX_SIZE> = Pipe::new();
+static SW_TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
-static TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
+static SW_RX_RING: StaticCell<[u8; RX_RING_BYTES]> = StaticCell::new();
-static RX_RING: StaticCell<[u8; RX_RING_BYTES]> = StaticCell::new();
 
 #[embassy_executor::main]
 async fn main(spawner: Spawner) {
@@ -42,9 +43,8 @@ async fn main(spawner: Spawner) {
     info!("init m8");
 
     // HARDWARE UART to the PC
-
     let mut cfg = Config::default();
-    cfg.baudrate = 230_400;
+    cfg.baudrate = BAUD;
     static TX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
     static RX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
     let uart = BufferedUart::new(
@@ -56,8 +56,8 @@ async fn main(spawner: Spawner) {
         Irqs,
         cfg,
     ).unwrap();
-    let (handle, yield_period) = usart1::setup_and_spawn(BAUD);
+    let yield_period = usart1::setup_and_spawn(BAUD);
-    spawner.spawn(uart_task(uart, handle.tx, handle.rx).unwrap());
+    spawner.spawn(uart_task(uart, &PIPE_HW_TX, &PIPE_HW_RX).unwrap());
     // END OF HARDWARE UART to the PC
 
     // SOFTWARE UART 
@@ -68,27 +68,75 @@ async fn main(spawner: Spawner) {
     dump_tim6_regs();
 
     // Safe one-time init from StaticCell
-    let rx_ring: &mut [u8; RX_RING_BYTES] = RX_RING.init([0; RX_RING_BYTES]);
+    let sw_rx_ring: &mut [u8; RX_RING_BYTES] = SW_RX_RING.init([0; RX_RING_BYTES]);
-    let tx_ring_mem: &mut [u32; TX_RING_BYTES] = TX_RING.init([0; TX_RING_BYTES]);
+    let sw_tx_ring: &mut [u32; TX_RING_BYTES] = SW_TX_RING.init([0; TX_RING_BYTES]);
-    spawner.spawn(rx_dma_task(p.GPDMA1_CH1, rx_ring, &PIPE_RX).unwrap());
+    spawner.spawn(rx_dma_task(p.GPDMA1_CH1, sw_rx_ring, &PIPE_SW_RX).unwrap());
 
     // Create and start the TX DMA ring in main.
-    // let bsrr_ptr = embassy_stm32::pac::GPIOA.bsrr().as_ptr() as *mut u32;
+    let bsrr_ptr = embassy_stm32::pac::GPIOA.bsrr().as_ptr() as *mut u32;
-    let odr_ptr = embassy_stm32::pac::GPIOA.odr().as_ptr() as *mut u32;
+    // let odr_ptr = embassy_stm32::pac::GPIOA.odr().as_ptr() as *mut u32; // NEEDS DECODE CHANGE
-    spawner.spawn(tx_dma_task(p.GPDMA1_CH0, odr_ptr, tx_ring_mem, &PIPE_RX).unwrap());
+    spawner.spawn(tx_dma_task(p.GPDMA1_CH0, bsrr_ptr, sw_tx_ring, &PIPE_SW_TX).unwrap());
     // EDN OF SOFTWARE UART 
 
+
+    // BRIDGE
+    spawner.spawn(bridge_hw_to_sw(&PIPE_HW_RX, &PIPE_SW_TX).unwrap());
+    spawner.spawn(bridge_sw_to_hw(&PIPE_SW_RX, &PIPE_HW_TX).unwrap());
+    // END OF BRIDGE
+    
     let mut last_yield = Instant::now();
+    let mut buf = [0u8; 32];
 
     loop {
         info!("tick start");
         // Timer::after(Duration::from_millis(100)).await;
         // info!("tick end");
 
-        if Instant::now().duration_since(last_yield) >= handle.yield_period {
+        let n1 = PIPE_HW_RX.read(&mut buf).await;
-            embassy_futures::yield_now().await;
+        if n1 > 0 {
+            info!("PC received: {:a}", &buf[..n1]);
+            let _ = PIPE_SW_TX.write(&buf[..n1]).await;
+            info!("SW UART TX sent echo: {:a}", &buf[..n1]);
+        }
+        yield_now().await;
+
+        let n2 = PIPE_SW_RX.read(&mut buf).await;
+        if n2 > 0 {
+            info!("SW UART RX received: {:a}", &buf[..n2]);
+        }
+
+        if Instant::now().duration_since(last_yield) >= yield_period {
+            yield_now().await;
             last_yield = Instant::now();
         }
 
     }
 }
+
+#[task]
+pub async fn bridge_hw_to_sw(
+    hw_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+    sw_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut buf = [0u8; 64];
+    loop {
+        let n = hw_rx.read(&mut buf).await;
+        if n > 0 {
+            let _ = sw_tx.write(&buf[..n]).await;
+        }
+    }
+}
+
+#[task]
+pub async fn bridge_sw_to_hw(
+    sw_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+    hw_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut buf = [0u8; 64];
+    loop {
+        let n = sw_rx.read(&mut buf).await;
+        if n > 0 {
+            let _ = hw_tx.write(&buf[..n]).await;
+        }
+    }
+}

semestralka_1/src/config.rs

@@ -1,13 +1,26 @@
 // src/config.rs
 use crate::software_uart::uart_emulation::{Parity, StopBits, UartConfig};
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
 
-pub const BAUD: u32 = 115_200;
+pub const BAUD: u32 = 9_600;
 pub const TX_PIN_BIT: u8 = 2; // PA2
+pub const RX_PIN_BIT: u8 = 3; // PA3
 pub const TX_OVERSAMPLE: u16 = 1;
 pub const RX_OVERSAMPLE: u16 = 16;
+
 pub const RX_RING_BYTES: usize = 4096;
 pub const TX_RING_BYTES: usize = 4096;
-pub const PIPE_RX_SIZE: usize = 256;
+
+pub const PIPE_HW_TX_SIZE: usize = 1024;
+pub const PIPE_HW_RX_SIZE: usize = 1024;
+pub const PIPE_SW_TX_SIZE: usize = 1024;
+pub const PIPE_SW_RX_SIZE: usize = 1024;
+
+pub static PIPE_HW_TX: Pipe<CriticalSectionRawMutex, PIPE_HW_TX_SIZE> = Pipe::new();
+pub static PIPE_HW_RX: Pipe<CriticalSectionRawMutex, PIPE_HW_RX_SIZE> = Pipe::new();
+pub static PIPE_SW_TX: Pipe<CriticalSectionRawMutex, PIPE_SW_TX_SIZE> = Pipe::new();
+pub static PIPE_SW_RX: Pipe<CriticalSectionRawMutex, PIPE_SW_RX_SIZE> = Pipe::new();
 
 pub const UART_CFG: UartConfig = UartConfig {
     data_bits: 8,

semestralka_1/src/hw_uart_pc/driver.rs

@@ -1,20 +1,12 @@
-// src/uart/driver.rs
+// src/hw_uart_pc/driver.rs
 use defmt::unwrap;
 use embassy_futures::select::{select, Either};
 use embassy_stm32::usart::BufferedUart;
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::pipe::Pipe;
-use embassy_time::Duration;
 use embedded_io_async::{Read, Write};
-
 use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
 
-pub struct UartHandle {
-    pub tx: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
-    pub rx: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
-    pub yield_period: Duration,
-}
-
 #[embassy_executor::task]
 pub async fn uart_task(
     mut uart: BufferedUart<'static>,

semestralka_1/src/hw_uart_pc/usart1.rs

@@ -1,24 +1,12 @@
 // src/uart/usart1.rs
 use defmt::info;
-use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
-use embassy_sync::pipe::Pipe;
 use embassy_time::Duration;
 
-use crate::hw_uart_pc::safety::{preflight_and_suggest_yield_period, RX_PIPE_CAP, TX_PIPE_CAP};
+use crate::hw_uart_pc::safety::preflight_and_suggest_yield_period;
-use crate::hw_uart_pc::driver::UartHandle;
 
-// Static pipes and buffers
+pub fn setup_and_spawn(baudrate: u32,) -> Duration {
-static UART1_TX_PIPE: Pipe<CriticalSectionRawMutex, TX_PIPE_CAP> = Pipe::new();
-static UART1_RX_PIPE: Pipe<CriticalSectionRawMutex, RX_PIPE_CAP> = Pipe::new();
-
-pub fn setup_and_spawn(baudrate: u32,) -> (UartHandle, Duration) {
     let yield_period: Duration = preflight_and_suggest_yield_period(baudrate);
     info!("HW USART1 safe");
-    let handle = UartHandle {
-        tx: &UART1_TX_PIPE,
-        rx: &UART1_RX_PIPE,
-        yield_period,
-    };
 
-    (handle, yield_period)
+    yield_period
 }

semestralka_1/src/software_uart/gpio_dma_uart_rx.rs

@@ -5,6 +5,7 @@ use embassy_stm32::{
     peripherals::GPDMA1_CH1,
     Peri,
 };
+use crate::config::RX_PIN_BIT;
 use embassy_stm32::dma::{
     ReadableRingBuffer,
     TransferOptions,
@@ -13,6 +14,7 @@ use crate::config::{RX_OVERSAMPLE, UART_CFG};
 use crate::software_uart::decode_uart_samples;
 use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
 use embassy_futures::yield_now;
+use defmt::info;
 
 // datasheet tabulka 137
 pub const TIM7_UP_REQ: Request = 5;
@@ -22,7 +24,7 @@ pub const TIM7_UP_REQ: Request = 5;
 pub async fn rx_dma_task(
     ch: Peri<'static, GPDMA1_CH1>,
     ring: &'static mut [u8],
-    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 256>,
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
 ) {
     let gpioa_idr = embassy_stm32::pac::GPIOA.idr().as_ptr() as *mut u8;
 
@@ -34,10 +36,25 @@ pub async fn rx_dma_task(
     let mut rx = unsafe { ReadableRingBuffer::new(ch, TIM7_UP_REQ, gpioa_idr, ring, opts) };
     rx.start();
 
-    let mut chunk = [0u8; 256];
+    let mut raw_chunk = [0u8; 256];
+    let mut levels = [0u8; 256];
     loop {
-        let _ = rx.read_exact(&mut chunk).await;
+        info!("rx_dma_task waiting for DMA data...");
-        let decoded = decode_uart_samples(&chunk, RX_OVERSAMPLE, &UART_CFG);
+        let _ = rx.read_exact(&mut raw_chunk).await;
+
+        for (i, b) in raw_chunk.iter().enumerate() {
+            levels[i] = ((*b >> RX_PIN_BIT) & 1) as u8;
+        }
+
+        let decoded = decode_uart_samples(&levels, RX_OVERSAMPLE, &UART_CFG);
+        if !decoded.is_empty() {
+            info!("SW RX raw samples (first 32): {:a}", &levels[..32]);
+            info!(
+                "SW RX decoded {} bytes: {:a}",
+                decoded.len(),
+                decoded.as_slice()
+            );
+        }
         pipe_rx.write(&decoded).await;
         yield_now().await;
     }

semestralka_1/src/software_uart/gpio_dma_uart_tx.rs

@@ -42,9 +42,9 @@ pub async fn encode_uart_frames<'a>(
 #[task]
 pub async fn tx_dma_task(
     ch: Peri<'static, GPDMA1_CH0>,
-    odr_ptr: *mut u32,
+    register: *mut u32, // Either odr or bsrr
     tx_ring_mem: &'static mut [u32],
-    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 256>,
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
 ) {
     let mut tx_opts = TransferOptions::default();
     tx_opts.half_transfer_ir = true;
@@ -55,7 +55,7 @@ pub async fn tx_dma_task(
         WritableRingBuffer::new(
             ch,
             TIM6_UP_REQ,
-            odr_ptr,
+            register,
             tx_ring_mem,
             tx_opts,
         )
@@ -78,6 +78,7 @@ pub async fn tx_dma_task(
         if used > 0 {
             let _ = tx_ring.write_exact(&frame_buf[..used]).await;
         }
+        info!("tx_dma_task wrote {} words", used);
         yield_now().await;
     }
 }

semestralka_1/src/software_uart/uart_emulation.rs

@@ -40,8 +40,8 @@ pub fn encode_uart_byte_cfg(
 ) -> usize {
     // GPIOx_BSRR register str. 636 kap. 13.4.7
     let set_high = |bit: u8| -> u32 { 1u32 << bit };
-    let set_low = |bit: u8| -> u32 { 0 };
+    // let set_low = |bit: u8| -> u32 { 0 }; // ODR
-    // let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) };
+    let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) }; // BSRR
 
     let mut idx = 0usize;
 

semestralka_1/tests/uart_emulation.rs

@@ -0,0 +1,41 @@
+#![no_std]
+#![no_main]
+
+use dma_gpio as _;
+use panic_probe as _;
+use defmt_rtt as _;
+
+#[defmt_test::tests]
+mod tests {
+    use defmt::assert_eq;
+    use dma_gpio::software_uart::uart_emulation::{
+        encode_uart_byte_cfg, UartConfig, Parity, StopBits
+    };
+
+    const TX_PIN_BIT: u8 = 2;
+
+    #[test]
+    fn test_encode_8n1() {
+        let cfg = UartConfig::default();
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(TX_PIN_BIT, 0x55, &cfg, &mut frame);
+        
+        assert_eq!(used, 10);
+        assert_eq!(frame[0], 1u32 << 18); // Start LOW
+        assert_eq!(frame[9], 1u32 << 2);  // Stop HIGH
+    }
+
+    #[test]
+    fn test_encode_parity() {
+        let cfg = UartConfig {
+            data_bits: 8,
+            parity: Parity::Even,
+            stop_bits: StopBits::One,
+        };
+        
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(TX_PIN_BIT, 0x00, &cfg, &mut frame);
+        
+        assert_eq!(used, 11);
+    }
+}

semestralka_1_2hwuart_internal/.cargo/config.toml

@@ -0,0 +1,15 @@
+[build]
+target = "thumbv8m.main-none-eabihf"
+
+[target.thumbv8m.main-none-eabihf]
+runner = "probe-rs run --chip STM32U575ZITxQ"
+
+rustflags = [
+  "-C", "linker=rust-lld",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "link-arg=-Tdefmt.x",
+  "-C", "link-arg=--nmagic",
+]
+
+[package.metadata.cargo-flash]
+chip = "STM32U575ZIT"

semestralka_1_2hwuart_internal/.gitignore

@@ -0,0 +1 @@
+/target

semestralka_1_2hwuart_internal/Cargo.toml

@@ -0,0 +1,45 @@
+[package]
+authors = ["Priec <filippriec@gmail.com>"]
+name = "dma_gpio"
+edition = "2024"
+version = "0.1.0"
+
+
+[dependencies]
+cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.5"
+panic-halt = "1.0.0"
+embassy-executor = { path = "/home/priec/programs/embassy/embassy-executor", features = ["arch-cortex-m", "executor-thread"] }
+embassy-futures = { path = "/home/priec/programs/embassy/embassy-futures" }
+embassy-sync = { path = "/home/priec/programs/embassy/embassy-sync" }
+embassy-time = { path = "/home/priec/programs/embassy/embassy-time", features = ["tick-hz-32_768"] }
+embassy-hal-internal = { path = "/home/priec/programs/embassy/embassy-hal-internal" }
+embassy-usb = { path = "/home/priec/programs/embassy/embassy-usb" }
+embassy-stm32 = { path = "/home/priec/programs/embassy/embassy-stm32", features = ["unstable-pac", "stm32u575zi", "time-driver-tim2", "memory-x", "defmt"] }
+
+embedded-hal = "1.0.0"
+embedded-graphics = "0.8.1"
+heapless = { version = "0.9.1", default-features = false }
+micromath = "2.1.0"
+tinybmp = "0.6.0"
+panic-probe = { version = "1.0.0", features = ["defmt"] }
+defmt-rtt = "1.1.0"
+defmt = "1.0.1"
+static_cell = "2.1.1"
+embedded-io = "0.6.1"
+embedded-io-async = "0.6.1"
+
+[dev-dependencies]
+defmt-test = "0.4.0"
+
+[[test]]
+name = "uart_emulation"
+harness = false
+
+[lib]
+test = false
+
+[[bin]]
+name = "main"
+path = "src/bin/main.rs"
+test = false

semestralka_1_2hwuart_internal/LICENSE-APACHE

@@ -0,0 +1,201 @@
+                              Apache License
+                        Version 2.0, January 2004
+                     http://www.apache.org/licenses/
+
+TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+1. Definitions.
+
+   "License" shall mean the terms and conditions for use, reproduction,
+   and distribution as defined by Sections 1 through 9 of this document.
+
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+
+   "Legal Entity" shall mean the union of the acting entity and all
+   other entities that control, are controlled by, or are under common
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+   outstanding shares, or (iii) beneficial ownership of such entity.
+
+   "You" (or "Your") shall mean an individual or Legal Entity
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+See the License for the specific language governing permissions and
+limitations under the License.

semestralka_1_2hwuart_internal/LICENSE-MIT

@@ -0,0 +1,23 @@
+Permission is hereby granted, free of charge, to any
+person obtaining a copy of this software and associated
+documentation files (the "Software"), to deal in the
+Software without restriction, including without
+limitation the rights to use, copy, modify, merge,
+publish, distribute, sublicense, and/or sell copies of
+the Software, and to permit persons to whom the Software
+is furnished to do so, subject to the following
+conditions:
+
+The above copyright notice and this permission notice
+shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
+ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
+IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.

semestralka_1_2hwuart_internal/Makefile

@@ -0,0 +1,23 @@
+TARGET = thumbv8m.main-none-eabihf
+CHIP = STM32U575ZI
+BIN = stm32u5-blinky
+MODE ?= release
+TARGET_DIR = target/$(TARGET)/$(MODE)
+ELF = $(TARGET_DIR)/$(BIN)
+PROBE = probe-rs
+
+.PHONY: all build flash clean empty
+
+all: build
+
+build:
+	cargo build --$(MODE)
+
+flash: build
+	$(PROBE) run --chip $(CHIP) $(ELF)
+
+empty:
+	$(PROBE) erase --chip $(CHIP)
+
+clean:
+	cargo clean

semestralka_1_2hwuart_internal/README.md

@@ -0,0 +1,232 @@
+# `app-template`
+
+> Quickly set up a [`probe-rs`] + [`defmt`] + [`flip-link`] embedded project
+
+[`probe-rs`]: https://crates.io/crates/probe-rs
+[`defmt`]: https://github.com/knurling-rs/defmt
+[`flip-link`]: https://github.com/knurling-rs/flip-link
+
+## Dependencies
+
+### 1. `flip-link`:
+
+```bash
+cargo install flip-link
+```
+
+### 2. `probe-rs`:
+
+Install probe-rs by following the instructions at <https://probe.rs/docs/getting-started/installation/>.
+
+### 3. [`cargo-generate`]:
+
+```bash
+cargo install cargo-generate
+```
+
+[`cargo-generate`]: https://crates.io/crates/cargo-generate
+
+> *Note:* You can also just clone this repository instead of using `cargo-generate`, but this involves additional manual adjustments.
+
+## Setup
+
+### 1. Initialize the project template
+
+```bash
+cargo generate \
+    --git https://github.com/knurling-rs/app-template \
+    --branch main \
+    --name my-app
+```
+
+If you look into your new `my-app` folder, you'll find that there are a few `TODO`s in the files marking the properties you need to set.
+
+Let's walk through them together now.
+
+### 2. Set `probe-rs` chip
+
+Pick a chip from ` probe-rs chip list` and enter it into `.cargo/config.toml`.
+
+If, for example, you have a nRF52840 Development Kit as used in one of [our exercises], replace `{{chip}}` with `nRF52840_xxAA`.
+
+[our workshops]: https://rust-exercises.ferrous-systems.com
+
+```diff
+ # .cargo/config.toml
+-runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format=oneline"]
++runner = ["probe-rs", "run", "--chip", "nRF52840_xxAA", "--log-format=oneline"]
+```
+
+### 3. Adjust the compilation target
+
+In `.cargo/config.toml`, pick the right compilation target for your board.
+
+```diff
+ # .cargo/config.toml
+ [build]
+-target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
+-# target = "thumbv7m-none-eabi"    # Cortex-M3
+-# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
+-# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
++target = "thumbv7em-none-eabihf" # Cortex-M4F (with FPU)
+```
+
+Add the target with `rustup`.
+
+```bash
+rustup target add thumbv7em-none-eabihf
+```
+
+### 4. Add a HAL as a dependency
+
+In `Cargo.toml`, list the Hardware Abstraction Layer (HAL) for your board as a dependency.
+
+For the nRF52840 you'll want to use the [`nrf52840-hal`].
+
+[`nrf52840-hal`]: https://crates.io/crates/nrf52840-hal
+
+```diff
+ # Cargo.toml
+ [dependencies]
+-# some-hal = "1.2.3"
++nrf52840-hal = "0.14.0"
+```
+
+⚠️ Note for RP2040 users ⚠️
+
+You will need to not just specify the `rp-hal` HAL, but a BSP (board support crate) which includes a second stage bootloader. Please find a list of available BSPs [here](https://github.com/rp-rs/rp-hal-boards#packages).
+
+### 5. Import your HAL
+
+Now that you have selected a HAL, fix the HAL import in `src/lib.rs`
+
+```diff
+ // my-app/src/lib.rs
+-// use some_hal as _; // memory layout
++use nrf52840_hal as _; // memory layout
+```
+
+### (6. Get a linker script)
+
+Some HAL crates require that you manually copy over a file called `memory.x` from the HAL to the root of your project. For nrf52840-hal, this is done automatically so no action is needed. For other HAL crates, see their documentation on where to find an example file.
+
+The `memory.x` file should look something like:
+
+```text
+MEMORY
+{
+  FLASH : ORIGIN = 0x00000000, LENGTH = 1024K
+  RAM   : ORIGIN = 0x20000000, LENGTH = 256K
+}
+```
+
+The `memory.x` file is included in the `cortex-m-rt` linker script `link.x`, and so `link.x` is the one you should tell `rustc` to use (see the `.cargo/config.toml` file where we do that).
+
+### 7. Run!
+
+You are now all set to `cargo-run` your first `defmt`-powered application!
+There are some examples in the `src/bin` directory.
+
+Start by `cargo run`-ning `my-app/src/bin/hello.rs`:
+
+```console
+$ # `rb` is an alias for `run --bin`
+$ cargo rb hello
+    Finished `dev` profile [optimized + debuginfo] target(s) in 0.01s
+     Running `probe-rs run --chip nrf52840_xxaa --log-format=oneline target/thumbv6m-none-eabi/debug/hello`
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.79 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+Hello, world!
+
+$ echo $?
+0
+```
+
+If you're running out of memory (`flip-link` bails with an overflow error), you can decrease the size of the device memory buffer by setting the `DEFMT_RTT_BUFFER_SIZE` environment variable. The default value is 1024 bytes, and powers of two should be used for optimal performance:
+
+```console
+$ DEFMT_RTT_BUFFER_SIZE=64 cargo rb hello
+```
+
+### (8. Set `rust-analyzer.linkedProjects`)
+
+If you are using [rust-analyzer] with VS Code for IDE-like features you can add following configuration to your `.vscode/settings.json` to make it work transparently across workspaces. Find the details of this option in the [RA docs].
+
+```json
+{
+    "rust-analyzer.linkedProjects": [
+        "Cargo.toml",
+        "firmware/Cargo.toml",
+    ]
+}
+```
+
+[RA docs]: https://rust-analyzer.github.io/manual.html#configuration
+[rust-analyzer]: https://rust-analyzer.github.io/
+
+## Running tests
+
+The template comes configured for running unit tests and integration tests on the target.
+
+Unit tests reside in the library crate and can test private API; the initial set of unit tests are in `src/lib.rs`.
+`cargo test --lib` will run those unit tests.
+
+```console
+$ cargo test --lib
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.15s
+     Running unittests src/lib.rs (target/thumbv6m-none-eabi/debug/deps/example-2b0d0e25d141bf57)
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.99 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.33 KiB/s (took 1s)                                                                                                                        Finished in 1.10s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Integration tests reside in the `tests` directory; the initial set of integration tests are in `tests/integration.rs`.
+`cargo test --test integration` will run those integration tests.
+Note that the argument of the `--test` flag must match the name of the test file in the `tests` directory.
+
+```console
+$ cargo test --test integration
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.10s
+     Running tests/integration.rs (target/thumbv6m-none-eabi/debug/deps/integration-aaaff41151f6a722)
+      Erasing ✔ 100% [####################]   8.00 KiB @  16.03 KiB/s (took 0s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Note that to add a new test file to the `tests` directory you also need to add a new `[[test]]` section to `Cargo.toml`.
+
+To run all the tests via `cargo test` the tests need to be explicitly disabled for all the existing binary targets.
+See `Cargo.toml` for details on how to do this.
+
+## Support
+
+`app-template` is part of the [Knurling] project, [Ferrous Systems]' effort at
+improving tooling used to develop for embedded systems.
+
+If you think that our work is useful, consider sponsoring it via [GitHub
+Sponsors].
+
+## License
+
+Licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+  http://www.apache.org/licenses/LICENSE-2.0)
+
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+### Contribution
+
+Unless you explicitly state otherwise, any contribution intentionally submitted
+for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
+licensed as above, without any additional terms or conditions.
+
+[Knurling]: https://knurling.ferrous-systems.com
+[Ferrous Systems]: https://ferrous-systems.com/
+[GitHub Sponsors]: https://github.com/sponsors/knurling-rs

semestralka_1_2hwuart_internal/src/bin/main.rs

@@ -0,0 +1,161 @@
+// src/bin/main.rs
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_time::Instant;
+use embassy_stm32::dma::Request;
+use embassy_stm32::gpio::{Input, Output, Level, Pull, Speed};
+use dma_gpio::software_uart::{
+    dma_timer::{init_tim6_for_uart, init_tim7_for_uart},
+    gpio_dma_uart_rx::rx_dma_task,
+    debug::dump_tim6_regs,
+};
+use dma_gpio::config::{BAUD, RX_OVERSAMPLE, TX_OVERSAMPLE};
+use dma_gpio::config::{TX_RING_BYTES, RX_RING_BYTES};
+use dma_gpio::software_uart::gpio_dma_uart_tx::tx_dma_task;
+use static_cell::StaticCell;
+use embassy_futures::yield_now;
+use dma_gpio::hw_uart_pc::usart1;
+use dma_gpio::hw_uart_pc::driver::uart_task;
+use embassy_stm32::usart::{BufferedUart, Config, BufferedInterruptHandler};
+use embassy_stm32::peripherals;
+use embassy_stm32::bind_interrupts;
+use dma_gpio::config::{PIPE_HW_TX, PIPE_HW_RX, PIPE_SW_TX, PIPE_SW_RX};
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use dma_gpio::hw_uart_internal::usart2;
+use dma_gpio::hw_uart_internal::driver::uart_task as uart_task_internal;
+use dma_gpio::config::{PIPE_INT_TX, PIPE_INT_RX};
+use embassy_time::{Duration, Timer};
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    USART1 => BufferedInterruptHandler<peripherals::USART1>;
+});
+bind_interrupts!(struct Irqs2 {
+    USART2 => BufferedInterruptHandler<peripherals::USART2>;
+});
+
+// Software uart
+pub const TIM6_UP_REQ: Request = 4;
+static SW_TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
+static SW_RX_RING: StaticCell<[u8; RX_RING_BYTES]> = StaticCell::new();
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    info!("boot");
+    let p = embassy_stm32::init(Default::default());
+    info!("init m8");
+
+
+    // HARDWARE UART to the PC
+    let mut cfg = Config::default();
+    cfg.baudrate = BAUD;
+    static TX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
+    static RX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
+    let uart = BufferedUart::new(
+        p.USART1,
+        p.PA10, // RX pin
+        p.PA9,  // TX pin
+        TX_BUF.init([0; 256]),
+        RX_BUF.init([0; 256]),
+        Irqs,
+        cfg,
+    ).unwrap();
+    let yield_period = usart1::setup_and_spawn(BAUD);
+    spawner.spawn(uart_task(uart, &PIPE_HW_TX, &PIPE_HW_RX).unwrap());
+    // END OF HARDWARE UART to the PC
+
+    // INTERNAL HARDWARE UART (USART2)
+    let mut cfg2 = Config::default();
+    cfg2.baudrate = BAUD;
+    static TX_BUF2: StaticCell<[u8; 256]> = StaticCell::new();
+    static RX_BUF2: StaticCell<[u8; 256]> = StaticCell::new();
+
+    let uart2 = BufferedUart::new(
+        p.USART2,
+        p.PA3, // RX
+        p.PA2, // TX
+        TX_BUF2.init([0; 256]),
+        RX_BUF2.init([0; 256]),
+        Irqs2,
+        cfg2,
+    ).unwrap();
+
+    let _ = usart2::setup_and_spawn(BAUD);
+    spawner.spawn(uart_task_internal(uart2, &PIPE_INT_TX, &PIPE_INT_RX).unwrap());
+    info!("USART2 ready");
+    // END OF INTERNAL HARDWARE UART (USART2)
+    
+    // USART1 <-> USART2 bridge
+    spawner.spawn(bridge_usart1_rx_to_usart2_tx(&PIPE_HW_RX, &PIPE_INT_TX).unwrap());
+    spawner.spawn(bridge_usart2_rx_to_usart1_tx(&PIPE_INT_RX, &PIPE_HW_TX).unwrap());
+    info!("USART1 <-> USART2 bridge active");
+    // END OF USART1 <-> USART2 bridge 
+
+    // SOFTWARE UART 
+    // let _rx = Input::new(p.PD6, Pull::Up);
+    let rx_pin = Input::new(p.PD6, Pull::Up);
+    // Configure TX as output (PB0)
+
+    let mut tx_pin = Output::new(p.PB0, Level::High, Speed::VeryHigh);
+    init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE);
+    init_tim7_for_uart(p.TIM7, BAUD, RX_OVERSAMPLE);
+    dump_tim6_regs();
+    // EDN OF SOFTWARE UART
+
+
+    let mut last_yield = Instant::now();
+    let mut buf = [0u8; 32];
+
+    let mut last_state: u8 = 0;
+    loop {
+        // info!("tick start");
+        // Timer::after(Duration::from_millis(100)).await;
+        // info!("tick end");
+
+        // let n1 = PIPE_HW_RX.read(&mut buf).await;
+        // if n1 > 0 {
+        //     info!("PC received: {:a}", &buf[..n1]);
+        //     let _ = PIPE_SW_TX.write(&buf[..n1]).await;
+        //     info!("SW UART TX sent echo: {:a}", &buf[..n1]);
+        // }
+        // yield_now().await;
+
+
+        yield_now().await;
+    }
+}
+
+#[embassy_executor::task]
+pub async fn bridge_usart1_rx_to_usart2_tx(
+    usart1_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+    usart2_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut buf = [0u8; 64];
+    loop {
+        let n = usart1_rx.read(&mut buf).await;
+        if n > 0 {
+            let _ = usart2_tx.write(&buf[..n]).await;
+            info!("bridge: USART1 -> USART2 sent {} bytes", n);
+        }
+        yield_now().await;
+    }
+}
+
+#[embassy_executor::task]
+pub async fn bridge_usart2_rx_to_usart1_tx(
+    usart2_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+    usart1_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut buf = [0u8; 64];
+    loop {
+        let n = usart2_rx.read(&mut buf).await;
+        if n > 0 {
+            let _ = usart1_tx.write(&buf[..n]).await;
+            // info!("bridge: USART2 -> USART1 sent {} bytes", n);
+        }
+        yield_now().await;
+    }
+}

semestralka_1_2hwuart_internal/src/config.rs

@@ -0,0 +1,35 @@
+// src/config.rs
+use crate::software_uart::uart_emulation::{Parity, StopBits, UartConfig};
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+
+pub const BAUD: u32 = 9_600;
+// pub const TX_PIN_BIT: u8 = 2; // PA2
+// pub const RX_PIN_BIT: u8 = 3; // PA3
+pub const TX_PIN_BIT: u8 = 0; // PB2
+pub const RX_PIN_BIT: u8 = 3; // PC3
+pub const TX_OVERSAMPLE: u16 = 1;
+pub const RX_OVERSAMPLE: u16 = 16;
+
+pub const RX_RING_BYTES: usize = 4096;
+pub const TX_RING_BYTES: usize = 4096;
+
+pub const PIPE_HW_TX_SIZE: usize = 1024;
+pub const PIPE_HW_RX_SIZE: usize = 1024;
+pub const PIPE_SW_TX_SIZE: usize = 1024;
+pub const PIPE_SW_RX_SIZE: usize = 1024;
+pub const PIPE_INT_TX_SIZE: usize = 1024;
+pub const PIPE_INT_RX_SIZE: usize = 1024;
+
+pub static PIPE_HW_TX: Pipe<CriticalSectionRawMutex, PIPE_HW_TX_SIZE> = Pipe::new();
+pub static PIPE_HW_RX: Pipe<CriticalSectionRawMutex, PIPE_HW_RX_SIZE> = Pipe::new();
+pub static PIPE_SW_TX: Pipe<CriticalSectionRawMutex, PIPE_SW_TX_SIZE> = Pipe::new();
+pub static PIPE_SW_RX: Pipe<CriticalSectionRawMutex, PIPE_SW_RX_SIZE> = Pipe::new();
+pub static PIPE_INT_TX: Pipe<CriticalSectionRawMutex, PIPE_INT_TX_SIZE> = Pipe::new();
+pub static PIPE_INT_RX: Pipe<CriticalSectionRawMutex, PIPE_INT_RX_SIZE> = Pipe::new();
+
+pub const UART_CFG: UartConfig = UartConfig {
+    data_bits: 8,
+    parity: Parity::None,
+    stop_bits: StopBits::One,
+};

semestralka_1_2hwuart_internal/src/hw_uart_internal/driver.rs

@@ -0,0 +1,41 @@
+// src/hw_uart_internal/driver.rs
+use defmt::unwrap;
+use embassy_futures::select::{select, Either};
+use embassy_stm32::usart::BufferedUart;
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+use embedded_io_async::{Read, Write};
+use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
+use embassy_futures::yield_now;
+
+#[embassy_executor::task]
+pub async fn uart_task(
+    mut uart: BufferedUart<'static>,
+    tx_pipe: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
+    rx_pipe: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
+) {
+    let mut rx_byte = [0u8; 1];
+    let mut tx_buf = [0u8; 64];
+
+    loop {
+        let rx_fut = uart.read(&mut rx_byte);
+        let tx_fut = async {
+            let n = tx_pipe.read(&mut tx_buf).await;
+            n
+        };
+
+        match select(rx_fut, tx_fut).await {
+            // Incoming data from UART hardware
+            Either::First(res) => {
+                if let Ok(_) = res {
+                    let _ = rx_pipe.write(&rx_byte).await;
+                }
+            }
+            // Outgoing data waiting in TX pipe
+            Either::Second(n) => {
+                unwrap!(uart.write(&tx_buf[..n]).await);
+            }
+        }
+        yield_now().await;
+    }
+}

semestralka_1_2hwuart_internal/src/hw_uart_internal/mod.rs

@@ -0,0 +1,4 @@
+// src/hw_uart_internal/mod.rs
+
+pub mod driver;
+pub mod usart2;

semestralka_1_2hwuart_internal/src/hw_uart_internal/usart2.rs

@@ -0,0 +1,11 @@
+// src/hw_uart_internal/usart2.rs
+use defmt::info;
+use embassy_time::Duration;
+
+use crate::hw_uart_pc::safety::preflight_and_suggest_yield_period;
+
+pub fn setup_and_spawn(baudrate: u32) -> Duration {
+    let yield_period = preflight_and_suggest_yield_period(baudrate);
+    info!("HW USART2 safe");
+    yield_period
+}

semestralka_1_2hwuart_internal/src/hw_uart_pc/driver.rs

@@ -0,0 +1,41 @@
+// src/hw_uart_pc/driver.rs
+use defmt::unwrap;
+use embassy_futures::select::{select, Either};
+use embassy_stm32::usart::BufferedUart;
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+use embedded_io_async::{Read, Write};
+use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
+use embassy_futures::yield_now;
+
+#[embassy_executor::task]
+pub async fn uart_task(
+    mut uart: BufferedUart<'static>,
+    tx_pipe: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
+    rx_pipe: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
+) {
+    let mut rx_byte = [0u8; 1];
+    let mut tx_buf = [0u8; 64];
+
+    loop {
+        let rx_fut = uart.read(&mut rx_byte);
+        let tx_fut = async {
+            let n = tx_pipe.read(&mut tx_buf).await;
+            n
+        };
+
+        match select(rx_fut, tx_fut).await {
+            // Incoming data from UART hardware
+            Either::First(res) => {
+                if let Ok(_) = res {
+                    let _ = rx_pipe.write(&rx_byte).await;
+                }
+            }
+            // Outgoing data waiting in TX pipe
+            Either::Second(n) => {
+                unwrap!(uart.write(&tx_buf[..n]).await);
+            }
+        }
+        yield_now().await;
+    }
+}

semestralka_1_2hwuart_internal/src/hw_uart_pc/mod.rs

@@ -0,0 +1,4 @@
+// src/hw_uart_pc/mod.rs
+pub mod driver;
+pub mod usart1;
+pub mod safety;

semestralka_1_2hwuart_internal/src/hw_uart_pc/safety.rs

@@ -0,0 +1,57 @@
+// src/safety.rs
+use defmt::info;
+use embassy_time::Duration;
+
+// ISR RX ring capacity = RX_BUF len
+const ISR_RX_BUF_CAP: usize = 256;
+// Yield 1/2 the time it takes to fill ISR RX ring.
+const YIELD_MARGIN_NUM: u32 = 1;
+const YIELD_MARGIN_DEN: u32 = 2;
+// Ensure RX_PIPE_CAP can hold this.
+const WORST_MAIN_LATENCY_MS: u32 = 20;
+
+pub const TX_PIPE_CAP: usize = 1024;
+pub const RX_PIPE_CAP: usize = 1024;
+
+
+
+/// Perform safety checks and compute yield timing to avoid buffer overflow.
+///
+/// # Panics
+/// Panics if pipe capacities are too small for the configured baud.
+pub fn preflight_and_suggest_yield_period(baud: u32) -> Duration {
+    // Approx bytes per second for 8N1 (10 bits per byte on the wire)
+    let bytes_per_sec = (baud / 10).max(1);
+
+    // Time until ISR RX ring fills, in microseconds.
+    let t_fill_us = (ISR_RX_BUF_CAP as u64) * 1_000_000u64 / (bytes_per_sec as u64);
+
+    // Choose a yield period as a fraction of t_fill.
+    let yield_us = (t_fill_us as u64)
+        .saturating_mul(YIELD_MARGIN_NUM as u64)
+        / (YIELD_MARGIN_DEN as u64);
+
+    // Verify RX pipe can absorb a worst-case app latency so uart_task
+    // can always forward without dropping when it runs.
+    let required_rx_pipe = (bytes_per_sec as u64) * (WORST_MAIN_LATENCY_MS as u64) / 1000;
+
+    if (RX_PIPE_CAP as u64) < required_rx_pipe {
+        core::panic!(
+            "RX pipe too small: have {}B, need >= {}B for {}ms at {} bps",
+            RX_PIPE_CAP, required_rx_pipe, WORST_MAIN_LATENCY_MS, baud
+        );
+    }
+
+    info!(
+        "Preflight: baud={}, rx_isr={}B, rx_pipe={}B, bytes/s={}, t_fill_us={}, yield_us={}",
+        baud,
+        ISR_RX_BUF_CAP,
+        RX_PIPE_CAP,
+        bytes_per_sec,
+        t_fill_us,
+        yield_us
+    );
+
+    // Never choose zero.
+    Duration::from_micros(yield_us.max(1) as u64)
+}

semestralka_1_2hwuart_internal/src/hw_uart_pc/usart1.rs

@@ -0,0 +1,12 @@
+// src/uart/usart1.rs
+use defmt::info;
+use embassy_time::Duration;
+
+use crate::hw_uart_pc::safety::preflight_and_suggest_yield_period;
+
+pub fn setup_and_spawn(baudrate: u32,) -> Duration {
+    let yield_period: Duration = preflight_and_suggest_yield_period(baudrate);
+    info!("HW USART1 safe");
+
+    yield_period
+}

semestralka_1_2hwuart_internal/src/lib.rs

@@ -0,0 +1,6 @@
+#![no_std]
+
+pub mod software_uart;
+pub mod config;
+pub mod hw_uart_pc;
+pub mod hw_uart_internal;

semestralka_1_2hwuart_internal/src/software_uart/debug.rs

@@ -0,0 +1,43 @@
+// src/software_uart/debug.rs
+use defmt::info;
+
+pub fn dump_tim6_regs() {
+    use embassy_stm32::pac::timer::TimBasic;
+    let tim = unsafe { TimBasic::from_ptr(0x4000_1000usize as _) };
+    let sr = tim.sr().read();
+    let dier = tim.dier().read();
+    let cr1 = tim.cr1().read();
+    let arr = tim.arr().read().arr();
+    let psc = tim.psc().read();
+    info!(
+        "TIM6: CR1.CEN={} DIER.UDE={} SR.UIF={} PSC={} ARR={}",
+        cr1.cen(),
+        dier.ude(),
+        sr.uif(),
+        psc,
+        arr
+    );
+}
+
+pub fn dump_dma_ch0_regs() {
+    use embassy_stm32::pac::gpdma::Gpdma;
+    let dma = unsafe { Gpdma::from_ptr(0x4002_0000usize as _) };
+    let ch = dma.ch(0);
+    let cr = ch.cr().read();
+    let tr1 = ch.tr1().read();
+    let tr2 = ch.tr2().read();
+    let br1 = ch.br1().read();
+    info!(
+        "GPDMA1_CH0: EN={} PRIO={} SDW={} DDW={} SINC={} DINC={} REQSEL={} SWREQ={} DREQ={} BNDT={}",
+        cr.en(),
+        cr.prio(),
+        tr1.sdw(),
+        tr1.ddw(),
+        tr1.sinc(),
+        tr1.dinc(),
+        tr2.reqsel(),
+        tr2.swreq(),
+        tr2.dreq(),
+        br1.bndt()
+    );
+}

semestralka_1_2hwuart_internal/src/software_uart/dma_timer.rs

@@ -0,0 +1,58 @@
+// src/dma_timer.rs
+
+use embassy_stm32::{
+    peripherals::{TIM6, TIM7},
+    rcc,
+    timer::low_level::Timer,
+    Peri,
+};
+use core::mem;
+use embassy_stm32::timer::BasicInstance;
+use embassy_stm32::pac::timer::vals::Urs;
+
+/// Initializes TIM6 to tick at `baud * oversample` frequency.
+/// Each TIM6 update event triggers one DMA beat.
+pub fn init_tim6_for_uart<'d>(tim6: Peri<'d, TIM6>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM6>();
+    let ll = Timer::new(tim6);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+/// Initializes TIM7 to tick at `baud * oversample` frequency.
+/// Each TIM7 update event triggers one DMA beat.
+pub fn init_tim7_for_uart<'d>(tim7: Peri<'d, TIM7>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM7>();
+    let ll = Timer::new(tim7);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+// Shared internal helper — identical CR1/ARR setup
+fn configure_basic_timer<T: BasicInstance>(ll: &Timer<'_, T>, baud: u32, oversample: u16) {
+    let f_timer = rcc::frequency::<T>().0;
+    let target = baud.saturating_mul(oversample.max(1) as u32).max(1);
+
+    // Compute ARR (prescaler = 0)
+    let mut arr = (f_timer / target).saturating_sub(1) as u16;
+    if arr == 0 { arr = 1; }
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_cen(false);
+        w.set_opm(false);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+
+    ll.regs_basic().psc().write_value(0u16);
+    ll.regs_basic().arr().write(|w| w.set_arr(arr));
+    ll.regs_basic().dier().modify(|w| w.set_ude(true));
+    ll.regs_basic().egr().write(|w| w.set_ug(true));
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_opm(false);
+        w.set_cen(true);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+}

semestralka_1_2hwuart_internal/src/software_uart/gpio_dma_uart_rx.rs

@@ -0,0 +1,80 @@
+// src/software_uart/runtime.rs
+use embassy_executor::task;
+use embassy_stm32::{
+    dma::Request,
+    peripherals::GPDMA1_CH1,
+    Peri,
+};
+use crate::config::RX_PIN_BIT;
+use embassy_stm32::dma::{
+    ReadableRingBuffer,
+    TransferOptions,
+};
+use crate::config::{RX_OVERSAMPLE, UART_CFG};
+use crate::software_uart::decode_uart_samples;
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use embassy_futures::yield_now;
+use defmt::info;
+
+// datasheet tabulka 137
+pub const TIM7_UP_REQ: Request = 5;
+
+/// RX DMA task: reads GPIO samples paced by TIM7 and fills PIPE_RX
+#[task]
+pub async fn rx_dma_task(
+    ch: Peri<'static, GPDMA1_CH1>,
+    register: *mut u8,
+    ring: &'static mut [u8],
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut opts = TransferOptions::default();
+    opts.half_transfer_ir = true;
+    opts.complete_transfer_ir = true;
+
+    // SAFETY: ring is exclusive to this task
+    let mut rx = unsafe { ReadableRingBuffer::new(ch, TIM7_UP_REQ, register, ring, opts) };
+    rx.start();
+
+    let mut raw_chunk = [0u8; 256];
+    let mut levels = [0u8; 256];
+    let mut last_bytes: [u8; 16] = [0; 16];   // remember previous 16 samples
+    let mut last_value: u8 = 0;              // remember previous single IDR sample (optional)
+
+    loop {
+        let _ = rx.read_exact(&mut raw_chunk).await;
+
+        // If nothing has changed (all bytes same as previous), skip logging
+        if raw_chunk[..16] == last_bytes[..] {
+            continue;
+        }
+
+        // Save for next comparison
+        last_bytes.copy_from_slice(&raw_chunk[..16]);
+        let current_avg = raw_chunk[0];
+
+        // Optionally only if single sample changed
+        if current_avg != last_value {
+            last_value = current_avg;
+
+            info!(
+                "DMA change detected: IDR[0..16]={=[u8]:02X} bit{}={}",
+                &raw_chunk[..16],
+                RX_PIN_BIT,
+                (current_avg >> RX_PIN_BIT) & 1
+            );
+        }
+
+        // Extract logic levels as before
+        for (i, b) in raw_chunk.iter().enumerate() {
+            levels[i] = ((*b >> RX_PIN_BIT) & 1) as u8;
+        }
+
+        let decoded = decode_uart_samples(&levels, RX_OVERSAMPLE, &UART_CFG);
+        if !decoded.is_empty() {
+            info!("SW RX decoded {:a}", decoded.as_slice());
+            pipe_rx.write(&decoded).await;
+        }
+
+        yield_now().await;
+    }
+}

semestralka_1_2hwuart_internal/src/software_uart/gpio_dma_uart_tx.rs

@@ -0,0 +1,84 @@
+// src/software_uart/gpio_dma_uart_tx.rs
+use embassy_executor::task;
+use embassy_stm32::{
+    dma::{Request, TransferOptions, WritableRingBuffer},
+    peripherals::GPDMA1_CH0,
+    Peri,
+};
+use embassy_futures::yield_now;
+use defmt::info;
+
+use embassy_sync::pipe::Pipe;
+use crate::config::{TX_PIN_BIT, UART_CFG};
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use crate::software_uart::uart_emulation::encode_uart_byte_cfg;
+
+pub const TIM6_UP_REQ: Request = 4;
+
+pub async fn encode_uart_frames<'a>(
+    pin_bit: u8,
+    bytes: &[u8],
+    out_buf: &'a mut [u32],
+) -> usize {
+    let mut offset = 0;
+    for &b in bytes {
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(pin_bit, b, &UART_CFG, &mut frame);
+
+        if offset + used <= out_buf.len() {
+            out_buf[offset..offset + used].copy_from_slice(&frame[..used]);
+            offset += used;
+        } else {
+            break;
+        }
+
+        // cooperative async yield
+        yield_now().await;
+    }
+    offset
+}
+
+/// TX DMA task: encodes UART frames and sends them via DMA at TIM6 rate
+#[task]
+pub async fn tx_dma_task(
+    ch: Peri<'static, GPDMA1_CH0>,
+    register: *mut u32, // Either odr or bsrr
+    tx_ring_mem: &'static mut [u32],
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut tx_opts = TransferOptions::default();
+    tx_opts.half_transfer_ir = true;
+    tx_opts.complete_transfer_ir = true;
+
+    // SAFETY: tx_ring is exclusive to this task
+    let mut tx_ring = unsafe {
+        WritableRingBuffer::new(
+            ch,
+            TIM6_UP_REQ,
+            register,
+            tx_ring_mem,
+            tx_opts,
+        )
+    };
+
+    tx_ring.start();
+    info!("TX DMA ring started");
+
+    let mut frame_buf = [0u32; 4096];
+    let mut rx_buf = [0u8; 256];
+
+    loop {
+        let n = pipe_rx.read(&mut rx_buf).await;
+        if n == 0 {
+            yield_now().await;
+            continue;
+        }
+
+        let used = encode_uart_frames(TX_PIN_BIT, &rx_buf[..n], &mut frame_buf).await;
+        if used > 0 {
+            let _ = tx_ring.write_exact(&frame_buf[..used]).await;
+        }
+        info!("tx_dma_task wrote {} words", used);
+        yield_now().await;
+    }
+}

semestralka_1_2hwuart_internal/src/software_uart/mod.rs

@@ -0,0 +1,13 @@
+// src/software_uart/mod.rs
+
+pub mod gpio_dma_uart_tx;
+pub mod gpio_dma_uart_rx;
+pub mod dma_timer;
+pub mod uart_emulation;
+pub mod debug;
+
+pub use gpio_dma_uart_tx::*;
+pub use gpio_dma_uart_rx::*;
+pub use dma_timer::*;
+pub use uart_emulation::*;
+pub use debug::*;

semestralka_1_2hwuart_internal/src/software_uart/uart_emulation.rs

@@ -0,0 +1,151 @@
+// src/software_uart/uart_emulation.rs
+use heapless::Vec;
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Parity {
+    None,
+    Even,
+    Odd,
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum StopBits {
+    One,
+    Two,
+}
+
+#[derive(Clone, Copy, Debug)]
+pub struct UartConfig {
+    pub data_bits: u8,
+    pub parity: Parity,
+    pub stop_bits: StopBits,
+}
+
+impl Default for UartConfig {
+    fn default() -> Self {
+        Self {
+            data_bits: 8,
+            parity: Parity::None,
+            stop_bits: StopBits::One,
+        }
+    }
+}
+
+/// Encodes one byte into a sequence of GPIO BSRR words
+pub fn encode_uart_byte_cfg(
+    pin_bit: u8,
+    data: u8,
+    cfg: &UartConfig,
+    out: &mut [u32; 12],
+) -> usize {
+    // GPIOx_BSRR register str. 636 kap. 13.4.7
+    let set_high = |bit: u8| -> u32 { 1u32 << bit };
+    // let set_low = |bit: u8| -> u32 { 0 }; // ODR
+    let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) }; // BSRR
+
+    let mut idx = 0usize;
+
+    // START bit (LOW)
+    out[idx] = set_low(pin_bit);
+    idx += 1;
+
+    // Data bits, LSB-first
+    let nbits = cfg.data_bits.clamp(5, 8);
+    for i in 0..nbits {
+        let one = ((data >> i) & 1) != 0;
+        out[idx] = if one { set_high(pin_bit) } else { set_low(pin_bit) };
+        idx += 1;
+    }
+
+    // Parity
+    match cfg.parity {
+        Parity::None => {}
+        Parity::Even | Parity::Odd => {
+            let mask: u8 = if nbits == 8 { 0xFF } else { (1u16 << nbits) as u8 - 1 };
+            let ones = (data & mask).count_ones() & 1;
+            let par_bit_is_one = match cfg.parity {
+                Parity::Even => ones == 1,
+                Parity::Odd => ones == 0,
+                _ => false,
+            };
+            out[idx] = if par_bit_is_one {
+                set_high(pin_bit)
+            } else {
+                set_low(pin_bit)
+            };
+            idx += 1;
+        }
+    }
+
+    // STOP bits (HIGH)
+    let stop_ticks = match cfg.stop_bits {
+        StopBits::One => 1usize,
+        StopBits::Two => 2usize,
+    };
+    for _ in 0..stop_ticks {
+        out[idx] = set_high(pin_bit);
+        idx += 1;
+    }
+
+    idx
+}
+
+/// Decode an oversampled stream of logic levels into UART bytes.
+pub fn decode_uart_samples(
+    samples: &[u8],
+    oversample: u16,
+    cfg: &UartConfig,
+) -> heapless::Vec<u8, 256> {
+
+    let mut out = Vec::<u8, 256>::new();
+    let mut idx = 0usize;
+    let nbits = cfg.data_bits as usize;
+
+    while idx + (oversample as usize * (nbits + 3)) < samples.len() {
+        // Wait for start bit (falling edge: high -> low)
+        if samples[idx] != 0 && samples[idx + 1] == 0 {
+            // Align to middle of start bit
+            idx += (oversample / 2) as usize;
+
+            // Sanity check start bit really low
+            if samples.get(idx).copied().unwrap_or(1) != 0 {
+                idx += 1;
+                continue;
+            }
+
+            // Sample data bits
+            let mut data: u8 = 0;
+            for bit in 0..nbits {
+                idx += oversample as usize;
+                let bit_val = samples
+                    .get(idx)
+                    .map(|&b| if b != 0 { 1u8 } else { 0u8 })
+                    .unwrap_or(1);
+                data |= bit_val << bit;
+            }
+
+            // Parity: skip / verify
+            match cfg.parity {
+                Parity::None => {}
+                Parity::Even | Parity::Odd => {
+                    idx += oversample as usize;
+                    // You can optionally add parity check here if needed
+                }
+            }
+
+            // Move past stop bits
+            let stop_skip = match cfg.stop_bits {
+                StopBits::One => oversample as usize,
+                StopBits::Two => (oversample * 2) as usize,
+            };
+            idx += stop_skip;
+
+            // Push decoded byte
+            let _ = out.push(data);
+        } else {
+            idx += 1;
+        }
+    }
+
+    out
+}

semestralka_1_2hwuart_internal/tests/uart_emulation.rs

@@ -0,0 +1,41 @@
+#![no_std]
+#![no_main]
+
+use dma_gpio as _;
+use panic_probe as _;
+use defmt_rtt as _;
+
+#[defmt_test::tests]
+mod tests {
+    use defmt::assert_eq;
+    use dma_gpio::software_uart::uart_emulation::{
+        encode_uart_byte_cfg, UartConfig, Parity, StopBits
+    };
+
+    const TX_PIN_BIT: u8 = 2;
+
+    #[test]
+    fn test_encode_8n1() {
+        let cfg = UartConfig::default();
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(TX_PIN_BIT, 0x55, &cfg, &mut frame);
+        
+        assert_eq!(used, 10);
+        assert_eq!(frame[0], 1u32 << 18); // Start LOW
+        assert_eq!(frame[9], 1u32 << 2);  // Stop HIGH
+    }
+
+    #[test]
+    fn test_encode_parity() {
+        let cfg = UartConfig {
+            data_bits: 8,
+            parity: Parity::Even,
+            stop_bits: StopBits::One,
+        };
+        
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(TX_PIN_BIT, 0x00, &cfg, &mut frame);
+        
+        assert_eq!(used, 11);
+    }
+}

semestralka_1_connected/.cargo/config.toml

@@ -0,0 +1,15 @@
+[build]
+target = "thumbv8m.main-none-eabihf"
+
+[target.thumbv8m.main-none-eabihf]
+runner = "probe-rs run --chip STM32U575ZITxQ"
+
+rustflags = [
+  "-C", "linker=rust-lld",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "link-arg=-Tdefmt.x",
+  "-C", "link-arg=--nmagic",
+]
+
+[package.metadata.cargo-flash]
+chip = "STM32U575ZIT"

semestralka_1_connected/.gitignore

@@ -0,0 +1 @@
+/target

semestralka_1_connected/Cargo.toml

@@ -0,0 +1,49 @@
+[package]
+authors = ["Priec <filippriec@gmail.com>"]
+name = "dma_gpio"
+edition = "2024"
+version = "0.1.0"
+
+
+[dependencies]
+cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.5"
+panic-halt = "1.0.0"
+embassy-executor = { path = "/home/priec/programs/embassy/embassy-executor", features = ["arch-cortex-m", "executor-thread"] }
+embassy-futures = { path = "/home/priec/programs/embassy/embassy-futures" }
+embassy-sync = { path = "/home/priec/programs/embassy/embassy-sync" }
+embassy-time = { path = "/home/priec/programs/embassy/embassy-time", features = ["tick-hz-32_768"] }
+embassy-hal-internal = { path = "/home/priec/programs/embassy/embassy-hal-internal" }
+embassy-usb = { path = "/home/priec/programs/embassy/embassy-usb" }
+embassy-stm32 = { path = "/home/priec/programs/embassy/embassy-stm32", features = ["unstable-pac", "stm32u575zi", "time-driver-tim2", "memory-x", "defmt"] }
+
+embedded-hal = "1.0.0"
+embedded-graphics = "0.8.1"
+heapless = { version = "0.9.1", default-features = false }
+micromath = "2.1.0"
+tinybmp = "0.6.0"
+panic-probe = { version = "1.0.0", features = ["defmt"] }
+defmt-rtt = "1.1.0"
+defmt = "1.0.1"
+static_cell = "2.1.1"
+embedded-io = "0.6.1"
+embedded-io-async = "0.6.1"
+
+[dev-dependencies]
+defmt-test = "0.4.0"
+
+[[test]]
+name = "uart_emulation"
+harness = false
+
+[lib]
+test = false
+
+[[bin]]
+name = "main"
+path = "src/bin/main.rs"
+test = false
+
+[profile.dev]
+opt-level = 3
+codegen-units = 1

semestralka_1_connected/LICENSE-APACHE

@@ -0,0 +1,201 @@
+                              Apache License
+                        Version 2.0, January 2004
+                     http://www.apache.org/licenses/
+
+TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+1. Definitions.
+
+   "License" shall mean the terms and conditions for use, reproduction,
+   and distribution as defined by Sections 1 through 9 of this document.
+
+   "Licensor" shall mean the copyright owner or entity authorized by
+   the copyright owner that is granting the License.
+
+   "Legal Entity" shall mean the union of the acting entity and all
+   other entities that control, are controlled by, or are under common
+   control with that entity. For the purposes of this definition,
+   "control" means (i) the power, direct or indirect, to cause the
+   direction or management of such entity, whether by contract or
+   otherwise, or (ii) ownership of fifty percent (50%) or more of the
+   outstanding shares, or (iii) beneficial ownership of such entity.
+
+   "You" (or "Your") shall mean an individual or Legal Entity
+   exercising permissions granted by this License.
+
+   "Source" form shall mean the preferred form for making modifications,
+   including but not limited to software source code, documentation
+   source, and configuration files.
+
+   "Object" form shall mean any form resulting from mechanical
+   transformation or translation of a Source form, including but
+   not limited to compiled object code, generated documentation,
+   and conversions to other media types.
+
+   "Work" shall mean the work of authorship, whether in Source or
+   Object form, made available under the License, as indicated by a
+   copyright notice that is included in or attached to the work
+   (an example is provided in the Appendix below).
+
+   "Derivative Works" shall mean any work, whether in Source or Object
+   form, that is based on (or derived from) the Work and for which the
+   editorial revisions, annotations, elaborations, or other modifications
+   represent, as a whole, an original work of authorship. For the purposes
+   of this License, Derivative Works shall not include works that remain
+   separable from, or merely link (or bind by name) to the interfaces of,
+   the Work and Derivative Works thereof.
+
+   "Contribution" shall mean any work of authorship, including
+   the original version of the Work and any modifications or additions
+   to that Work or Derivative Works thereof, that is intentionally
+   submitted to Licensor for inclusion in the Work by the copyright owner
+   or by an individual or Legal Entity authorized to submit on behalf of
+   the copyright owner. For the purposes of this definition, "submitted"
+   means any form of electronic, verbal, or written communication sent
+   to the Licensor or its representatives, including but not limited to
+   communication on electronic mailing lists, source code control systems,
+   and issue tracking systems that are managed by, or on behalf of, the
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+limitations under the License.

semestralka_1_connected/LICENSE-MIT

@@ -0,0 +1,23 @@
+Permission is hereby granted, free of charge, to any
+person obtaining a copy of this software and associated
+documentation files (the "Software"), to deal in the
+Software without restriction, including without
+limitation the rights to use, copy, modify, merge,
+publish, distribute, sublicense, and/or sell copies of
+the Software, and to permit persons to whom the Software
+is furnished to do so, subject to the following
+conditions:
+
+The above copyright notice and this permission notice
+shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
+ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
+IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.

semestralka_1_connected/Makefile

@@ -0,0 +1,23 @@
+TARGET = thumbv8m.main-none-eabihf
+CHIP = STM32U575ZI
+BIN = stm32u5-blinky
+MODE ?= release
+TARGET_DIR = target/$(TARGET)/$(MODE)
+ELF = $(TARGET_DIR)/$(BIN)
+PROBE = probe-rs
+
+.PHONY: all build flash clean empty
+
+all: build
+
+build:
+	cargo build --$(MODE)
+
+flash: build
+	$(PROBE) run --chip $(CHIP) $(ELF)
+
+empty:
+	$(PROBE) erase --chip $(CHIP)
+
+clean:
+	cargo clean

semestralka_1_connected/README.md

@@ -0,0 +1,232 @@
+# `app-template`
+
+> Quickly set up a [`probe-rs`] + [`defmt`] + [`flip-link`] embedded project
+
+[`probe-rs`]: https://crates.io/crates/probe-rs
+[`defmt`]: https://github.com/knurling-rs/defmt
+[`flip-link`]: https://github.com/knurling-rs/flip-link
+
+## Dependencies
+
+### 1. `flip-link`:
+
+```bash
+cargo install flip-link
+```
+
+### 2. `probe-rs`:
+
+Install probe-rs by following the instructions at <https://probe.rs/docs/getting-started/installation/>.
+
+### 3. [`cargo-generate`]:
+
+```bash
+cargo install cargo-generate
+```
+
+[`cargo-generate`]: https://crates.io/crates/cargo-generate
+
+> *Note:* You can also just clone this repository instead of using `cargo-generate`, but this involves additional manual adjustments.
+
+## Setup
+
+### 1. Initialize the project template
+
+```bash
+cargo generate \
+    --git https://github.com/knurling-rs/app-template \
+    --branch main \
+    --name my-app
+```
+
+If you look into your new `my-app` folder, you'll find that there are a few `TODO`s in the files marking the properties you need to set.
+
+Let's walk through them together now.
+
+### 2. Set `probe-rs` chip
+
+Pick a chip from ` probe-rs chip list` and enter it into `.cargo/config.toml`.
+
+If, for example, you have a nRF52840 Development Kit as used in one of [our exercises], replace `{{chip}}` with `nRF52840_xxAA`.
+
+[our workshops]: https://rust-exercises.ferrous-systems.com
+
+```diff
+ # .cargo/config.toml
+-runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format=oneline"]
++runner = ["probe-rs", "run", "--chip", "nRF52840_xxAA", "--log-format=oneline"]
+```
+
+### 3. Adjust the compilation target
+
+In `.cargo/config.toml`, pick the right compilation target for your board.
+
+```diff
+ # .cargo/config.toml
+ [build]
+-target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
+-# target = "thumbv7m-none-eabi"    # Cortex-M3
+-# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
+-# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
++target = "thumbv7em-none-eabihf" # Cortex-M4F (with FPU)
+```
+
+Add the target with `rustup`.
+
+```bash
+rustup target add thumbv7em-none-eabihf
+```
+
+### 4. Add a HAL as a dependency
+
+In `Cargo.toml`, list the Hardware Abstraction Layer (HAL) for your board as a dependency.
+
+For the nRF52840 you'll want to use the [`nrf52840-hal`].
+
+[`nrf52840-hal`]: https://crates.io/crates/nrf52840-hal
+
+```diff
+ # Cargo.toml
+ [dependencies]
+-# some-hal = "1.2.3"
++nrf52840-hal = "0.14.0"
+```
+
+⚠️ Note for RP2040 users ⚠️
+
+You will need to not just specify the `rp-hal` HAL, but a BSP (board support crate) which includes a second stage bootloader. Please find a list of available BSPs [here](https://github.com/rp-rs/rp-hal-boards#packages).
+
+### 5. Import your HAL
+
+Now that you have selected a HAL, fix the HAL import in `src/lib.rs`
+
+```diff
+ // my-app/src/lib.rs
+-// use some_hal as _; // memory layout
++use nrf52840_hal as _; // memory layout
+```
+
+### (6. Get a linker script)
+
+Some HAL crates require that you manually copy over a file called `memory.x` from the HAL to the root of your project. For nrf52840-hal, this is done automatically so no action is needed. For other HAL crates, see their documentation on where to find an example file.
+
+The `memory.x` file should look something like:
+
+```text
+MEMORY
+{
+  FLASH : ORIGIN = 0x00000000, LENGTH = 1024K
+  RAM   : ORIGIN = 0x20000000, LENGTH = 256K
+}
+```
+
+The `memory.x` file is included in the `cortex-m-rt` linker script `link.x`, and so `link.x` is the one you should tell `rustc` to use (see the `.cargo/config.toml` file where we do that).
+
+### 7. Run!
+
+You are now all set to `cargo-run` your first `defmt`-powered application!
+There are some examples in the `src/bin` directory.
+
+Start by `cargo run`-ning `my-app/src/bin/hello.rs`:
+
+```console
+$ # `rb` is an alias for `run --bin`
+$ cargo rb hello
+    Finished `dev` profile [optimized + debuginfo] target(s) in 0.01s
+     Running `probe-rs run --chip nrf52840_xxaa --log-format=oneline target/thumbv6m-none-eabi/debug/hello`
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.79 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+Hello, world!
+
+$ echo $?
+0
+```
+
+If you're running out of memory (`flip-link` bails with an overflow error), you can decrease the size of the device memory buffer by setting the `DEFMT_RTT_BUFFER_SIZE` environment variable. The default value is 1024 bytes, and powers of two should be used for optimal performance:
+
+```console
+$ DEFMT_RTT_BUFFER_SIZE=64 cargo rb hello
+```
+
+### (8. Set `rust-analyzer.linkedProjects`)
+
+If you are using [rust-analyzer] with VS Code for IDE-like features you can add following configuration to your `.vscode/settings.json` to make it work transparently across workspaces. Find the details of this option in the [RA docs].
+
+```json
+{
+    "rust-analyzer.linkedProjects": [
+        "Cargo.toml",
+        "firmware/Cargo.toml",
+    ]
+}
+```
+
+[RA docs]: https://rust-analyzer.github.io/manual.html#configuration
+[rust-analyzer]: https://rust-analyzer.github.io/
+
+## Running tests
+
+The template comes configured for running unit tests and integration tests on the target.
+
+Unit tests reside in the library crate and can test private API; the initial set of unit tests are in `src/lib.rs`.
+`cargo test --lib` will run those unit tests.
+
+```console
+$ cargo test --lib
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.15s
+     Running unittests src/lib.rs (target/thumbv6m-none-eabi/debug/deps/example-2b0d0e25d141bf57)
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.99 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.33 KiB/s (took 1s)                                                                                                                        Finished in 1.10s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Integration tests reside in the `tests` directory; the initial set of integration tests are in `tests/integration.rs`.
+`cargo test --test integration` will run those integration tests.
+Note that the argument of the `--test` flag must match the name of the test file in the `tests` directory.
+
+```console
+$ cargo test --test integration
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.10s
+     Running tests/integration.rs (target/thumbv6m-none-eabi/debug/deps/integration-aaaff41151f6a722)
+      Erasing ✔ 100% [####################]   8.00 KiB @  16.03 KiB/s (took 0s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Note that to add a new test file to the `tests` directory you also need to add a new `[[test]]` section to `Cargo.toml`.
+
+To run all the tests via `cargo test` the tests need to be explicitly disabled for all the existing binary targets.
+See `Cargo.toml` for details on how to do this.
+
+## Support
+
+`app-template` is part of the [Knurling] project, [Ferrous Systems]' effort at
+improving tooling used to develop for embedded systems.
+
+If you think that our work is useful, consider sponsoring it via [GitHub
+Sponsors].
+
+## License
+
+Licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+  http://www.apache.org/licenses/LICENSE-2.0)
+
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+### Contribution
+
+Unless you explicitly state otherwise, any contribution intentionally submitted
+for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
+licensed as above, without any additional terms or conditions.
+
+[Knurling]: https://knurling.ferrous-systems.com
+[Ferrous Systems]: https://ferrous-systems.com/
+[GitHub Sponsors]: https://github.com/sponsors/knurling-rs

semestralka_1_connected/src/bin/main.rs

@@ -0,0 +1,190 @@
+// src/bin/main.rs
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use core::cell::RefCell;
+use cortex_m::interrupt::Mutex;
+use embassy_executor::Spawner;
+use embassy_futures::yield_now;
+use embassy_sync::{
+    blocking_mutex::raw::CriticalSectionRawMutex,
+    channel::Channel,
+    pipe::Pipe,
+};
+use embassy_time::{Duration, Instant, Timer};
+use embassy_stm32::{
+    bind_interrupts,
+    dma::Request,
+    gpio::{Input, Level, Output, Pull, Speed},
+    interrupt,
+    pac,
+    peripherals,
+    rcc::{self, Pll, PllDiv, PllMul, PllPreDiv, PllSource, Sysclk},
+    usart::{BufferedInterruptHandler, BufferedUart, Config},
+    Config as CPUConfig,
+};
+use static_cell::StaticCell;
+use dma_gpio::config::{
+    BAUD, PIPE_HW_RX, PIPE_HW_TX, PIPE_INT_RX, PIPE_INT_TX, PIPE_SW_RX,
+    PIPE_SW_TX, RX_OVERSAMPLE, RX_RING_BYTES, TX_OVERSAMPLE, TX_RING_BYTES,
+    UART_CFG,
+};
+use dma_gpio::hw_uart_pc::{driver::uart_task, usart1};
+use dma_gpio::hw_uart_internal::{
+    driver::uart_task as uart_task_internal,
+    usart2,
+};
+use dma_gpio::software_uart::{
+    debug::dump_tim6_regs,
+    decode_uart_samples,
+    dma_timer::{init_tim6_for_uart, init_tim7_for_uart},
+    gpio_dma_uart_rx::rx_dma_task,
+    gpio_dma_uart_tx::tx_dma_task,
+};
+use {defmt_rtt as _, panic_probe as _};
+
+static PD6_BITS: Channel<CriticalSectionRawMutex, u8, 16384> = Channel::new();
+
+bind_interrupts!(struct Irqs {
+    USART1 => BufferedInterruptHandler<peripherals::USART1>;
+});
+bind_interrupts!(struct Irqs2 {
+    USART2 => BufferedInterruptHandler<peripherals::USART2>;
+});
+
+// Software uart
+pub const TIM6_UP_REQ: Request = 4;
+static SW_TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
+static SW_RX_RING: StaticCell<[u8; RX_RING_BYTES]> = StaticCell::new();
+static mut RX_PIN: Option<Input<'static>> = None;
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    info!("boot");
+    let mut config = CPUConfig::default();
+    config.rcc.hsi = true;
+    config.rcc.sys = Sysclk::PLL1_R;
+    config.rcc.pll1 = Some(Pll {
+        source: PllSource::HSI,
+        // 16 MHz / 1 × 20 / 2 = 160 MHz
+        prediv: PllPreDiv::DIV1,
+        mul:    PllMul::MUL20,
+        divp:   None,
+        divq:   None,
+        divr:   Some(PllDiv::DIV2),
+    });
+    config.enable_independent_io_supply = true;
+    config.enable_independent_analog_supply = true;
+
+    let p = embassy_stm32::init(config);
+    let f_tim7 = rcc::frequency::<embassy_stm32::peripherals::TIM7>().0;
+    info!("TIM7 clock after PLL config = {} Hz", f_tim7);
+    let f_tim6 = rcc::frequency::<embassy_stm32::peripherals::TIM6>().0;
+    info!("TIM6 clock after PLL config = {} Hz", f_tim6);
+
+    // HARDWARE UART to the PC
+    let mut cfg = Config::default();
+    cfg.baudrate = BAUD;
+    static TX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
+    static RX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
+    let uart = BufferedUart::new(
+        p.USART1,
+        p.PA10, // RX pin
+        p.PA9,  // TX pin
+        TX_BUF.init([0; 256]),
+        RX_BUF.init([0; 256]),
+        Irqs,
+        cfg,
+    ).unwrap();
+    let yield_period = usart1::setup_and_spawn(BAUD);
+    spawner.spawn(uart_task(uart, &PIPE_HW_TX, &PIPE_HW_RX).unwrap());
+    // END OF HARDWARE UART to the PC
+
+    // INTERNAL HARDWARE UART (USART2)
+    let mut cfg2 = Config::default();
+    cfg2.baudrate = BAUD;
+    static TX_BUF2: StaticCell<[u8; 256]> = StaticCell::new();
+    static RX_BUF2: StaticCell<[u8; 256]> = StaticCell::new();
+
+    let uart2 = BufferedUart::new(
+        p.USART2,
+        p.PA3, // RX
+        p.PA2, // TX
+        TX_BUF2.init([0; 256]),
+        RX_BUF2.init([0; 256]),
+        Irqs2,
+        cfg2,
+    ).unwrap();
+    let yield_period2 = usart2::setup_and_spawn(BAUD);
+    spawner.spawn(uart_task_internal(uart2, &PIPE_INT_TX, &PIPE_INT_RX).unwrap());
+    info!("USART2 ready");
+    // END OF INTERNAL HARDWARE UART (USART2)
+    
+    // USART1 <-> USART2 bridge
+    spawner.spawn(bridge_usart1_rx_to_usart2_tx(&PIPE_HW_RX, &PIPE_INT_TX).unwrap());
+    spawner.spawn(bridge_usart2_rx_to_usart1_tx(&PIPE_INT_RX, &PIPE_HW_TX).unwrap());
+    info!("USART1 <-> USART2 bridge active");
+    // END OF USART1 <-> USART2 bridge 
+
+    // SOFTWARE UART 
+    let rx_pin = Input::new(p.PD6, Pull::Up);
+    unsafe { RX_PIN = Some(rx_pin) };
+
+    let mut tx_pin = Output::new(p.PB0, Level::High, Speed::VeryHigh);
+    init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE);
+    init_tim7_for_uart(p.TIM7, BAUD, RX_OVERSAMPLE);
+    dump_tim6_regs();
+
+    let bsrr_ptr = embassy_stm32::pac::GPIOB.bsrr().as_ptr() as *mut u32; // POZOR B REGISTER
+    spawner.spawn(tx_dma_task(p.GPDMA1_CH0, bsrr_ptr, SW_TX_RING.init([0; TX_RING_BYTES]), &PIPE_SW_TX).unwrap());
+    // EDN OF SOFTWARE UART
+
+
+    let rx_ring = SW_RX_RING.init([0u8; RX_RING_BYTES]);
+    let gpio_idr = embassy_stm32::pac::GPIOD.idr().as_ptr() as *mut u8;
+    spawner.spawn(rx_dma_task(p.GPDMA1_CH1, gpio_idr, rx_ring, &PIPE_SW_RX).unwrap());
+    info!("SW UART RX DMA started");
+
+    let mut buf = [0u8; 64];
+    loop {
+        let n = PIPE_SW_RX.read(&mut buf).await;
+        if n > 0 {
+            let _ = PIPE_SW_TX.write(&buf[..n]).await;
+            // info!("SW UART decoded: {:a}", &buf[..n]);
+        }
+        yield_now().await;
+    }
+}
+
+#[embassy_executor::task]
+pub async fn bridge_usart1_rx_to_usart2_tx(
+    usart1_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+    usart2_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut buf = [0u8; 64];
+    loop {
+        let n = usart1_rx.read(&mut buf).await;
+        if n > 0 {
+            let _ = usart2_tx.write(&buf[..n]).await;
+            // info!("bridge USART1 - USART2 sent:{} bytes: {}", n, &buf[..n]);
+        }
+        yield_now().await;
+    }
+}
+
+#[embassy_executor::task]
+pub async fn bridge_usart2_rx_to_usart1_tx(
+    usart2_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+    usart1_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut buf = [0u8; 64];
+    loop {
+        let n = usart2_rx.read(&mut buf).await;
+        if n > 0 {
+            let _ = usart1_tx.write(&buf[..n]).await;
+            // info!("bridge: USART2 -> USART1 sent {} bytes", n);
+        }
+        yield_now().await;
+    }
+}

semestralka_1_connected/src/config.rs

@@ -0,0 +1,35 @@
+// src/config.rs
+use crate::software_uart::uart_emulation::{Parity, StopBits, UartConfig};
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+
+pub const BAUD: u32 = 9_600;
+// pub const TX_PIN_BIT: u8 = 2; // PA2
+// pub const RX_PIN_BIT: u8 = 3; // PA3
+pub const TX_PIN_BIT: u8 = 0; // PB2
+pub const RX_PIN_BIT: u8 = 6; // PC3
+pub const TX_OVERSAMPLE: u16 = 1;
+pub const RX_OVERSAMPLE: u16 = 13;
+
+pub const RX_RING_BYTES: usize = 32768;
+pub const TX_RING_BYTES: usize = 4096;
+
+pub const PIPE_HW_TX_SIZE: usize = 1024;
+pub const PIPE_HW_RX_SIZE: usize = 1024;
+pub const PIPE_SW_TX_SIZE: usize = 1024;
+pub const PIPE_SW_RX_SIZE: usize = 4096;
+pub const PIPE_INT_TX_SIZE: usize = 1024;
+pub const PIPE_INT_RX_SIZE: usize = 1024;
+
+pub static PIPE_HW_TX: Pipe<CriticalSectionRawMutex, PIPE_HW_TX_SIZE> = Pipe::new();
+pub static PIPE_HW_RX: Pipe<CriticalSectionRawMutex, PIPE_HW_RX_SIZE> = Pipe::new();
+pub static PIPE_SW_TX: Pipe<CriticalSectionRawMutex, PIPE_SW_TX_SIZE> = Pipe::new();
+pub static PIPE_SW_RX: Pipe<CriticalSectionRawMutex, PIPE_SW_RX_SIZE> = Pipe::new();
+pub static PIPE_INT_TX: Pipe<CriticalSectionRawMutex, PIPE_INT_TX_SIZE> = Pipe::new();
+pub static PIPE_INT_RX: Pipe<CriticalSectionRawMutex, PIPE_INT_RX_SIZE> = Pipe::new();
+
+pub const UART_CFG: UartConfig = UartConfig {
+    data_bits: 8,
+    parity: Parity::None,
+    stop_bits: StopBits::One,
+};

semestralka_1_connected/src/hw_uart_internal/driver.rs

@@ -0,0 +1,41 @@
+// src/hw_uart_internal/driver.rs
+use defmt::unwrap;
+use embassy_futures::select::{select, Either};
+use embassy_stm32::usart::BufferedUart;
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+use embedded_io_async::{Read, Write};
+use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
+use embassy_futures::yield_now;
+
+#[embassy_executor::task]
+pub async fn uart_task(
+    mut uart: BufferedUart<'static>,
+    tx_pipe: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
+    rx_pipe: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
+) {
+    let mut rx_byte = [0u8; 1];
+    let mut tx_buf = [0u8; 64];
+
+    loop {
+        let rx_fut = uart.read(&mut rx_byte);
+        let tx_fut = async {
+            let n = tx_pipe.read(&mut tx_buf).await;
+            n
+        };
+
+        match select(rx_fut, tx_fut).await {
+            // Incoming data from UART hardware
+            Either::First(res) => {
+                if let Ok(_) = res {
+                    let _ = rx_pipe.write(&rx_byte).await;
+                }
+            }
+            // Outgoing data waiting in TX pipe
+            Either::Second(n) => {
+                unwrap!(uart.write(&tx_buf[..n]).await);
+            }
+        }
+        yield_now().await;
+    }
+}

semestralka_1_connected/src/hw_uart_internal/mod.rs

@@ -0,0 +1,4 @@
+// src/hw_uart_internal/mod.rs
+
+pub mod driver;
+pub mod usart2;

semestralka_1_connected/src/hw_uart_internal/usart2.rs

@@ -0,0 +1,11 @@
+// src/hw_uart_internal/usart2.rs
+use defmt::info;
+use embassy_time::Duration;
+
+use crate::hw_uart_pc::safety::preflight_and_suggest_yield_period;
+
+pub fn setup_and_spawn(baudrate: u32) -> Duration {
+    let yield_period = preflight_and_suggest_yield_period(baudrate);
+    info!("HW USART2 safe");
+    yield_period
+}

semestralka_1_connected/src/hw_uart_pc/driver.rs

@@ -0,0 +1,41 @@
+// src/hw_uart_pc/driver.rs
+use defmt::unwrap;
+use embassy_futures::select::{select, Either};
+use embassy_stm32::usart::BufferedUart;
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+use embedded_io_async::{Read, Write};
+use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
+use embassy_futures::yield_now;
+
+#[embassy_executor::task]
+pub async fn uart_task(
+    mut uart: BufferedUart<'static>,
+    tx_pipe: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
+    rx_pipe: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
+) {
+    let mut rx_byte = [0u8; 1];
+    let mut tx_buf = [0u8; 64];
+
+    loop {
+        let rx_fut = uart.read(&mut rx_byte);
+        let tx_fut = async {
+            let n = tx_pipe.read(&mut tx_buf).await;
+            n
+        };
+
+        match select(rx_fut, tx_fut).await {
+            // Incoming data from UART hardware
+            Either::First(res) => {
+                if let Ok(_) = res {
+                    let _ = rx_pipe.write(&rx_byte).await;
+                }
+            }
+            // Outgoing data waiting in TX pipe
+            Either::Second(n) => {
+                unwrap!(uart.write(&tx_buf[..n]).await);
+            }
+        }
+        yield_now().await;
+    }
+}

semestralka_1_connected/src/hw_uart_pc/mod.rs

@@ -0,0 +1,4 @@
+// src/hw_uart_pc/mod.rs
+pub mod driver;
+pub mod usart1;
+pub mod safety;

semestralka_1_connected/src/hw_uart_pc/safety.rs

@@ -0,0 +1,57 @@
+// src/safety.rs
+use defmt::info;
+use embassy_time::Duration;
+
+// ISR RX ring capacity = RX_BUF len
+const ISR_RX_BUF_CAP: usize = 256;
+// Yield 1/2 the time it takes to fill ISR RX ring.
+const YIELD_MARGIN_NUM: u32 = 1;
+const YIELD_MARGIN_DEN: u32 = 2;
+// Ensure RX_PIPE_CAP can hold this.
+const WORST_MAIN_LATENCY_MS: u32 = 20;
+
+pub const TX_PIPE_CAP: usize = 1024;
+pub const RX_PIPE_CAP: usize = 1024;
+
+
+
+/// Perform safety checks and compute yield timing to avoid buffer overflow.
+///
+/// # Panics
+/// Panics if pipe capacities are too small for the configured baud.
+pub fn preflight_and_suggest_yield_period(baud: u32) -> Duration {
+    // Approx bytes per second for 8N1 (10 bits per byte on the wire)
+    let bytes_per_sec = (baud / 10).max(1);
+
+    // Time until ISR RX ring fills, in microseconds.
+    let t_fill_us = (ISR_RX_BUF_CAP as u64) * 1_000_000u64 / (bytes_per_sec as u64);
+
+    // Choose a yield period as a fraction of t_fill.
+    let yield_us = (t_fill_us as u64)
+        .saturating_mul(YIELD_MARGIN_NUM as u64)
+        / (YIELD_MARGIN_DEN as u64);
+
+    // Verify RX pipe can absorb a worst-case app latency so uart_task
+    // can always forward without dropping when it runs.
+    let required_rx_pipe = (bytes_per_sec as u64) * (WORST_MAIN_LATENCY_MS as u64) / 1000;
+
+    if (RX_PIPE_CAP as u64) < required_rx_pipe {
+        core::panic!(
+            "RX pipe too small: have {}B, need >= {}B for {}ms at {} bps",
+            RX_PIPE_CAP, required_rx_pipe, WORST_MAIN_LATENCY_MS, baud
+        );
+    }
+
+    info!(
+        "Preflight: baud={}, rx_isr={}B, rx_pipe={}B, bytes/s={}, t_fill_us={}, yield_us={}",
+        baud,
+        ISR_RX_BUF_CAP,
+        RX_PIPE_CAP,
+        bytes_per_sec,
+        t_fill_us,
+        yield_us
+    );
+
+    // Never choose zero.
+    Duration::from_micros(yield_us.max(1) as u64)
+}

semestralka_1_connected/src/hw_uart_pc/usart1.rs

@@ -0,0 +1,12 @@
+// src/uart/usart1.rs
+use defmt::info;
+use embassy_time::Duration;
+
+use crate::hw_uart_pc::safety::preflight_and_suggest_yield_period;
+
+pub fn setup_and_spawn(baudrate: u32,) -> Duration {
+    let yield_period: Duration = preflight_and_suggest_yield_period(baudrate);
+    info!("HW USART1 safe");
+
+    yield_period
+}

semestralka_1_connected/src/lib.rs

@@ -0,0 +1,6 @@
+#![no_std]
+
+pub mod software_uart;
+pub mod config;
+pub mod hw_uart_pc;
+pub mod hw_uart_internal;

semestralka_1_connected/src/software_uart/debug.rs

@@ -0,0 +1,43 @@
+// src/software_uart/debug.rs
+use defmt::info;
+
+pub fn dump_tim6_regs() {
+    use embassy_stm32::pac::timer::TimBasic;
+    let tim = unsafe { TimBasic::from_ptr(0x4000_1000usize as _) };
+    let sr = tim.sr().read();
+    let dier = tim.dier().read();
+    let cr1 = tim.cr1().read();
+    let arr = tim.arr().read().arr();
+    let psc = tim.psc().read();
+    info!(
+        "TIM6: CR1.CEN={} DIER.UDE={} SR.UIF={} PSC={} ARR={}",
+        cr1.cen(),
+        dier.ude(),
+        sr.uif(),
+        psc,
+        arr
+    );
+}
+
+pub fn dump_dma_ch0_regs() {
+    use embassy_stm32::pac::gpdma::Gpdma;
+    let dma = unsafe { Gpdma::from_ptr(0x4002_0000usize as _) };
+    let ch = dma.ch(0);
+    let cr = ch.cr().read();
+    let tr1 = ch.tr1().read();
+    let tr2 = ch.tr2().read();
+    let br1 = ch.br1().read();
+    info!(
+        "GPDMA1_CH0: EN={} PRIO={} SDW={} DDW={} SINC={} DINC={} REQSEL={} SWREQ={} DREQ={} BNDT={}",
+        cr.en(),
+        cr.prio(),
+        tr1.sdw(),
+        tr1.ddw(),
+        tr1.sinc(),
+        tr1.dinc(),
+        tr2.reqsel(),
+        tr2.swreq(),
+        tr2.dreq(),
+        br1.bndt()
+    );
+}

semestralka_1_connected/src/software_uart/dma_timer.rs

@@ -0,0 +1,67 @@
+// src/dma_timer.rs
+
+use embassy_stm32::{
+    peripherals::{TIM6, TIM7},
+    rcc,
+    timer::low_level::Timer,
+    Peri,
+};
+use core::mem;
+use embassy_stm32::timer::BasicInstance;
+use embassy_stm32::pac::timer::vals::Urs;
+
+/// Initializes TIM6 to tick at `baud * oversample` frequency.
+/// Each TIM6 update event triggers one DMA beat.
+pub fn init_tim6_for_uart<'d>(tim6: Peri<'d, TIM6>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM6>();
+    let ll = Timer::new(tim6);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+/// Initializes TIM7 to tick at `baud * oversample` frequency.
+/// Each TIM7 update event triggers one DMA beat.
+pub fn init_tim7_for_uart<'d>(tim7: Peri<'d, TIM7>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM7>();
+    let ll = Timer::new(tim7);
+    configure_basic_timer(&ll, baud, oversample);
+    // Enable Update Interrupt (UIE)
+    ll.regs_basic().dier().modify(|w| {
+        w.set_ude(true);
+        w.set_uie(false);
+    });
+    mem::forget(ll);
+}
+
+// Shared internal helper — identical CR1/ARR setup
+fn configure_basic_timer<T: BasicInstance>(ll: &Timer<'_, T>, baud: u32, oversample: u16) {
+    let f_timer = rcc::frequency::<T>().0;
+    let target = baud.saturating_mul(oversample.max(1) as u32).max(1);
+
+    // Compute ARR (prescaler = 0)
+    // let mut arr = (f_timer / target).saturating_sub(1) as u16;
+    let mut arr = ((f_timer + target / 2) / target).saturating_sub(1) as u16;
+    if arr == 0 { arr = 1; }
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_cen(false);
+        w.set_opm(false);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+
+    ll.regs_basic().psc().write_value(0u16);
+    ll.regs_basic().arr().write(|w| w.set_arr(arr));
+    ll.regs_basic().dier().modify(|w| w.set_ude(true));
+    ll.regs_basic().egr().write(|w| w.set_ug(true));
+
+    // Clear spurious UIF from UG trigger
+    ll.regs_basic().sr().modify(|w| w.set_uif(false));
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_opm(false);
+        w.set_cen(true);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+}

semestralka_1_connected/src/software_uart/gpio_dma_uart_rx.rs

@@ -0,0 +1,94 @@
+// src/software_uart/runtime.rs
+use embassy_executor::task;
+use embassy_stm32::{
+    dma::Request,
+    peripherals::GPDMA1_CH1,
+    Peri,
+};
+use crate::config::RX_PIN_BIT;
+use embassy_stm32::dma::{
+    ReadableRingBuffer,
+    TransferOptions,
+};
+use crate::config::{RX_OVERSAMPLE, UART_CFG};
+use crate::software_uart::decode_uart_samples;
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use embassy_futures::yield_now;
+use defmt::info;
+
+// datasheet tabulka 137
+pub const TIM7_UP_REQ: Request = 5;
+
+/// RX DMA task: reads GPIO samples paced by TIM7 and fills PIPE_RX
+#[task]
+pub async fn rx_dma_task(
+    ch: Peri<'static, GPDMA1_CH1>,
+    register: *mut u8,
+    ring: &'static mut [u8],
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 4096>,
+) {
+    let mut opts = TransferOptions::default();
+    opts.half_transfer_ir = true;
+    opts.complete_transfer_ir = true;
+
+    // SAFETY: ring is exclusive to this task
+    let mut rx = unsafe { ReadableRingBuffer::new(ch, TIM7_UP_REQ, register, ring, opts) };
+    rx.start();
+
+    // We read into the second half of a buffer, keeping "leftovers" in the first half.
+    const CHUNK_SIZE: usize = 4096;
+    const HISTORY_SIZE: usize = 512;
+    const TOTAL_BUF_SIZE: usize = HISTORY_SIZE + CHUNK_SIZE;
+    
+    // Logic level buffer
+    let mut level_buf = [0u8; TOTAL_BUF_SIZE];
+    let mut valid_len = 0usize; 
+
+    let mut raw_chunk = [0u8; CHUNK_SIZE];
+
+    loop {
+        let _ = rx.read_exact(&mut raw_chunk).await;
+
+        for (i, b) in raw_chunk.iter().enumerate() {
+             level_buf[valid_len + i] = ((*b >> RX_PIN_BIT) & 1) as u8;
+        }
+        let current_end = valid_len + CHUNK_SIZE;
+
+        let (decoded, consumed) = decode_uart_samples(
+            &level_buf[..current_end], 
+            RX_OVERSAMPLE, 
+            &UART_CFG
+        );
+
+        if !decoded.is_empty() {
+             pipe_rx.write(decoded.as_slice()).await;
+
+             for byte in decoded.as_slice() {
+                 // info!("DMA BUFFER CHAR: {} (ASCII: {})", *byte, *byte as char);
+             }
+        }
+
+        // Shift remaining data to front
+        // We processed 'consumed' samples.
+        // We keep everything from 'consumed' up to 'current_end'.
+        let remaining = current_end - consumed;
+        
+        // SAFETY if remaining > HISTORY_SIZE, we are in trouble (buffer too small / decoder stuck).
+        if remaining > 0 {
+            level_buf.copy_within(consumed..current_end, 0);
+        }
+        valid_len = remaining;
+        
+        // If valid_len grows too large (decoder not consuming), we must discard to avoid panic on next write
+        if valid_len >= HISTORY_SIZE {
+             // Discard oldest to make space
+             // logic: we move the last (HISTORY_SIZE/2) to 0.
+             // This effectively "skips" garbage data.
+             let keep = HISTORY_SIZE / 2;
+             level_buf.copy_within(valid_len - keep..valid_len, 0);
+             valid_len = keep;
+        }
+
+        yield_now().await;
+    }
+}

semestralka_1_connected/src/software_uart/gpio_dma_uart_tx.rs

@@ -0,0 +1,90 @@
+// src/software_uart/gpio_dma_uart_tx.rs
+use embassy_executor::task;
+use embassy_stm32::{
+    dma::{Request, Transfer, TransferOptions},
+    peripherals::GPDMA1_CH0,
+    Peri,
+};
+use embassy_futures::yield_now;
+use defmt::info;
+
+use embassy_sync::pipe::Pipe;
+use crate::config::{TX_PIN_BIT, UART_CFG};
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use crate::software_uart::uart_emulation::encode_uart_byte_cfg;
+
+pub const TIM6_UP_REQ: Request = 4;
+
+pub async fn encode_uart_frames<'a>(
+    pin_bit: u8,
+    bytes: &[u8],
+    out_buf: &'a mut [u32],
+) -> usize {
+    let mut offset = 0;
+    for &b in bytes {
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(pin_bit, b, &UART_CFG, &mut frame);
+
+        if offset + used <= out_buf.len() {
+            out_buf[offset..offset + used].copy_from_slice(&frame[..used]);
+            offset += used;
+        } else {
+            break;
+        }
+
+        yield_now().await;
+    }
+    offset
+}
+
+#[task]
+pub async fn tx_dma_task(
+    mut ch: Peri<'static, GPDMA1_CH0>,
+    register: *mut u32, // GPIOx_BSRR
+    _tx_ring_mem: &'static mut [u32],
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    info!("TX DMA task ready (One‑shot)");
+
+    let mut frame_buf = [0u32; 4096];
+    let mut rx_buf = [0u8; 256];
+    let tim6 = embassy_stm32::pac::TIM6;
+
+    loop {
+        let n = pipe_rx.read(&mut rx_buf).await;
+        if n == 0 {
+            yield_now().await;
+            continue;
+        }
+
+        let used = encode_uart_frames(TX_PIN_BIT, &rx_buf[..n], &mut frame_buf).await;
+        if used > 0 {
+            // Clear pending UIF
+            tim6.sr().write(|w| w.set_uif(false));
+            // Wait for the next UIF (next bit tick)
+            while !tim6.sr().read().uif() {
+                yield_now().await;
+            }
+            // Clear UIF so first DMA beat happens on the FOLLOWING tick
+            tim6.sr().write(|w| w.set_uif(false));
+
+            let mut tx_opts = TransferOptions::default();
+            tx_opts.half_transfer_ir = false;
+            tx_opts.complete_transfer_ir = true;
+
+            unsafe {
+                let transfer = Transfer::new_write(
+                    ch.reborrow(),
+                    TIM6_UP_REQ,
+                    &frame_buf[..used],
+                    register,
+                    tx_opts,
+                );
+                transfer.await;
+            }
+        }
+
+        // info!("tx_dma_task sent {} words", used);
+        yield_now().await;
+    }
+}

semestralka_1_connected/src/software_uart/mod.rs

@@ -0,0 +1,13 @@
+// src/software_uart/mod.rs
+
+pub mod gpio_dma_uart_tx;
+pub mod gpio_dma_uart_rx;
+pub mod dma_timer;
+pub mod uart_emulation;
+pub mod debug;
+
+pub use gpio_dma_uart_tx::*;
+pub use gpio_dma_uart_rx::*;
+pub use dma_timer::*;
+pub use uart_emulation::*;
+pub use debug::*;

semestralka_1_connected/src/software_uart/uart_emulation.rs

@@ -0,0 +1,204 @@
+// src/software_uart/uart_emulation.rs
+use heapless::Vec;
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Parity {
+    None,
+    Even,
+    Odd,
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum StopBits {
+    One,
+    Two,
+}
+
+#[derive(Clone, Copy, Debug)]
+pub struct UartConfig {
+    pub data_bits: u8,
+    pub parity: Parity,
+    pub stop_bits: StopBits,
+}
+
+impl Default for UartConfig {
+    fn default() -> Self {
+        Self {
+            data_bits: 8,
+            parity: Parity::None,
+            stop_bits: StopBits::One,
+        }
+    }
+}
+
+/// Encodes one byte into a sequence of GPIO BSRR words
+pub fn encode_uart_byte_cfg(
+    pin_bit: u8,
+    data: u8,
+    cfg: &UartConfig,
+    out: &mut [u32; 12],
+) -> usize {
+    // GPIOx_BSRR register str. 636 kap. 13.4.7
+    let set_high = |bit: u8| -> u32 { 1u32 << bit };
+    // let set_low = |bit: u8| -> u32 { 0 }; // ODR
+    let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) }; // BSRR
+
+    let mut idx = 0usize;
+
+    // START bit (LOW)
+    out[idx] = set_low(pin_bit);
+    idx += 1;
+
+    // Data bits, LSB-first
+    let nbits = cfg.data_bits.clamp(5, 8);
+    for i in 0..nbits {
+        let one = ((data >> i) & 1) != 0;
+        out[idx] = if one { set_high(pin_bit) } else { set_low(pin_bit) };
+        idx += 1;
+    }
+
+    // Parity
+    match cfg.parity {
+        Parity::None => {}
+        Parity::Even | Parity::Odd => {
+            let mask: u8 = if nbits == 8 { 0xFF } else { (1u16 << nbits) as u8 - 1 };
+            let ones = (data & mask).count_ones() & 1;
+            let par_bit_is_one = match cfg.parity {
+                Parity::Even => ones == 1,
+                Parity::Odd => ones == 0,
+                _ => false,
+            };
+            out[idx] = if par_bit_is_one {
+                set_high(pin_bit)
+            } else {
+                set_low(pin_bit)
+            };
+            idx += 1;
+        }
+    }
+
+    // STOP bits (HIGH)
+    let stop_ticks = match cfg.stop_bits {
+        StopBits::One => 1usize,
+        StopBits::Two => 2usize,
+    };
+    for _ in 0..stop_ticks {
+        out[idx] = set_high(pin_bit);
+        idx += 1;
+    }
+
+    idx
+}
+
+/// Decode an oversampled stream of logic levels into UART bytes.
+/// Returns (decoded bytes, number of samples consumed/processed).
+pub fn decode_uart_samples(
+    samples: &[u8],
+    oversample: u16,
+    cfg: &UartConfig,
+) -> (heapless::Vec<u8, 256>, usize) {
+    let mut out = Vec::<u8, 256>::new();
+    let mut idx = 0usize;
+    let nbits = cfg.data_bits as usize;
+    let ovs = oversample as usize;
+
+    // Calculate total frame width in samples to ensure we have enough data
+    // 1 start + n data + parity? + stops
+    let parity_bits = match cfg.parity {
+        Parity::None => 0,
+        _ => 1,
+    };
+    let stop_bits_count = match cfg.stop_bits {
+        StopBits::One => 1,
+        StopBits::Two => 2,
+    };
+    let frame_bits = 1 + nbits + parity_bits + stop_bits_count;
+    let frame_len = frame_bits * ovs;
+
+    // Majority vote over 3 samples centered at `i`
+    let get_bit = |i: usize| -> u8 {
+        let mut votes = 0;
+        // Check i-1, i, i+1. Saturating sub/add handles boundaries roughly.
+        if i > 0 && samples.get(i - 1).map_or(true, |&x| x != 0) {
+            votes += 1;
+        }
+        if samples.get(i).map_or(true, |&x| x != 0) {
+            votes += 1;
+        }
+        if samples.get(i + 1).map_or(true, |&x| x != 0) {
+            votes += 1;
+        }
+
+        if votes >= 2 {
+            1
+        } else {
+            0
+        }
+    };
+
+    // Loop while we have enough remaining samples for a full frame
+    while idx + frame_len <= samples.len() {
+        // Wait for falling edge (High -> Low)
+        // samples[idx] == 1 (Idle/Stop) && samples[idx+1] == 0 (Start)
+        if samples[idx] != 0 && samples[idx + 1] == 0 {
+            // Align to center of START bit
+            // Start bit begins at idx+1. Center is at idx + 1 + (ovs/2)
+            let center_offset = 1 + (ovs / 2);
+            let mut scan_idx = idx + center_offset;
+
+            // Validate Start Bit
+            if get_bit(scan_idx) != 0 {
+                idx += 1; // False start (noise), move on
+                continue;
+            }
+
+            // Move to center of first data bit
+            scan_idx += ovs;
+
+            // Read Data Bits
+            let mut data: u8 = 0;
+            for bit in 0..nbits {
+                if get_bit(scan_idx) == 1 {
+                    data |= 1 << bit;
+                }
+                scan_idx += ovs;
+            }
+
+            // Skip Parity
+            if cfg.parity != Parity::None {
+                scan_idx += ovs;
+            }
+
+            // Validate Stop Bit (Must be 1)
+            // If stop bit is 0, it's a framing error. We reject the whole byte.
+            if get_bit(scan_idx) == 0 {
+                idx += 1; // Next sample
+                continue;
+            }
+
+            // Byte is valid
+            let _ = out.push(data);
+
+            // Active Resync: Fast-forward through the stop bit(s) and idle time
+            // scan_idx is currently at the center of the Stop bit.
+            idx = scan_idx;
+            // Advance while we are reading High (1).
+            // As soon as we see Low (0), we stop. That 0 is the beginning of the NEXT start bit.
+            // The outer loop expects `idx` to be the High *before* the start bit, so we will handle that.
+            while idx < samples.len() && samples[idx] != 0 {
+                idx += 1;
+            }
+            // Back up one step.
+            // The outer loop logic is: `if samples[idx] != 0 && samples[idx+1] == 0`.
+            // If we stopped at `idx` because it was 0, then `idx-1` was the last 1 (Idle).
+            if idx > 0 {
+                idx -= 1;
+            }
+        } else {
+            // No start bit detected here, move to next sample
+            idx += 1;
+        }
+    }
+
+    (out, idx)
+}

semestralka_1_connected/tests/uart_emulation.rs

@@ -0,0 +1,41 @@
+#![no_std]
+#![no_main]
+
+use dma_gpio as _;
+use panic_probe as _;
+use defmt_rtt as _;
+
+#[defmt_test::tests]
+mod tests {
+    use defmt::assert_eq;
+    use dma_gpio::software_uart::uart_emulation::{
+        encode_uart_byte_cfg, UartConfig, Parity, StopBits
+    };
+
+    const TX_PIN_BIT: u8 = 2;
+
+    #[test]
+    fn test_encode_8n1() {
+        let cfg = UartConfig::default();
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(TX_PIN_BIT, 0x55, &cfg, &mut frame);
+        
+        assert_eq!(used, 10);
+        assert_eq!(frame[0], 1u32 << 18); // Start LOW
+        assert_eq!(frame[9], 1u32 << 2);  // Stop HIGH
+    }
+
+    #[test]
+    fn test_encode_parity() {
+        let cfg = UartConfig {
+            data_bits: 8,
+            parity: Parity::Even,
+            stop_bits: StopBits::One,
+        };
+        
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(TX_PIN_BIT, 0x00, &cfg, &mut frame);
+        
+        assert_eq!(used, 11);
+    }
+}

semestralka_1_final_crate/software_uart/.cargo/config.toml

@@ -0,0 +1,2 @@
+[build]
+target = "thumbv8m.main-none-eabihf"

semestralka_1_final_crate/software_uart/.gitignore

@@ -0,0 +1 @@
+target/

semestralka_1_final_crate/software_uart/Cargo.toml

@@ -0,0 +1,36 @@
+[package]
+name = "software_uart"
+version = "1.0.0"
+edition = "2024"
+license = "MIT OR Apache-2.0"
+
+[dependencies]
+cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.5"
+panic-halt = "1.0.0"
+embassy-executor = { path = "/home/priec/programs/embassy/embassy-executor", features = ["arch-cortex-m", "executor-thread"] }
+embassy-futures = { path = "/home/priec/programs/embassy/embassy-futures" }
+embassy-sync = { path = "/home/priec/programs/embassy/embassy-sync" }
+embassy-time = { path = "/home/priec/programs/embassy/embassy-time", features = ["tick-hz-32_768"] }
+embassy-hal-internal = { path = "/home/priec/programs/embassy/embassy-hal-internal" }
+embassy-usb = { path = "/home/priec/programs/embassy/embassy-usb" }
+embassy-stm32 = { path = "/home/priec/programs/embassy/embassy-stm32", features = ["unstable-pac", "stm32u575zi", "time-driver-tim2", "memory-x", "defmt"] }
+
+embedded-hal = "1.0.0"
+embedded-graphics = "0.8.1"
+heapless = { version = "0.9.1", default-features = false }
+micromath = "2.1.0"
+tinybmp = "0.6.0"
+panic-probe = { version = "1.0.0", features = ["defmt"] }
+defmt-rtt = "1.1.0"
+defmt = "1.0.1"
+static_cell = "2.1.1"
+embedded-io = "0.6.1"
+embedded-io-async = "0.6.1"
+
+[dev-dependencies]
+defmt-test = "0.4.0"
+
+[profile.dev]
+opt-level = 3
+codegen-units = 1

semestralka_1_final_crate/software_uart/docs/decode_rx_uml.txt

@@ -0,0 +1,82 @@
+@startuml
+title Dekodovanie UART: decode_uart_samples
+
+start
+
+:Inicializacia out (Vec<u8, 256>) a idx = 0;
+
+:nbits = cfg.data_bits;
+:ovs = oversample;
+
+:parity_bits = 0 alebo 1 podla cfg.parity;
+:stop_bits_count = 1 alebo 2 podla cfg.stop_bits;
+
+:frame_bits = 1 + nbits + parity_bits + stop_bits_count;
+:frame_len = frame_bits * ovs;
+
+while (idx + frame_len <= samples.len()?) is (ano)
+  if (Start bit detekovany?\n(samples[idx] != 0 && samples[idx + 1] == 0)) then (ano)
+    :center_offset = ovs / 2;
+    :scan_idx = idx + center_offset;
+
+    if (get_bit(scan_idx) == 0?\nvalidacia START bitu) then (ano)
+      :scan_idx += ovs\n(posun na prvy data bit);
+      :data = 0;
+
+      repeat :Citanie datovych bitov (0..nbits-1, LSB first)
+        if (get_bit(scan_idx) == 1?) then (ano)
+          :data |= 1 << bit;
+        endif
+        :scan_idx += ovs;
+      repeat while (zvysne data bity?) is (ano)
+      ->nie;
+
+      :error_data = false;
+
+      if (cfg.parity != Parity::None?) then (ano)
+        :expected_parity = calculate_parity(data, cfg.parity);
+        :actual_parity = get_bit(scan_idx);
+        if (expected_parity != actual_parity?) then (ano)
+          :error_data = true;
+          note right: Chyba parity
+        endif
+        :scan_idx += ovs;
+      endif
+
+      repeat :Kontrola stop bitov
+        if (get_bit(scan_idx) == 0?) then (ano)
+          :error_data = true;
+          note right: Framing chyba (stop bit = 0)
+          break
+        endif
+        :scan_idx += ovs;
+      repeat while (zvysne stop bity?) is (ano)
+      ->nie;
+
+      if (error_data?) then (ano)
+        :idx += 1;\n(preskoc chybny frame);
+      else (nie)
+        :push data do out;
+        :idx = scan_idx;
+
+        :Preskoc idle HIGH (hladanie dalsieho start bitu);
+        while (idx < samples.len() && samples[idx] != 0?) is (ano)
+          :idx += 1;
+        endwhile (nie)
+
+        if (idx > 0?) then (ano)
+          :idx -= 1;\n("mensi hack");
+        endif
+      endif
+    else (nie)
+      :idx += 1;\n(falosny start);
+    endif
+  else (nie)
+    :idx += 1;
+  endif
+endwhile (nie)
+
+:Navrat (out, idx);
+
+stop
+@enduml

semestralka_1_final_crate/software_uart/docs/decode_timing.txt

@@ -0,0 +1,29 @@
+@startuml
+scale 5 as 100 pixels
+
+clock "TIM7" as clk with period 1
+binary "UART RX" as uart
+binary "Sample" as smp
+
+@0
+uart is low
+smp is low
+
+@8
+smp is high
+
+@9
+smp is low
+
+@16
+uart is high
+
+@24
+smp is high
+
+@25
+smp is low
+
+@32
+uart is high
+@enduml

semestralka_1_final_crate/software_uart/docs/encode_timing.txt

@@ -0,0 +1,24 @@
+@startuml
+scale 5 as 100 pixels
+
+clock "TIM6" as clk with period 1
+binary "GPIO TX" as gpio
+binary "BSRR write" as bsrr
+
+@0
+gpio is low
+bsrr is high
+
+@1
+bsrr is low
+
+@16
+gpio is high
+bsrr is high
+
+@17
+bsrr is low
+
+@32
+gpio is high
+@enduml

semestralka_1_final_crate/software_uart/docs/encode_tx.txt

@@ -0,0 +1,31 @@
+@startuml
+title Enkodovanie UART: encode_uart_byte_cfg
+
+start
+
+:set_high = 1 << pin_bit;
+:set_low = 1 << (pin_bit + 16);
+:nbits = cfg.data_bits, idx = 0;
+
+:START bit (LOW)\nout[idx++] = set_low;
+
+repeat :Data bity (LSB first)
+  :out[idx++] = ((data >> i) & 1) ?\nset_high : set_low;
+repeat while (i < nbits?) is (ano)
+->nie;
+
+if (cfg.parity != None?) then (ano)
+  :ones = data.count_ones() & 1;
+  :par_bit = (Even) ? ones==1 : ones==0;
+  :out[idx++] = par_bit ? set_high : set_low;
+endif
+
+repeat :STOP bity (HIGH)
+  :out[idx++] = set_high;
+repeat while (zvysne stop bity?) is (ano)
+->nie;
+
+:Return idx;
+
+stop
+@enduml

semestralka_1_final_crate/software_uart/docs/flake.nix

@@ -0,0 +1,18 @@
+{
+  description = "PlantUML dev shell";
+
+  inputs.nixpkgs.url = "github:NixOS/nixpkgs";
+
+  outputs = { self, nixpkgs }:
+    let
+      system = "x86_64-linux";
+      pkgs = nixpkgs.legacyPackages.${system};
+    in {
+      devShells.${system}.default = pkgs.mkShell {
+        buildInputs = [
+          pkgs.plantuml
+          pkgs.graphviz
+        ];
+      };
+    };
+}

semestralka_1_final_crate/software_uart/docs/rx_uml.txt

@@ -0,0 +1,35 @@
+@startuml
+title TIM7 → DMA → ReadableRingBuffer → rx_dma_task
+
+start
+
+:TIM7 tick (oversampling);
+
+:DMA interrupts ON;
+:DMA ringbuffer setup;
+
+repeat
+  :'read_exact' cakanie na byty o velkosti CHUNK_SIZE;
+
+  :Extract Rx z IDR → level_buf;
+
+  :current_end = valid_len + CHUNK_SIZE;
+
+  :Dekodovanie decode_uart_samples(level_buf[0..current_end]);
+
+  if (decoded byty existuju?) then (ano)
+    :pipe_rx.write(decoded);
+  endif
+
+  :Posunutie level_buf vlavo o 'consumed';
+  :valid_len = remaining;
+
+  if (valid_len >= HISTORY_SIZE?) then (ano)
+    :Zmensenie o HISTORY_SIZE/2;
+    :valid_len = HISTORY_SIZE/2;
+  endif
+
+  :yield_now();
+
+repeat while (true)
+@enduml

semestralka_1_final_crate/software_uart/docs/tx_uml.txt

@@ -0,0 +1,29 @@
+@startuml
+title pipe_rx → DMA → GPIOx_BSRR
+
+start
+
+
+
+repeat
+  :n = pipe_rx.read(rx_buf);
+  
+  if (n > 0?) then (ano)
+    :Enkodovanie rx_buf → frame_buf\n(encode_uart_frames);
+    
+    if (used > 0?) then (ano)
+      :TIM6.SR.UIF = false;
+      :Cakanie na TIM6 tick;
+      :TIM6.SR.UIF = false;
+      
+      :DMA Transfer\nframe_buf → GPIOx_BSRR;
+      :Transfer await;
+    endif
+  endif
+  
+  :yield_now();
+
+repeat while (true)
+
+stop
+@enduml

semestralka_1_final_crate/software_uart/src/debug.rs

@@ -0,0 +1,43 @@
+// src/debug.rs
+use defmt::info;
+
+pub fn dump_tim6_regs() {
+    use embassy_stm32::pac::timer::TimBasic;
+    let tim = unsafe { TimBasic::from_ptr(0x4000_1000usize as _) };
+    let sr = tim.sr().read();
+    let dier = tim.dier().read();
+    let cr1 = tim.cr1().read();
+    let arr = tim.arr().read().arr();
+    let psc = tim.psc().read();
+    info!(
+        "TIM6: CR1.CEN={} DIER.UDE={} SR.UIF={} PSC={} ARR={}",
+        cr1.cen(),
+        dier.ude(),
+        sr.uif(),
+        psc,
+        arr
+    );
+}
+
+pub fn dump_dma_ch0_regs() {
+    use embassy_stm32::pac::gpdma::Gpdma;
+    let dma = unsafe { Gpdma::from_ptr(0x4002_0000usize as _) };
+    let ch = dma.ch(0);
+    let cr = ch.cr().read();
+    let tr1 = ch.tr1().read();
+    let tr2 = ch.tr2().read();
+    let br1 = ch.br1().read();
+    info!(
+        "GPDMA1_CH0: EN={} PRIO={} SDW={} DDW={} SINC={} DINC={} REQSEL={} SWREQ={} DREQ={} BNDT={}",
+        cr.en(),
+        cr.prio(),
+        tr1.sdw(),
+        tr1.ddw(),
+        tr1.sinc(),
+        tr1.dinc(),
+        tr2.reqsel(),
+        tr2.swreq(),
+        tr2.dreq(),
+        br1.bndt()
+    );
+}

semestralka_1_final_crate/software_uart/src/dma_timer.rs

@@ -0,0 +1,39 @@
+// src/dma_timer.rs
+
+use embassy_stm32::{
+    peripherals::{TIM6, TIM7},
+    timer::low_level::Timer,
+    Peri,
+    time::Hertz,
+};
+use core::mem;
+use embassy_stm32::timer::BasicInstance;
+
+/// Initializes TIM6 to tick at `baud * oversample` frequency.
+/// Each TIM6 update event triggers one DMA beat.
+pub fn init_tim6_for_uart<'d>(tim6: Peri<'d, TIM6>, baud: u32, oversample: u16) {
+    let ll = Timer::new(tim6);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+/// Initializes TIM7 to tick at `baud * oversample` frequency.
+/// Each TIM7 update event triggers one DMA beat.
+pub fn init_tim7_for_uart<'d>(tim7: Peri<'d, TIM7>, baud: u32, oversample: u16) {
+    let ll = Timer::new(tim7);
+    configure_basic_timer(&ll, baud, oversample);
+    ll.enable_update_interrupt(false); //Disable CPU interrupts
+    mem::forget(ll);
+}
+
+fn configure_basic_timer<T: BasicInstance>(ll: &Timer<'_, T>, baud: u32, oversample: u16) {
+    let target = baud.saturating_mul(oversample.max(1) as u32).max(1);
+    let target_freq = Hertz(target);
+
+    ll.stop();
+    ll.set_frequency(target_freq);
+    ll.enable_update_dma(true);
+
+    ll.clear_update_interrupt();
+    ll.start();
+}

semestralka_1_final_crate/software_uart/src/gpio_dma_uart_rx.rs

@@ -0,0 +1,98 @@
+// src/gpio_dma_uart_rx.rs
+
+use embassy_executor::task;
+use embassy_stm32::{
+    dma::Request,
+    peripherals::GPDMA1_CH1,
+    Peri,
+};
+use embassy_stm32::dma::{
+    ReadableRingBuffer,
+    TransferOptions,
+};
+use crate::decode_uart_samples;
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use embassy_futures::yield_now;
+use crate::UartConfig;
+use defmt::info;
+
+// datasheet tabulka 137
+pub const TIM7_UP_REQ: Request = 5;
+
+/// RX DMA task: reads GPIO samples paced by TIM7 and fills PIPE_RX
+#[task]
+pub async fn rx_dma_task(
+    ch: Peri<'static, GPDMA1_CH1>,
+    register: *mut u8,
+    ring: &'static mut [u8],
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 4096>,
+    rx_pin_bit: u8,
+    rx_oversample: u16,
+    uart_cfg: &'static UartConfig,
+) {
+    let mut opts = TransferOptions::default();
+    opts.half_transfer_ir = true;
+    opts.complete_transfer_ir = true;
+
+    // SAFETY: ring is exclusive to this task
+    let mut rx = unsafe {
+        ReadableRingBuffer::new(
+            ch,
+            TIM7_UP_REQ,
+            register,
+            ring,
+            opts
+        )
+    };
+    rx.start();
+
+    const CHUNK_SIZE: usize = 4096;
+    const HISTORY_SIZE: usize = 512;
+    const TOTAL_BUF_SIZE: usize = HISTORY_SIZE + CHUNK_SIZE;
+    
+    let mut level_buf = [0u8; TOTAL_BUF_SIZE];
+    let mut valid_len = 0usize; 
+
+    let mut raw_chunk = [0u8; CHUNK_SIZE];
+
+    loop {
+        let _ = rx.read_exact(&mut raw_chunk).await;
+
+        // Extract Rx pin value from IDR
+        for (i, b) in raw_chunk.iter().enumerate() {
+             level_buf[valid_len + i] = ((*b >> rx_pin_bit) & 1) as u8;
+        }
+        let current_end = valid_len + CHUNK_SIZE;
+
+        let (decoded, consumed) = decode_uart_samples(
+            &level_buf[..current_end], 
+            rx_oversample,
+            uart_cfg
+        );
+
+        if !decoded.is_empty() {
+             pipe_rx.write(decoded.as_slice()).await;
+
+             // for byte in decoded.as_slice() {
+                 // info!("DMA BUFFER CHAR: {} (ASCII: {})", *byte, *byte as char);
+             // }
+        }
+
+        // Shift remaining data to history partition 
+        let remaining = current_end - consumed;
+        
+        if remaining > 0 {
+            level_buf.copy_within(consumed..current_end, 0);
+        }
+        valid_len = remaining;
+        
+        // SAFETY if decoder is stuck and buffer is filling up, discard old data
+        if valid_len >= HISTORY_SIZE {
+             let keep = HISTORY_SIZE / 2;
+             level_buf.copy_within(valid_len - keep..valid_len, 0);
+             valid_len = keep;
+        }
+
+        yield_now().await;
+    }
+}

semestralka_1_final_crate/software_uart/src/gpio_dma_uart_tx.rs

@@ -0,0 +1,91 @@
+// src/gpio_dma_uart_tx.rs
+use embassy_executor::task;
+use embassy_stm32::{
+    dma::{Request, Transfer, TransferOptions},
+    peripherals::GPDMA1_CH0,
+    Peri,
+};
+use embassy_futures::yield_now;
+use defmt::info;
+
+use crate::UartConfig;
+use embassy_sync::pipe::Pipe;
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use crate::uart_emulation::encode_uart_byte_cfg;
+
+pub const TIM6_UP_REQ: Request = 4;
+
+pub async fn encode_uart_frames<'a>(
+    pin_bit: u8,
+    bytes: &[u8],
+    out_buf: &'a mut [u32],
+    uart_cfg: &UartConfig,
+) -> usize {
+    let mut offset = 0;
+    for &b in bytes {
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(pin_bit, b, uart_cfg, &mut frame);
+
+        if offset + used <= out_buf.len() {
+            out_buf[offset..offset + used].copy_from_slice(&frame[..used]);
+            offset += used;
+        } else {
+            break;
+        }
+
+        yield_now().await;
+    }
+    offset
+}
+
+#[task]
+pub async fn tx_dma_task(
+    mut ch: Peri<'static, GPDMA1_CH0>,
+    register: *mut u32, // GPIOx_BSRR
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+    tx_pin_bit: u8,
+    uart_cfg: &'static UartConfig,
+) {
+    info!("TX DMA task ready (One‑shot)");
+    let mut frame_buf = [0u32; 4096];
+    let mut rx_buf = [0u8; 256];
+    let tim6 = embassy_stm32::pac::TIM6;
+
+    loop {
+        let n = pipe_rx.read(&mut rx_buf).await;
+        if n == 0 {
+            yield_now().await;
+            continue;
+        }
+
+        let used = encode_uart_frames(tx_pin_bit, &rx_buf[..n], &mut frame_buf, uart_cfg).await;
+        if used > 0 {
+            // Clear pending UIF
+            tim6.sr().write(|w| w.set_uif(false));
+            // Wait for the next UIF (next bit tick)
+            while !tim6.sr().read().uif() {
+                yield_now().await;
+            }
+            // Clear UIF so first DMA beat happens on the FOLLOWING tick
+            tim6.sr().write(|w| w.set_uif(false));
+
+            let mut tx_opts = TransferOptions::default();
+            tx_opts.half_transfer_ir = false;
+            tx_opts.complete_transfer_ir = true;
+
+            unsafe {
+                let transfer = Transfer::new_write(
+                    ch.reborrow(),
+                    TIM6_UP_REQ,
+                    &frame_buf[..used],
+                    register,
+                    tx_opts,
+                );
+                transfer.await;
+            }
+        }
+
+        // info!("tx_dma_task sent {} words", used);
+        yield_now().await;
+    }
+}

semestralka_1_final_crate/software_uart/src/lib.rs

@@ -0,0 +1,15 @@
+// src/lib.rs
+
+#![no_std]
+
+pub mod gpio_dma_uart_tx;
+pub mod gpio_dma_uart_rx;
+pub mod dma_timer;
+pub mod uart_emulation;
+pub mod debug;
+
+pub use gpio_dma_uart_tx::*;
+pub use gpio_dma_uart_rx::*;
+pub use dma_timer::*;
+pub use uart_emulation::*;
+pub use debug::*;

semestralka_1_final_crate/software_uart/src/uart_emulation.rs

@@ -0,0 +1,207 @@
+// src/uart_emulation.rs
+
+use heapless::Vec;
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Parity {
+    None,
+    Even,
+    Odd,
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum StopBits {
+    One,
+    Two,
+}
+
+#[derive(Clone, Copy, Debug)]
+pub struct UartConfig {
+    pub data_bits: u8,
+    pub parity: Parity,
+    pub stop_bits: StopBits,
+}
+
+impl Default for UartConfig {
+    fn default() -> Self {
+        Self {
+            data_bits: 8,
+            parity: Parity::None,
+            stop_bits: StopBits::One,
+        }
+    }
+}
+
+/// Encodes one byte into a sequence of GPIO BSRR words
+pub fn encode_uart_byte_cfg(
+    pin_bit: u8,
+    data: u8,
+    cfg: &UartConfig,
+    out: &mut [u32; 12],
+) -> usize {
+    // GPIOx_BSRR register str. 636 kap. 13.4.7
+    let set_high = |bit: u8| -> u32 { 1u32 << bit };
+    // let set_low = |bit: u8| -> u32 { 0 }; // ODR
+    let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) }; // BSRR
+
+    let nbits = cfg.data_bits;
+    let mut idx = 0usize;
+
+    // START bit (LOW)
+    out[idx] = set_low(pin_bit);
+    idx += 1;
+
+    // Data bits, LSB-first
+    for i in 0..nbits {
+        let one = ((data >> i) & 1) != 0;
+        out[idx] = if one { set_high(pin_bit) } else { set_low(pin_bit) };
+        idx += 1;
+    }
+
+    // Parity
+    match cfg.parity {
+        Parity::None => {}
+        Parity::Even | Parity::Odd => {
+            let mask: u8 = if nbits == 8 { 0xFF } else { (1u16 << nbits) as u8 - 1 };
+            let ones = (data & mask).count_ones() & 1;
+            let par_bit_is_one = match cfg.parity {
+                Parity::Even => ones == 1,
+                Parity::Odd => ones == 0,
+                _ => false,
+            };
+            out[idx] = if par_bit_is_one {
+                set_high(pin_bit)
+            } else {
+                set_low(pin_bit)
+            };
+            idx += 1;
+        }
+    }
+
+    // STOP bits (HIGH)
+    let stop_ticks = match cfg.stop_bits {
+        StopBits::One => 1,
+        StopBits::Two => 2,
+    };
+    for _ in 0..stop_ticks {
+        out[idx] = set_high(pin_bit);
+        idx += 1;
+    }
+
+    idx
+}
+
+/// Decode an oversampled stream of logic levels into UART bytes.
+/// Returns (decoded bytes, number of samples consumed/processed).
+pub fn decode_uart_samples(
+    samples: &[u8],
+    oversample: u16,
+    cfg: &UartConfig,
+) -> (heapless::Vec<u8, 256>, usize) {
+    let mut out = Vec::<u8, 256>::new();
+    let mut idx = 0usize;
+    let nbits = cfg.data_bits as usize;
+    let ovs = oversample as usize;
+
+    // Calculate total frame width in samples to ensure we have enough data
+    // 1 start + n data + parity? + stops
+    let parity_bits = match cfg.parity {
+        Parity::None => 0,
+        _ => 1,
+    };
+    let stop_bits_count = match cfg.stop_bits {
+        StopBits::One => 1,
+        StopBits::Two => 2,
+    };
+    let frame_bits = 1 + nbits + parity_bits + stop_bits_count;
+    let frame_len = frame_bits * ovs;
+
+    // Get sample in the middle of the bit
+    let get_bit = |i: usize| -> u8 {
+        if samples[i] != 0 { 1 } else { 0 }
+    };
+
+    // Decode while remaining samples for a full frame
+    while idx + frame_len <= samples.len() {
+        // Start - idle HIGH to start LOW
+        if samples[idx] != 0 && samples[idx + 1] == 0 {
+            let center_offset = ovs / 2;
+            let mut scan_idx = idx + center_offset;
+
+            // Validate Start Bit
+            if get_bit(scan_idx) != 0 {
+                idx += 1; // False start (noise), move on
+                continue;
+            }
+
+            // Move to center of first data bit
+            scan_idx += ovs;
+
+            // Read Data Bits
+            let mut data: u8 = 0;
+            for bit in 0..nbits {
+                if get_bit(scan_idx) == 1 {
+                    data |= 1 << bit;
+                }
+                scan_idx += ovs;
+            }
+
+            let mut error_data = false;
+            if cfg.parity != Parity::None {
+                let expected_parity = calculate_parity(data, cfg.parity);
+                let actual_parity = get_bit(scan_idx);
+                if expected_parity != actual_parity {
+                    // Parity error
+                    error_data = true;
+                }
+                scan_idx += ovs;
+            }
+
+            for _ in 0..stop_bits_count {
+                if get_bit(scan_idx) == 0 {
+                    // Framing error
+                    error_data = true;
+                    break;
+                }
+                scan_idx += ovs;
+            }
+            if error_data {
+                idx += 1;
+                continue;  // Skip this frame completely
+            }
+
+            let _ = out.push(data);
+            idx = scan_idx;
+
+            // Next startbit reach
+            while idx < samples.len() && samples[idx] != 0 {
+                idx += 1;
+            }
+
+            // Mensi hack
+            if idx > 0 {
+                idx -= 1;
+            }
+        } else {
+            // No start bit detected here, move to next sample
+            idx += 1;
+        }
+    }
+
+    (out, idx)
+}
+
+/// Calculate the expected parity bit (0 or 1) for the given data and parity mode
+fn calculate_parity(data: u8, parity: Parity) -> u8 {
+    match parity {
+        Parity::None => 0,
+        Parity::Even | Parity::Odd => {
+            let ones = data.count_ones() & 1;
+            match parity {
+                Parity::Even => ones as u8,  // If ones=1 (odd), emit 1 to make even
+                Parity::Odd => (ones ^ 1) as u8,  // XOR - If ones=1 (odd), emit 0 to keep odd
+                _ => 0,
+            }
+        }
+    }
+}

semestralka_1_final_lib/.cargo/config.toml

@@ -0,0 +1,15 @@
+[build]
+target = "thumbv8m.main-none-eabihf"
+
+[target.thumbv8m.main-none-eabihf]
+runner = "probe-rs run --chip STM32U575ZITxQ"
+
+rustflags = [
+  "-C", "linker=rust-lld",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "link-arg=-Tdefmt.x",
+  "-C", "link-arg=--nmagic",
+]
+
+[package.metadata.cargo-flash]
+chip = "STM32U575ZIT"