finished and fully functional

time to do final merge
dma used to transfer Tx
2025-11-19 23:30:55 +01:00 · 2025-11-19 21:46:07 +01:00 · 2025-11-19 21:41:08 +01:00 · 2025-11-19 21:12:41 +01:00 · 2025-11-19 20:40:13 +01:00 · 2025-11-19 20:28:24 +01:00
298 changed files with 32489 additions and 247 deletions
--- a/dma_gpio/src/bin/main.rs
+++ b/dma_gpio/src/bin/main.rs
@@ -4,24 +4,27 @@

 use defmt::*;
 use embassy_executor::Spawner;
+use embassy_stm32::dma::Request;
 use embassy_stm32::gpio::{Input, Output, Level, Pull, Speed};
 use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
-use embassy_time::{Duration, Timer};
 use embassy_stm32::dma::{TransferOptions, WritableRingBuffer};
 use dma_gpio::software_uart::{
    dma_timer::{init_tim6_for_uart, init_tim7_for_uart},
-    gpio_dma_uart_tx::{write_uart_frames_to_ring, TIM6_UP_REQ},
+    gpio_dma_uart_tx::encode_uart_frames,
    gpio_dma_uart_rx::rx_dma_task,
    debug::dump_tim6_regs,
 };
 use dma_gpio::config::{BAUD, TX_PIN_BIT, RX_OVERSAMPLE, TX_OVERSAMPLE};
 use dma_gpio::config::{TX_RING_BYTES, RX_RING_BYTES, PIPE_RX_SIZE};
 use static_cell::StaticCell;
+use embassy_futures::yield_now;
 use {defmt_rtt as _, panic_probe as _};

+pub const TIM6_UP_REQ: Request = 4;
+
 static PIPE_RX: Pipe<CriticalSectionRawMutex, PIPE_RX_SIZE> = Pipe::new();
-static RX_RING: StaticCell<[u8; RX_RING_BYTES]> = StaticCell::new();
 static TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
+static RX_RING: StaticCell<[u8; RX_RING_BYTES]> = StaticCell::new();

 #[embassy_executor::main]
 async fn main(spawner: Spawner) {
@@ -64,16 +67,26 @@ async fn main(spawner: Spawner) {
    tx_ring.start();
    info!("TX DMA ring started");

+    let mut frame_buf = [0u32; 4096];
+
    loop {
        info!("tick start");
-        Timer::after(Duration::from_millis(100)).await;
-        info!("tick end");
-        write_uart_frames_to_ring(
-            &mut tx_ring,
+        // Timer::after(Duration::from_millis(100)).await;
+        // info!("tick end");
+        let used = encode_uart_frames(
            TX_PIN_BIT,
            b"Hello marshmallow\r\n",
-        ).await;
+            &mut frame_buf,
+        )
+        .await;
+
+        if used == 0 {
+            info!("encode_uart_frames() produced 0 words, skipping write");
+            yield_now().await;
+            continue;
+        }
+        let _ = tx_ring.write_exact(&frame_buf[..used]).await;
        info!("text");
-        Timer::after(Duration::from_secs(1)).await;
+        yield_now().await;
    }
 }
--- a/dma_gpio/src/software_uart/gpio_dma_uart_tx.rs
+++ b/dma_gpio/src/software_uart/gpio_dma_uart_tx.rs
@@ -1,23 +1,28 @@
 // src/software_uart/gpio_dma_uart_tx.rs
-use embassy_stm32::dma::Request;
-use embassy_stm32::dma::WritableRingBuffer;
+use embassy_futures::yield_now;
 use crate::software_uart::uart_emulation::encode_uart_byte_cfg;
 use crate::config::UART_CFG;

-// kapitola 17.4.11 - 2 casovace pre 2 DMA
-pub const TIM6_UP_REQ: Request = 4; // Table 137: tim6_upd_dma, strana 687 STM32U5xx datasheet
-
-/// Push UART frames into the DMA-backed TX ring
-pub async fn write_uart_frames_to_ring(
-    ring: &mut WritableRingBuffer<'static, u32>,
+pub async fn encode_uart_frames<'a>(
    pin_bit: u8,
    bytes: &[u8],
-) {
+    out_buf: &'a mut [u32],
+) -> usize {
+    let mut offset = 0;
    for &b in bytes {
        let mut frame = [0u32; 12];
        let used = encode_uart_byte_cfg(pin_bit, b, &UART_CFG, &mut frame);

-        // Will wait until all words are written
-        ring.write_exact(&frame[..used]).await.unwrap();
+        if offset + used <= out_buf.len() {
+            out_buf[offset..offset + used].copy_from_slice(&frame[..used]);
+            offset += used;
+        } else {
+            break;
+        }
+
+        // cooperative async yield
+        yield_now().await;
    }
+    offset
 }
+
--- a/flake.nix
+++ b/flake.nix
@@ -59,6 +59,7 @@
        echo "cargo flash --release --chip STM32U575ZI"
 	echo "cargo run --bin main"
 	echo "probe-rs run --chip STM32U575ZITxQ target/thumbv8m.main-none-eabihf/release/main"
+	echo "probe-rs erase --chip STM32U575ZITxQ"
 	echo "target/**/build/embassy-stm32-*/out/_generated.rs"
      '';
    };
--- a/semestralka_1/Cargo.lock
+++ b/semestralka_1/Cargo.lock
@@ -14,6 +14,15 @@ dependencies = [
 "zerocopy",
 ]

+[[package]]
+name = "aho-corasick"
+version = "1.1.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ddd31a130427c27518df266943a5308ed92d4b226cc639f5a8f1002816174301"
+dependencies = [
+ "memchr",
+]
+
 [[package]]
 name = "aligned"
 version = "0.4.2"
@@ -32,33 +41,6 @@ dependencies = [
 "stable_deref_trait",
 ]

-[[package]]
-name = "async_uart"
-version = "0.1.0"
-dependencies = [
- "cortex-m",
- "cortex-m-rt",
- "defmt 1.0.1",
- "defmt-rtt",
- "defmt-test",
- "embassy-executor",
- "embassy-futures",
- "embassy-stm32",
- "embassy-sync",
- "embassy-time",
- "embassy-usb",
- "embedded-graphics",
- "embedded-hal 1.0.0",
- "embedded-io",
- "embedded-io-async",
- "heapless 0.9.1",
- "micromath",
- "panic-halt",
- "panic-probe",
- "static_cell",
- "tinybmp",
-]
-
 [[package]]
 name = "autocfg"
 version = "1.5.0"
@@ -125,12 +107,32 @@ version = "1.5.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "1fd0f2584146f6f2ef48085050886acf353beff7305ebd1ae69500e27c67f64b"

+[[package]]
+name = "cc"
+version = "1.2.44"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "37521ac7aabe3d13122dc382493e20c9416f299d2ccd5b3a5340a2570cdeb0f3"
+dependencies = [
+ "find-msvc-tools",
+ "shlex",
+]
+
 [[package]]
 name = "cfg-if"
 version = "1.0.4"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801"

+[[package]]
+name = "cordyceps"
+version = "0.3.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "688d7fbb8092b8de775ef2536f36c8c31f2bc4006ece2e8d8ad2d17d00ce0a2a"
+dependencies = [
+ "loom",
+ "tracing",
+]
+
 [[package]]
 name = "cortex-m"
 version = "0.7.7"
@@ -288,6 +290,34 @@ dependencies = [
 "syn 2.0.107",
 ]

+[[package]]
+name = "dma_gpio"
+version = "0.1.0"
+dependencies = [
+ "cortex-m",
+ "cortex-m-rt",
+ "defmt 1.0.1",
+ "defmt-rtt",
+ "defmt-test",
+ "embassy-executor",
+ "embassy-futures",
+ "embassy-hal-internal",
+ "embassy-stm32",
+ "embassy-sync",
+ "embassy-time",
+ "embassy-usb",
+ "embedded-graphics",
+ "embedded-hal 1.0.0",
+ "embedded-io",
+ "embedded-io-async",
+ "heapless 0.9.1",
+ "micromath",
+ "panic-halt",
+ "panic-probe",
+ "static_cell",
+ "tinybmp",
+]
+
 [[package]]
 name = "document-features"
 version = "0.2.11"
@@ -300,8 +330,7 @@ dependencies = [
 [[package]]
 name = "embassy-embedded-hal"
 version = "0.5.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "554e3e840696f54b4c9afcf28a0f24da431c927f4151040020416e7393d6d0d8"
+source = "git+https://github.com/embassy-rs/embassy.git?branch=main#9b1add3d83e98c6c9ae9230bf35cd89bba530a20"
 dependencies = [
 "defmt 1.0.1",
 "embassy-futures",
@@ -319,9 +348,9 @@ dependencies = [
 [[package]]
 name = "embassy-executor"
 version = "0.9.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "06070468370195e0e86f241c8e5004356d696590a678d47d6676795b2e439c6b"
+source = "git+https://github.com/embassy-rs/embassy.git?branch=main#9b1add3d83e98c6c9ae9230bf35cd89bba530a20"
 dependencies = [
+ "cordyceps",
 "cortex-m",
 "critical-section",
 "document-features",
@@ -332,8 +361,7 @@ dependencies = [
 [[package]]
 name = "embassy-executor-macros"
 version = "0.7.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "dfdddc3a04226828316bf31393b6903ee162238576b1584ee2669af215d55472"
+source = "git+https://github.com/embassy-rs/embassy.git?branch=main#9b1add3d83e98c6c9ae9230bf35cd89bba530a20"
 dependencies = [
 "darling",
 "proc-macro2",
@@ -344,20 +372,17 @@ dependencies = [
 [[package]]
 name = "embassy-executor-timer-queue"
 version = "0.1.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "2fc328bf943af66b80b98755db9106bf7e7471b0cf47dc8559cd9a6be504cc9c"
+source = "git+https://github.com/embassy-rs/embassy.git?branch=main#9b1add3d83e98c6c9ae9230bf35cd89bba530a20"

 [[package]]
 name = "embassy-futures"
 version = "0.1.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "dc2d050bdc5c21e0862a89256ed8029ae6c290a93aecefc73084b3002cdebb01"
+source = "git+https://github.com/embassy-rs/embassy.git?branch=main#9b1add3d83e98c6c9ae9230bf35cd89bba530a20"

 [[package]]
 name = "embassy-hal-internal"
 version = "0.3.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "95285007a91b619dc9f26ea8f55452aa6c60f7115a4edc05085cd2bd3127cd7a"
+source = "git+https://github.com/embassy-rs/embassy.git?branch=main#9b1add3d83e98c6c9ae9230bf35cd89bba530a20"
 dependencies = [
 "cortex-m",
 "critical-section",
@@ -368,17 +393,15 @@ dependencies = [
 [[package]]
 name = "embassy-net-driver"
 version = "0.2.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "524eb3c489760508f71360112bca70f6e53173e6fe48fc5f0efd0f5ab217751d"
+source = "git+https://github.com/embassy-rs/embassy.git?branch=main#9b1add3d83e98c6c9ae9230bf35cd89bba530a20"
 dependencies = [
- "defmt 0.3.100",
+ "defmt 1.0.1",
 ]

 [[package]]
 name = "embassy-net-driver-channel"
 version = "0.3.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b7b2739fbcf6cd206ae08779c7d709087b16577d255f2ea4a45bc4bbbf305b3f"
+source = "git+https://github.com/embassy-rs/embassy.git?branch=main#9b1add3d83e98c6c9ae9230bf35cd89bba530a20"
 dependencies = [
 "embassy-futures",
 "embassy-net-driver",
@@ -388,8 +411,7 @@ dependencies = [
 [[package]]
 name = "embassy-stm32"
 version = "0.4.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0d972eab325cc96afee98f80a91ca6b00249b6356dc0fdbff68b70c200df9fae"
+source = "git+https://github.com/embassy-rs/embassy.git?branch=main#9b1add3d83e98c6c9ae9230bf35cd89bba530a20"
 dependencies = [
 "aligned",
 "bit_field",
@@ -421,6 +443,7 @@ dependencies = [
 "embedded-storage",
 "embedded-storage-async",
 "futures-util",
+ "heapless 0.9.1",
 "nb 1.1.0",
 "proc-macro2",
 "quote",
@@ -437,8 +460,7 @@ dependencies = [
 [[package]]
 name = "embassy-sync"
 version = "0.7.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "73974a3edbd0bd286759b3d483540f0ebef705919a5f56f4fc7709066f71689b"
+source = "git+https://github.com/embassy-rs/embassy.git?branch=main#9b1add3d83e98c6c9ae9230bf35cd89bba530a20"
 dependencies = [
 "cfg-if",
 "critical-section",
@@ -452,8 +474,7 @@ dependencies = [
 [[package]]
 name = "embassy-time"
 version = "0.5.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f4fa65b9284d974dad7a23bb72835c4ec85c0b540d86af7fc4098c88cff51d65"
+source = "git+https://github.com/embassy-rs/embassy.git?branch=main#9b1add3d83e98c6c9ae9230bf35cd89bba530a20"
 dependencies = [
 "cfg-if",
 "critical-section",
@@ -469,8 +490,7 @@ dependencies = [
 [[package]]
 name = "embassy-time-driver"
 version = "0.2.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a0a244c7dc22c8d0289379c8d8830cae06bb93d8f990194d0de5efb3b5ae7ba6"
+source = "git+https://github.com/embassy-rs/embassy.git?branch=main#9b1add3d83e98c6c9ae9230bf35cd89bba530a20"
 dependencies = [
 "document-features",
 ]
@@ -478,8 +498,7 @@ dependencies = [
 [[package]]
 name = "embassy-time-queue-utils"
 version = "0.3.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "80e2ee86063bd028a420a5fb5898c18c87a8898026da1d4c852af2c443d0a454"
+source = "git+https://github.com/embassy-rs/embassy.git?branch=main#9b1add3d83e98c6c9ae9230bf35cd89bba530a20"
 dependencies = [
 "embassy-executor-timer-queue",
 "heapless 0.8.0",
@@ -488,8 +507,7 @@ dependencies = [
 [[package]]
 name = "embassy-usb"
 version = "0.5.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "dc4462e48b19a4f401a11901bdd981aab80c6a826608016a0bdc73cbbab31954"
+source = "git+https://github.com/embassy-rs/embassy.git?branch=main#9b1add3d83e98c6c9ae9230bf35cd89bba530a20"
 dependencies = [
 "embassy-futures",
 "embassy-net-driver-channel",
@@ -504,8 +522,7 @@ dependencies = [
 [[package]]
 name = "embassy-usb-driver"
 version = "0.2.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "17119855ccc2d1f7470a39756b12068454ae27a3eabb037d940b5c03d9c77b7a"
+source = "git+https://github.com/embassy-rs/embassy.git?branch=main#9b1add3d83e98c6c9ae9230bf35cd89bba530a20"
 dependencies = [
 "defmt 1.0.1",
 "embedded-io-async",
@@ -514,8 +531,7 @@ dependencies = [
 [[package]]
 name = "embassy-usb-synopsys-otg"
 version = "0.3.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "288751f8eaa44a5cf2613f13cee0ca8e06e6638cb96e897e6834702c79084b23"
+source = "git+https://github.com/embassy-rs/embassy.git?branch=main#9b1add3d83e98c6c9ae9230bf35cd89bba530a20"
 dependencies = [
 "critical-section",
 "defmt 1.0.1",
@@ -630,6 +646,12 @@ version = "0.3.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "a357d28ed41a50f9c765dbfe56cbc04a64e53e5fc58ba79fbc34c10ef3df831f"

+[[package]]
+name = "find-msvc-tools"
+version = "0.1.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "52051878f80a721bb68ebfbc930e07b65ba72f2da88968ea5c06fd6ca3d3a127"
+
 [[package]]
 name = "float-cmp"
 version = "0.9.0"
@@ -675,6 +697,20 @@ dependencies = [
 "pin-utils",
 ]

+[[package]]
+name = "generator"
+version = "0.8.7"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "605183a538e3e2a9c1038635cc5c2d194e2ee8fd0d1b66b8349fad7dbacce5a2"
+dependencies = [
+ "cc",
+ "cfg-if",
+ "libc",
+ "log",
+ "rustversion",
+ "windows",
+]
+
 [[package]]
 name = "hash32"
 version = "0.3.1"
@@ -719,6 +755,18 @@ version = "1.0.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "b9e0384b61958566e926dc50660321d12159025e767c18e043daf26b70104c39"

+[[package]]
+name = "lazy_static"
+version = "1.5.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "bbd2bcb4c963f2ddae06a2efc7e9f3591312473c50c6685e1f298068316e66fe"
+
+[[package]]
+name = "libc"
+version = "0.2.177"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "2874a2af47a2325c2001a6e6fad9b16a53b802102b528163885171cf92b15976"
+
 [[package]]
 name = "litrs"
 version = "0.4.2"
@@ -731,6 +779,34 @@ version = "0.4.28"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "34080505efa8e45a4b816c349525ebe327ceaa8559756f0356cba97ef3bf7432"

+[[package]]
+name = "loom"
+version = "0.7.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "419e0dc8046cb947daa77eb95ae174acfbddb7673b4151f56d1eed8e93fbfaca"
+dependencies = [
+ "cfg-if",
+ "generator",
+ "scoped-tls",
+ "tracing",
+ "tracing-subscriber",
+]
+
+[[package]]
+name = "matchers"
+version = "0.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d1525a2a28c7f4fa0fc98bb91ae755d1e2d1505079e05539e35bc876b5d65ae9"
+dependencies = [
+ "regex-automata",
+]
+
+[[package]]
+name = "memchr"
+version = "2.7.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f52b00d39961fc5b2736ea853c9cc86238e165017a493d1d5c8eac6bdc4cc273"
+
 [[package]]
 name = "micromath"
 version = "2.1.0"
@@ -752,6 +828,15 @@ version = "1.1.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "8d5439c4ad607c3c23abf66de8c8bf57ba8adcd1f129e699851a6e43935d339d"

+[[package]]
+name = "nu-ansi-term"
+version = "0.50.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7957b9740744892f114936ab4a57b3f487491bbeafaf8083688b16841a4240e5"
+dependencies = [
+ "windows-sys",
+]
+
 [[package]]
 name = "num-traits"
 version = "0.2.19"
@@ -853,6 +938,23 @@ version = "0.9.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "99d9a13982dcf210057a8a78572b2217b667c3beacbf3a0d8b454f6f82837d38"

+[[package]]
+name = "regex-automata"
+version = "0.4.13"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5276caf25ac86c8d810222b3dbb938e512c55c6831a10f3e6ed1c93b84041f1c"
+dependencies = [
+ "aho-corasick",
+ "memchr",
+ "regex-syntax",
+]
+
+[[package]]
+name = "regex-syntax"
+version = "0.8.8"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7a2d987857b319362043e95f5353c0535c1f58eec5336fdfcf626430af7def58"
+
 [[package]]
 name = "rustc_version"
 version = "0.2.3"
@@ -862,6 +964,18 @@ dependencies = [
 "semver",
 ]

+[[package]]
+name = "rustversion"
+version = "1.0.22"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b39cdef0fa800fc44525c84ccb54a029961a8215f9619753635a9c0d2538d46d"
+
+[[package]]
+name = "scoped-tls"
+version = "1.0.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e1cf6437eb19a8f4a6cc0f7dca544973b0b78843adbfeb3683d1a94a0024a294"
+
 [[package]]
 name = "sdio-host"
 version = "0.9.0"
@@ -912,6 +1026,27 @@ dependencies = [
 "syn 2.0.107",
 ]

+[[package]]
+name = "sharded-slab"
+version = "0.1.7"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f40ca3c46823713e0d4209592e8d6e826aa57e928f09752619fc696c499637f6"
+dependencies = [
+ "lazy_static",
+]
+
+[[package]]
+name = "shlex"
+version = "1.3.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0fda2ff0d084019ba4d7c6f371c95d8fd75ce3524c3cb8fb653a3023f6323e64"
+
+[[package]]
+name = "smallvec"
+version = "1.15.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "67b1b7a3b5fe4f1376887184045fcf45c69e92af734b7aaddc05fb777b6fbd03"
+
 [[package]]
 name = "ssmarshal"
 version = "1.0.0"
@@ -955,8 +1090,7 @@ dependencies = [
 [[package]]
 name = "stm32-metapac"
 version = "18.0.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "6fd8ec3a292a0d9fc4798416a61b21da5ae50341b2e7b8d12e662bf305366097"
+source = "git+https://github.com/embassy-rs/stm32-data-generated?tag=stm32-data-b9f6b0c542d85ee695d71c35ced195e0cef51ac0#9b8fb67703361e2237b6c1ec4f1ee5949223d412"
 dependencies = [
 "cortex-m",
 "cortex-m-rt",
@@ -1011,6 +1145,15 @@ dependencies = [
 "syn 2.0.107",
 ]

+[[package]]
+name = "thread_local"
+version = "1.1.9"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f60246a4944f24f6e018aa17cdeffb7818b76356965d03b07d6a9886e8962185"
+dependencies = [
+ "cfg-if",
+]
+
 [[package]]
 name = "tinybmp"
 version = "0.6.0"
@@ -1020,6 +1163,67 @@ dependencies = [
 "embedded-graphics",
 ]

+[[package]]
+name = "tracing"
+version = "0.1.41"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "784e0ac535deb450455cbfa28a6f0df145ea1bb7ae51b821cf5e7927fdcfbdd0"
+dependencies = [
+ "pin-project-lite",
+ "tracing-attributes",
+ "tracing-core",
+]
+
+[[package]]
+name = "tracing-attributes"
+version = "0.1.30"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "81383ab64e72a7a8b8e13130c49e3dab29def6d0c7d76a03087b3cf71c5c6903"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn 2.0.107",
+]
+
+[[package]]
+name = "tracing-core"
+version = "0.1.34"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b9d12581f227e93f094d3af2ae690a574abb8a2b9b7a96e7cfe9647b2b617678"
+dependencies = [
+ "once_cell",
+ "valuable",
+]
+
+[[package]]
+name = "tracing-log"
+version = "0.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ee855f1f400bd0e5c02d150ae5de3840039a3f54b025156404e34c23c03f47c3"
+dependencies = [
+ "log",
+ "once_cell",
+ "tracing-core",
+]
+
+[[package]]
+name = "tracing-subscriber"
+version = "0.3.20"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "2054a14f5307d601f88daf0553e1cbf472acc4f2c51afab632431cdcd72124d5"
+dependencies = [
+ "matchers",
+ "nu-ansi-term",
+ "once_cell",
+ "regex-automata",
+ "sharded-slab",
+ "smallvec",
+ "thread_local",
+ "tracing",
+ "tracing-core",
+ "tracing-log",
+]
+
 [[package]]
 name = "unicode-ident"
 version = "1.0.19"
@@ -1073,6 +1277,12 @@ dependencies = [
 "usbd-hid-descriptors",
 ]

+[[package]]
+name = "valuable"
+version = "0.1.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ba73ea9cf16a25df0c8caa16c51acb937d5712a8429db78a3ee29d5dcacd3a65"
+
 [[package]]
 name = "vcell"
 version = "0.1.3"
@@ -1100,6 +1310,132 @@ dependencies = [
 "vcell",
 ]

+[[package]]
+name = "windows"
+version = "0.61.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9babd3a767a4c1aef6900409f85f5d53ce2544ccdfaa86dad48c91782c6d6893"
+dependencies = [
+ "windows-collections",
+ "windows-core",
+ "windows-future",
+ "windows-link 0.1.3",
+ "windows-numerics",
+]
+
+[[package]]
+name = "windows-collections"
+version = "0.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "3beeceb5e5cfd9eb1d76b381630e82c4241ccd0d27f1a39ed41b2760b255c5e8"
+dependencies = [
+ "windows-core",
+]
+
+[[package]]
+name = "windows-core"
+version = "0.61.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "c0fdd3ddb90610c7638aa2b3a3ab2904fb9e5cdbecc643ddb3647212781c4ae3"
+dependencies = [
+ "windows-implement",
+ "windows-interface",
+ "windows-link 0.1.3",
+ "windows-result",
+ "windows-strings",
+]
+
+[[package]]
+name = "windows-future"
+version = "0.2.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "fc6a41e98427b19fe4b73c550f060b59fa592d7d686537eebf9385621bfbad8e"
+dependencies = [
+ "windows-core",
+ "windows-link 0.1.3",
+ "windows-threading",
+]
+
+[[package]]
+name = "windows-implement"
+version = "0.60.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "053e2e040ab57b9dc951b72c264860db7eb3b0200ba345b4e4c3b14f67855ddf"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn 2.0.107",
+]
+
+[[package]]
+name = "windows-interface"
+version = "0.59.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "3f316c4a2570ba26bbec722032c4099d8c8bc095efccdc15688708623367e358"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn 2.0.107",
+]
+
+[[package]]
+name = "windows-link"
+version = "0.1.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5e6ad25900d524eaabdbbb96d20b4311e1e7ae1699af4fb28c17ae66c80d798a"
+
+[[package]]
+name = "windows-link"
+version = "0.2.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f0805222e57f7521d6a62e36fa9163bc891acd422f971defe97d64e70d0a4fe5"
+
+[[package]]
+name = "windows-numerics"
+version = "0.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9150af68066c4c5c07ddc0ce30421554771e528bde427614c61038bc2c92c2b1"
+dependencies = [
+ "windows-core",
+ "windows-link 0.1.3",
+]
+
+[[package]]
+name = "windows-result"
+version = "0.3.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "56f42bd332cc6c8eac5af113fc0c1fd6a8fd2aa08a0119358686e5160d0586c6"
+dependencies = [
+ "windows-link 0.1.3",
+]
+
+[[package]]
+name = "windows-strings"
+version = "0.4.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "56e6c93f3a0c3b36176cb1327a4958a0353d5d166c2a35cb268ace15e91d3b57"
+dependencies = [
+ "windows-link 0.1.3",
+]
+
+[[package]]
+name = "windows-sys"
+version = "0.61.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ae137229bcbd6cdf0f7b80a31df61766145077ddf49416a728b02cb3921ff3fc"
+dependencies = [
+ "windows-link 0.2.1",
+]
+
+[[package]]
+name = "windows-threading"
+version = "0.1.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b66463ad2e0ea3bbf808b7f1d371311c80e115c0b71d60efc142cafbcfb057a6"
+dependencies = [
+ "windows-link 0.1.3",
+]
+
 [[package]]
 name = "zerocopy"
 version = "0.8.27"
--- a/semestralka_1/Cargo.toml
+++ b/semestralka_1/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 authors = ["Priec <filippriec@gmail.com>"]
-name = "async_uart"
+name = "dma_gpio"
 edition = "2024"
 version = "0.1.0"

@@ -10,12 +10,13 @@ cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-sing
 cortex-m-rt = "0.7.5"
 panic-halt = "1.0.0"

-embassy-executor = { version = "0.9.1", features = ["arch-cortex-m", "executor-thread"] }
-embassy-futures = "0.1.2"
-embassy-stm32 = { version = "0.4.0", features = ["unstable-pac", "stm32u575zi", "time-driver-any", "memory-x", "defmt"] }
-embassy-sync = "0.7.2"
-embassy-time = { version = "0.5.0", features = ["tick-hz-32_768"] }
-embassy-usb = "0.5.1"
+embassy-executor = { git = "https://github.com/embassy-rs/embassy.git", branch = "main", features = ["arch-cortex-m", "executor-thread"] }
+embassy-futures = { git = "https://github.com/embassy-rs/embassy.git", branch = "main" }
+embassy-sync    = { git = "https://github.com/embassy-rs/embassy.git", branch = "main" }
+embassy-time    = { git = "https://github.com/embassy-rs/embassy.git", branch = "main", features = ["tick-hz-32_768"] }
+embassy-hal-internal = { git = "https://github.com/embassy-rs/embassy.git", branch = "main" }
+embassy-usb = { git = "https://github.com/embassy-rs/embassy.git", branch = "main" }
+embassy-stm32 = { git = "https://github.com/embassy-rs/embassy.git", branch = "main", features = ["unstable-pac", "stm32u575zi", "time-driver-tim2", "memory-x", "defmt"] }

 embedded-hal = "1.0.0"
 embedded-graphics = "0.8.1"
@@ -26,8 +27,20 @@ panic-probe = { version = "1.0.0", features = ["defmt"] }
 defmt-rtt = "1.1.0"
 defmt = "1.0.1"
 static_cell = "2.1.1"
-embedded-io-async = "0.6.0"
 embedded-io = "0.6.1"
+embedded-io-async = "0.6.1"

 [dev-dependencies]
 defmt-test = "0.4.0"
+
+[[test]]
+name = "uart_emulation"
+harness = false
+
+[lib]
+test = false
+
+[[bin]]
+name = "main"
+path = "src/bin/main.rs"
+test = false
--- a/semestralka_1/datasheet.txt
+++ b/semestralka_1/datasheet.txt
@@ -1 +0,0 @@
-https://www.ti.com/lit/ug/sprugp1/sprugp1.pdf?ts=1761641486453
--- a/semestralka_1/src/bin/main.rs
+++ b/semestralka_1/src/bin/main.rs
@@ -1,157 +1,142 @@
 // src/bin/main.rs
-
 #![no_std]
 #![no_main]
+
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::bind_interrupts;
-use embassy_stm32::peripherals;
-use embassy_stm32::peripherals::{PA2, PA3};
-use embassy_stm32::gpio::{Input, Output, Pull, Speed, Level};
-use embassy_stm32::Peripherals;
-use embassy_stm32::usart::{BufferedInterruptHandler, BufferedUart, Config};
-use embassy_stm32::timer::low_level::Timer as HardwareTimer;
-use embassy_stm32::interrupt::{self, typelevel::TIM2 as TIM2_IRQ, Priority};
-use embassy_stm32::peripherals::TIM2;
-use embedded_io_async::{Read, Write};
-use embassy_stm32::time::Hertz;
-use embassy_time::{Timer, Duration, Instant};
-use embassy_futures::yield_now;
-use embassy_futures::select::{select, Either};
-use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
-use embassy_sync::pipe::Pipe;
-use embassy_sync::signal::Signal;
+use embassy_time::Instant;
+use embassy_executor::task;
+use embassy_stm32::dma::Request;
+use embassy_stm32::gpio::{Input, Output, Level, Pull, Speed};
+use dma_gpio::software_uart::{
+    dma_timer::{init_tim6_for_uart, init_tim7_for_uart},
+    gpio_dma_uart_rx::rx_dma_task,
+    debug::dump_tim6_regs,
+};
+use dma_gpio::config::{BAUD, RX_OVERSAMPLE, TX_OVERSAMPLE};
+use dma_gpio::config::{TX_RING_BYTES, RX_RING_BYTES};
+use dma_gpio::software_uart::gpio_dma_uart_tx::tx_dma_task;
 use static_cell::StaticCell;
+use embassy_futures::yield_now;
+use dma_gpio::hw_uart_pc::usart1;
+use dma_gpio::hw_uart_pc::driver::uart_task;
+use embassy_stm32::usart::{BufferedUart, Config, BufferedInterruptHandler};
+use embassy_stm32::peripherals;
+use embassy_stm32::bind_interrupts;
+use dma_gpio::config::{PIPE_HW_TX, PIPE_HW_RX, PIPE_SW_TX, PIPE_SW_RX};
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
 use {defmt_rtt as _, panic_probe as _};
-use async_uart::safety::{preflight_and_suggest_yield_period, RX_PIPE_CAP, TX_PIPE_CAP};

-static UART_TX: Pipe<CriticalSectionRawMutex, TX_PIPE_CAP> = Pipe::new();
-static UART_RX: Pipe<CriticalSectionRawMutex, RX_PIPE_CAP> = Pipe::new();
-static TIM2_TICK: Signal<CriticalSectionRawMutex, ()> = Signal::new();
+bind_interrupts!(struct Irqs {
+    USART1 => BufferedInterruptHandler<peripherals::USART1>;
+});

-bind_interrupts!(
-    struct Irqs {
-        USART1 => BufferedInterruptHandler<peripherals::USART1>;
-    }
-);
-
-#[embassy_executor::task]
-async fn uart_task(mut uart: BufferedUart<'static>) {
-    let mut rx_byte = [0u8; 1];
-    let mut tx_buf = [0u8; 64];
-    loop {
-        // Wait for either RX or TX events.
-        let rx_fut = uart.read(&mut rx_byte);
-        let tx_fut = async {
-            // Until there's outgoing data in TX pipe
-            let n = UART_TX.read(&mut tx_buf).await;
-            n
-        };
-        match select(rx_fut, tx_fut).await {
-            // Incoming data from UART hardware
-            Either::First(res) => {
-                if let Ok(_) = res {
-                    // Forward to RX pipe
-                    let _ = UART_RX.write(&rx_byte).await;
-                    let _ = UART_TX.try_write(&rx_byte);
-                }
-            }
-            // Outgoing data waiting in TX pipe
-            Either::Second(n) => {
-                unwrap!(uart.write(&tx_buf[..n]).await);
-            }
-        }
-    }
-}
+// Software uart
+pub const TIM6_UP_REQ: Request = 4;
+static SW_TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
+static SW_RX_RING: StaticCell<[u8; RX_RING_BYTES]> = StaticCell::new();

 #[embassy_executor::main]
 async fn main(spawner: Spawner) {
-    info!("tititititi");
+    info!("boot");
    let p = embassy_stm32::init(Default::default());
+    info!("init m8");
+
+    // HARDWARE UART to the PC
+    let mut cfg = Config::default();
+    cfg.baudrate = BAUD;
    static TX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
    static RX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
-    let tx_buf = TX_BUF.init([0; 256]);
-    let rx_buf = RX_BUF.init([0; 256]);
-    let mut cfg = Config::default();
-    cfg.baudrate = 230_400;
-
-    // Call preflight and get the computed yield period
-    let yield_period = preflight_and_suggest_yield_period(cfg.baudrate);
-
-    let usart = BufferedUart::new(
+    let uart = BufferedUart::new(
        p.USART1,
-        p.PA10, // RX
-        p.PA9,  // TX
-        tx_buf,
-        rx_buf,
+        p.PA10, // RX pin
+        p.PA9,  // TX pin
+        TX_BUF.init([0; 256]),
+        RX_BUF.init([0; 256]),
        Irqs,
        cfg,
    ).unwrap();
-    info!("starting uart task");
-    spawner.spawn(uart_task(usart)).unwrap();
+    let yield_period = usart1::setup_and_spawn(BAUD);
+    spawner.spawn(uart_task(uart, &PIPE_HW_TX, &PIPE_HW_RX).unwrap());
+    // END OF HARDWARE UART to the PC

-    let mut transfer: u32 = 16;
-    let mut rx_buf = [0u8; 64];
-    let mut last_yield = Instant::now();
-
-    // Software UART bits init
-    let mut tx = Output::new(p.PA2, Level::Low, Speed::Low);
+    // SOFTWARE UART 
    let _rx = Input::new(p.PA3, Pull::Up);
+    let _tx = Output::new(p.PA2, Level::High, Speed::VeryHigh);
+    init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE);
+    init_tim7_for_uart(p.TIM7, BAUD, RX_OVERSAMPLE);
+    dump_tim6_regs();

-    let tim = HardwareTimer::new(p.TIM2);
+    // Safe one-time init from StaticCell
+    let sw_rx_ring: &mut [u8; RX_RING_BYTES] = SW_RX_RING.init([0; RX_RING_BYTES]);
+    let sw_tx_ring: &mut [u32; TX_RING_BYTES] = SW_TX_RING.init([0; TX_RING_BYTES]);
+    spawner.spawn(rx_dma_task(p.GPDMA1_CH1, sw_rx_ring, &PIPE_SW_RX).unwrap());

-    // Configure for 230_400 Hz
-    tim.set_frequency(Hertz(cfg.baudrate*transfer));
-    tim.enable_update_interrupt(true);
-    tim.start();
+    // Create and start the TX DMA ring in main.
+    let bsrr_ptr = embassy_stm32::pac::GPIOA.bsrr().as_ptr() as *mut u32;
+    // let odr_ptr = embassy_stm32::pac::GPIOA.odr().as_ptr() as *mut u32; // NEEDS DECODE CHANGE
+    spawner.spawn(tx_dma_task(p.GPDMA1_CH0, bsrr_ptr, sw_tx_ring, &PIPE_SW_TX).unwrap());
+    // EDN OF SOFTWARE UART 
+
+
+    // BRIDGE
+    spawner.spawn(bridge_hw_to_sw(&PIPE_HW_RX, &PIPE_SW_TX).unwrap());
+    spawner.spawn(bridge_sw_to_hw(&PIPE_SW_RX, &PIPE_HW_TX).unwrap());
+    // END OF BRIDGE
+    
+    let mut last_yield = Instant::now();
+    let mut buf = [0u8; 32];

-    tx.set_high();
    loop {
+        info!("tick start");
+        // Timer::after(Duration::from_millis(100)).await;
+        // info!("tick end");

-        TIM2_TICK.wait().await;
-        tx.set_low();
-        TIM2_TICK.wait().await;
+        let n1 = PIPE_HW_RX.read(&mut buf).await;
+        if n1 > 0 {
+            info!("PC received: {:a}", &buf[..n1]);
+            let _ = PIPE_SW_TX.write(&buf[..n1]).await;
+            info!("SW UART TX sent echo: {:a}", &buf[..n1]);
+        }
+        yield_now().await;

-        Timer::after(Duration::from_millis(1000)).await;
-        // Poll RX pipe for new data (non-blocking)
-        if let Ok(n) = UART_RX.try_read(&mut rx_buf) {
-            if n > 0 {
-                if let Ok(s) = core::str::from_utf8(&rx_buf[..n]) {
-                    info!("RX got: {}", s);
-                } else {
-                    info!("RX got (non‑utf8): {:?}", &rx_buf[..n]);
-                }
-            }
+        let n2 = PIPE_SW_RX.read(&mut buf).await;
+        if n2 > 0 {
+            info!("SW UART RX received: {:a}", &buf[..n2]);
        }

-        // Guaranteed to yield before ISR RX buffer can overflow
        if Instant::now().duration_since(last_yield) >= yield_period {
            yield_now().await;
            last_yield = Instant::now();
-            // info!("Yield mf {}", counter);
        }
-        // Timer::after(Duration::from_micros(1)).await;
-        // Timer::after(Duration::from_secs(5)).await;
+
    }
 }

-#[embassy_stm32::interrupt]
-fn TIM2() {
-    use embassy_stm32::timer::CoreInstance;
-
-    // Access TIM2 core registers directly.
-    let regs = unsafe {
-        embassy_stm32::pac::timer::TimCore::from_ptr(
-            <peripherals::TIM2 as CoreInstance>::regs(),
-        )
-    };
-
-    // Clear update flag to avoid retriggering.
-    let sr = regs.sr().read();
-    if sr.uif() {
-        regs.sr().modify(|r| r.set_uif(false));
-
-        // Signal the waiting task that a tick occurred.
-        TIM2_TICK.signal(());
+#[task]
+pub async fn bridge_hw_to_sw(
+    hw_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+    sw_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut buf = [0u8; 64];
+    loop {
+        let n = hw_rx.read(&mut buf).await;
+        if n > 0 {
+            let _ = sw_tx.write(&buf[..n]).await;
+        }
+    }
+}
+
+#[task]
+pub async fn bridge_sw_to_hw(
+    sw_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+    hw_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut buf = [0u8; 64];
+    loop {
+        let n = sw_rx.read(&mut buf).await;
+        if n > 0 {
+            let _ = hw_tx.write(&buf[..n]).await;
+        }
    }
 }
--- a/semestralka_1/src/config.rs
+++ b/semestralka_1/src/config.rs
@@ -0,0 +1,29 @@
+// src/config.rs
+use crate::software_uart::uart_emulation::{Parity, StopBits, UartConfig};
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+
+pub const BAUD: u32 = 9_600;
+pub const TX_PIN_BIT: u8 = 2; // PA2
+pub const RX_PIN_BIT: u8 = 3; // PA3
+pub const TX_OVERSAMPLE: u16 = 1;
+pub const RX_OVERSAMPLE: u16 = 16;
+
+pub const RX_RING_BYTES: usize = 4096;
+pub const TX_RING_BYTES: usize = 4096;
+
+pub const PIPE_HW_TX_SIZE: usize = 1024;
+pub const PIPE_HW_RX_SIZE: usize = 1024;
+pub const PIPE_SW_TX_SIZE: usize = 1024;
+pub const PIPE_SW_RX_SIZE: usize = 1024;
+
+pub static PIPE_HW_TX: Pipe<CriticalSectionRawMutex, PIPE_HW_TX_SIZE> = Pipe::new();
+pub static PIPE_HW_RX: Pipe<CriticalSectionRawMutex, PIPE_HW_RX_SIZE> = Pipe::new();
+pub static PIPE_SW_TX: Pipe<CriticalSectionRawMutex, PIPE_SW_TX_SIZE> = Pipe::new();
+pub static PIPE_SW_RX: Pipe<CriticalSectionRawMutex, PIPE_SW_RX_SIZE> = Pipe::new();
+
+pub const UART_CFG: UartConfig = UartConfig {
+    data_bits: 8,
+    parity: Parity::None,
+    stop_bits: StopBits::One,
+};
--- a/semestralka_1/src/hw_uart_pc/driver.rs
+++ b/semestralka_1/src/hw_uart_pc/driver.rs
@@ -0,0 +1,39 @@
+// src/hw_uart_pc/driver.rs
+use defmt::unwrap;
+use embassy_futures::select::{select, Either};
+use embassy_stm32::usart::BufferedUart;
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+use embedded_io_async::{Read, Write};
+use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
+
+#[embassy_executor::task]
+pub async fn uart_task(
+    mut uart: BufferedUart<'static>,
+    tx_pipe: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
+    rx_pipe: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
+) {
+    let mut rx_byte = [0u8; 1];
+    let mut tx_buf = [0u8; 64];
+
+    loop {
+        let rx_fut = uart.read(&mut rx_byte);
+        let tx_fut = async {
+            let n = tx_pipe.read(&mut tx_buf).await;
+            n
+        };
+
+        match select(rx_fut, tx_fut).await {
+            // Incoming data from UART hardware
+            Either::First(res) => {
+                if let Ok(_) = res {
+                    let _ = rx_pipe.write(&rx_byte).await;
+                }
+            }
+            // Outgoing data waiting in TX pipe
+            Either::Second(n) => {
+                unwrap!(uart.write(&tx_buf[..n]).await);
+            }
+        }
+    }
+}
--- a/semestralka_1/src/hw_uart_pc/mod.rs
+++ b/semestralka_1/src/hw_uart_pc/mod.rs
@@ -0,0 +1,4 @@
+// src/uart/mod.rs
+pub mod driver;
+pub mod usart1;
+pub mod safety;
--- a/semestralka_1/src/hw_uart_pc/safety.rs
+++ b/semestralka_1/src/hw_uart_pc/safety.rs
--- a/semestralka_1/src/hw_uart_pc/usart1.rs
+++ b/semestralka_1/src/hw_uart_pc/usart1.rs
@@ -0,0 +1,12 @@
+// src/uart/usart1.rs
+use defmt::info;
+use embassy_time::Duration;
+
+use crate::hw_uart_pc::safety::preflight_and_suggest_yield_period;
+
+pub fn setup_and_spawn(baudrate: u32,) -> Duration {
+    let yield_period: Duration = preflight_and_suggest_yield_period(baudrate);
+    info!("HW USART1 safe");
+
+    yield_period
+}
--- a/semestralka_1/src/lib.rs
+++ b/semestralka_1/src/lib.rs
@@ -1,3 +1,5 @@
 #![no_std]
-pub mod safety;
-// pub mod software_uart;
+
+pub mod software_uart;
+pub mod config;
+pub mod hw_uart_pc;
--- a/semestralka_1/src/software_uart/debug.rs
+++ b/semestralka_1/src/software_uart/debug.rs
@@ -0,0 +1,43 @@
+// src/software_uart/debug.rs
+use defmt::info;
+
+pub fn dump_tim6_regs() {
+    use embassy_stm32::pac::timer::TimBasic;
+    let tim = unsafe { TimBasic::from_ptr(0x4000_1000usize as _) };
+    let sr = tim.sr().read();
+    let dier = tim.dier().read();
+    let cr1 = tim.cr1().read();
+    let arr = tim.arr().read().arr();
+    let psc = tim.psc().read();
+    info!(
+        "TIM6: CR1.CEN={} DIER.UDE={} SR.UIF={} PSC={} ARR={}",
+        cr1.cen(),
+        dier.ude(),
+        sr.uif(),
+        psc,
+        arr
+    );
+}
+
+pub fn dump_dma_ch0_regs() {
+    use embassy_stm32::pac::gpdma::Gpdma;
+    let dma = unsafe { Gpdma::from_ptr(0x4002_0000usize as _) };
+    let ch = dma.ch(0);
+    let cr = ch.cr().read();
+    let tr1 = ch.tr1().read();
+    let tr2 = ch.tr2().read();
+    let br1 = ch.br1().read();
+    info!(
+        "GPDMA1_CH0: EN={} PRIO={} SDW={} DDW={} SINC={} DINC={} REQSEL={} SWREQ={} DREQ={} BNDT={}",
+        cr.en(),
+        cr.prio(),
+        tr1.sdw(),
+        tr1.ddw(),
+        tr1.sinc(),
+        tr1.dinc(),
+        tr2.reqsel(),
+        tr2.swreq(),
+        tr2.dreq(),
+        br1.bndt()
+    );
+}
--- a/semestralka_1/src/software_uart/dma_timer.rs
+++ b/semestralka_1/src/software_uart/dma_timer.rs
@@ -0,0 +1,58 @@
+// src/dma_timer.rs
+
+use embassy_stm32::{
+    peripherals::{TIM6, TIM7},
+    rcc,
+    timer::low_level::Timer,
+    Peri,
+};
+use core::mem;
+use embassy_stm32::timer::BasicInstance;
+use embassy_stm32::pac::timer::vals::Urs;
+
+/// Initializes TIM6 to tick at `baud * oversample` frequency.
+/// Each TIM6 update event triggers one DMA beat.
+pub fn init_tim6_for_uart<'d>(tim6: Peri<'d, TIM6>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM6>();
+    let ll = Timer::new(tim6);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+/// Initializes TIM7 to tick at `baud * oversample` frequency.
+/// Each TIM7 update event triggers one DMA beat.
+pub fn init_tim7_for_uart<'d>(tim7: Peri<'d, TIM7>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM7>();
+    let ll = Timer::new(tim7);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+// Shared internal helper — identical CR1/ARR setup
+fn configure_basic_timer<T: BasicInstance>(ll: &Timer<'_, T>, baud: u32, oversample: u16) {
+    let f_timer = rcc::frequency::<T>().0;
+    let target = baud.saturating_mul(oversample.max(1) as u32).max(1);
+
+    // Compute ARR (prescaler = 0)
+    let mut arr = (f_timer / target).saturating_sub(1) as u16;
+    if arr == 0 { arr = 1; }
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_cen(false);
+        w.set_opm(false);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+
+    ll.regs_basic().psc().write_value(0u16);
+    ll.regs_basic().arr().write(|w| w.set_arr(arr));
+    ll.regs_basic().dier().modify(|w| w.set_ude(true));
+    ll.regs_basic().egr().write(|w| w.set_ug(true));
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_opm(false);
+        w.set_cen(true);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+}
--- a/semestralka_1/src/software_uart/gpio_dma_uart_rx.rs
+++ b/semestralka_1/src/software_uart/gpio_dma_uart_rx.rs
@@ -0,0 +1,61 @@
+// src/software_uart/runtime.rs
+use embassy_executor::task;
+use embassy_stm32::{
+    dma::Request,
+    peripherals::GPDMA1_CH1,
+    Peri,
+};
+use crate::config::RX_PIN_BIT;
+use embassy_stm32::dma::{
+    ReadableRingBuffer,
+    TransferOptions,
+};
+use crate::config::{RX_OVERSAMPLE, UART_CFG};
+use crate::software_uart::decode_uart_samples;
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use embassy_futures::yield_now;
+use defmt::info;
+
+// datasheet tabulka 137
+pub const TIM7_UP_REQ: Request = 5;
+
+/// RX DMA task: reads GPIO samples paced by TIM7 and fills PIPE_RX
+#[task]
+pub async fn rx_dma_task(
+    ch: Peri<'static, GPDMA1_CH1>,
+    ring: &'static mut [u8],
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let gpioa_idr = embassy_stm32::pac::GPIOA.idr().as_ptr() as *mut u8;
+
+    let mut opts = TransferOptions::default();
+    opts.half_transfer_ir = true;
+    opts.complete_transfer_ir = true;
+
+    // SAFETY: ring is exclusive to this task
+    let mut rx = unsafe { ReadableRingBuffer::new(ch, TIM7_UP_REQ, gpioa_idr, ring, opts) };
+    rx.start();
+
+    let mut raw_chunk = [0u8; 256];
+    let mut levels = [0u8; 256];
+    loop {
+        info!("rx_dma_task waiting for DMA data...");
+        let _ = rx.read_exact(&mut raw_chunk).await;
+
+        for (i, b) in raw_chunk.iter().enumerate() {
+            levels[i] = ((*b >> RX_PIN_BIT) & 1) as u8;
+        }
+
+        let decoded = decode_uart_samples(&levels, RX_OVERSAMPLE, &UART_CFG);
+        if !decoded.is_empty() {
+            info!("SW RX raw samples (first 32): {:a}", &levels[..32]);
+            info!(
+                "SW RX decoded {} bytes: {:a}",
+                decoded.len(),
+                decoded.as_slice()
+            );
+        }
+        pipe_rx.write(&decoded).await;
+        yield_now().await;
+    }
+}
--- a/semestralka_1/src/software_uart/gpio_dma_uart_tx.rs
+++ b/semestralka_1/src/software_uart/gpio_dma_uart_tx.rs
@@ -0,0 +1,84 @@
+// src/software_uart/gpio_dma_uart_tx.rs
+use embassy_executor::task;
+use embassy_stm32::{
+    dma::{Request, TransferOptions, WritableRingBuffer},
+    peripherals::GPDMA1_CH0,
+    Peri,
+};
+use embassy_futures::yield_now;
+use defmt::info;
+
+use embassy_sync::pipe::Pipe;
+use crate::config::{TX_PIN_BIT, UART_CFG};
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use crate::software_uart::uart_emulation::encode_uart_byte_cfg;
+
+pub const TIM6_UP_REQ: Request = 4;
+
+pub async fn encode_uart_frames<'a>(
+    pin_bit: u8,
+    bytes: &[u8],
+    out_buf: &'a mut [u32],
+) -> usize {
+    let mut offset = 0;
+    for &b in bytes {
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(pin_bit, b, &UART_CFG, &mut frame);
+
+        if offset + used <= out_buf.len() {
+            out_buf[offset..offset + used].copy_from_slice(&frame[..used]);
+            offset += used;
+        } else {
+            break;
+        }
+
+        // cooperative async yield
+        yield_now().await;
+    }
+    offset
+}
+
+/// TX DMA task: encodes UART frames and sends them via DMA at TIM6 rate
+#[task]
+pub async fn tx_dma_task(
+    ch: Peri<'static, GPDMA1_CH0>,
+    register: *mut u32, // Either odr or bsrr
+    tx_ring_mem: &'static mut [u32],
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut tx_opts = TransferOptions::default();
+    tx_opts.half_transfer_ir = true;
+    tx_opts.complete_transfer_ir = true;
+
+    // SAFETY: tx_ring is exclusive to this task
+    let mut tx_ring = unsafe {
+        WritableRingBuffer::new(
+            ch,
+            TIM6_UP_REQ,
+            register,
+            tx_ring_mem,
+            tx_opts,
+        )
+    };
+
+    tx_ring.start();
+    info!("TX DMA ring started");
+
+    let mut frame_buf = [0u32; 4096];
+    let mut rx_buf = [0u8; 256];
+
+    loop {
+        let n = pipe_rx.read(&mut rx_buf).await;
+        if n == 0 {
+            yield_now().await;
+            continue;
+        }
+
+        let used = encode_uart_frames(TX_PIN_BIT, &rx_buf[..n], &mut frame_buf).await;
+        if used > 0 {
+            let _ = tx_ring.write_exact(&frame_buf[..used]).await;
+        }
+        info!("tx_dma_task wrote {} words", used);
+        yield_now().await;
+    }
+}
--- a/semestralka_1/src/software_uart/mod.rs
+++ b/semestralka_1/src/software_uart/mod.rs
@@ -1,4 +1,13 @@
 // src/software_uart/mod.rs

-pub mod suart;
-pub use suart::*;
+pub mod gpio_dma_uart_tx;
+pub mod gpio_dma_uart_rx;
+pub mod dma_timer;
+pub mod uart_emulation;
+pub mod debug;
+
+pub use gpio_dma_uart_tx::*;
+pub use gpio_dma_uart_rx::*;
+pub use dma_timer::*;
+pub use uart_emulation::*;
+pub use debug::*;
--- a/semestralka_1/src/software_uart/suart.rs
+++ b/semestralka_1/src/software_uart/suart.rs
@@ -1,19 +0,0 @@
-// src/software_uart/suart.rs
-
-use embassy_stm32::peripherals::{PA2, PA3};
-use embassy_stm32::gpio::{Input, Output, Pull, Speed, Level};
-use embassy_stm32::Peripherals;
-use embassy_time::Timer;
-
-pub async fn suart_test(mut tx_pin: PA2, rx_pin: PA3) {
-    let mut tx = Output::new(tx_pin.into(), Level::Low, Speed::Low);
-    let _rx = Input::new(rx_pin.into(), Pull::Up);
-
-    loop {
-        tx.set_high();
-        Timer::after_millis(500).await;
-
-        tx.set_low();
-        Timer::after_millis(500).await;
-    }
-}
--- a/semestralka_1/src/software_uart/uart_emulation.rs
+++ b/semestralka_1/src/software_uart/uart_emulation.rs
@@ -0,0 +1,151 @@
+// src/software_uart/uart_emulation.rs
+use heapless::Vec;
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Parity {
+    None,
+    Even,
+    Odd,
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum StopBits {
+    One,
+    Two,
+}
+
+#[derive(Clone, Copy, Debug)]
+pub struct UartConfig {
+    pub data_bits: u8,
+    pub parity: Parity,
+    pub stop_bits: StopBits,
+}
+
+impl Default for UartConfig {
+    fn default() -> Self {
+        Self {
+            data_bits: 8,
+            parity: Parity::None,
+            stop_bits: StopBits::One,
+        }
+    }
+}
+
+/// Encodes one byte into a sequence of GPIO BSRR words
+pub fn encode_uart_byte_cfg(
+    pin_bit: u8,
+    data: u8,
+    cfg: &UartConfig,
+    out: &mut [u32; 12],
+) -> usize {
+    // GPIOx_BSRR register str. 636 kap. 13.4.7
+    let set_high = |bit: u8| -> u32 { 1u32 << bit };
+    // let set_low = |bit: u8| -> u32 { 0 }; // ODR
+    let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) }; // BSRR
+
+    let mut idx = 0usize;
+
+    // START bit (LOW)
+    out[idx] = set_low(pin_bit);
+    idx += 1;
+
+    // Data bits, LSB-first
+    let nbits = cfg.data_bits.clamp(5, 8);
+    for i in 0..nbits {
+        let one = ((data >> i) & 1) != 0;
+        out[idx] = if one { set_high(pin_bit) } else { set_low(pin_bit) };
+        idx += 1;
+    }
+
+    // Parity
+    match cfg.parity {
+        Parity::None => {}
+        Parity::Even | Parity::Odd => {
+            let mask: u8 = if nbits == 8 { 0xFF } else { (1u16 << nbits) as u8 - 1 };
+            let ones = (data & mask).count_ones() & 1;
+            let par_bit_is_one = match cfg.parity {
+                Parity::Even => ones == 1,
+                Parity::Odd => ones == 0,
+                _ => false,
+            };
+            out[idx] = if par_bit_is_one {
+                set_high(pin_bit)
+            } else {
+                set_low(pin_bit)
+            };
+            idx += 1;
+        }
+    }
+
+    // STOP bits (HIGH)
+    let stop_ticks = match cfg.stop_bits {
+        StopBits::One => 1usize,
+        StopBits::Two => 2usize,
+    };
+    for _ in 0..stop_ticks {
+        out[idx] = set_high(pin_bit);
+        idx += 1;
+    }
+
+    idx
+}
+
+/// Decode an oversampled stream of logic levels into UART bytes.
+pub fn decode_uart_samples(
+    samples: &[u8],
+    oversample: u16,
+    cfg: &UartConfig,
+) -> heapless::Vec<u8, 256> {
+
+    let mut out = Vec::<u8, 256>::new();
+    let mut idx = 0usize;
+    let nbits = cfg.data_bits as usize;
+
+    while idx + (oversample as usize * (nbits + 3)) < samples.len() {
+        // Wait for start bit (falling edge: high -> low)
+        if samples[idx] != 0 && samples[idx + 1] == 0 {
+            // Align to middle of start bit
+            idx += (oversample / 2) as usize;
+
+            // Sanity check start bit really low
+            if samples.get(idx).copied().unwrap_or(1) != 0 {
+                idx += 1;
+                continue;
+            }
+
+            // Sample data bits
+            let mut data: u8 = 0;
+            for bit in 0..nbits {
+                idx += oversample as usize;
+                let bit_val = samples
+                    .get(idx)
+                    .map(|&b| if b != 0 { 1u8 } else { 0u8 })
+                    .unwrap_or(1);
+                data |= bit_val << bit;
+            }
+
+            // Parity: skip / verify
+            match cfg.parity {
+                Parity::None => {}
+                Parity::Even | Parity::Odd => {
+                    idx += oversample as usize;
+                    // You can optionally add parity check here if needed
+                }
+            }
+
+            // Move past stop bits
+            let stop_skip = match cfg.stop_bits {
+                StopBits::One => oversample as usize,
+                StopBits::Two => (oversample * 2) as usize,
+            };
+            idx += stop_skip;
+
+            // Push decoded byte
+            let _ = out.push(data);
+        } else {
+            idx += 1;
+        }
+    }
+
+    out
+}
--- a/semestralka_1/tests/integration.rs
+++ b/semestralka_1/tests/integration.rs
@@ -1,14 +0,0 @@
-#![no_std]
-#![no_main]
-
-// See https://crates.io/crates/defmt-test/0.3.0 for more documentation (e.g. about the 'state'
-// feature)
-#[defmt_test::tests]
-mod tests {
-    use defmt::assert;
-
-    #[test]
-    fn it_works() {
-        assert!(true)
-    }
-}
--- a/semestralka_1/tests/uart_emulation.rs
+++ b/semestralka_1/tests/uart_emulation.rs
@@ -0,0 +1,41 @@
+#![no_std]
+#![no_main]
+
+use dma_gpio as _;
+use panic_probe as _;
+use defmt_rtt as _;
+
+#[defmt_test::tests]
+mod tests {
+    use defmt::assert_eq;
+    use dma_gpio::software_uart::uart_emulation::{
+        encode_uart_byte_cfg, UartConfig, Parity, StopBits
+    };
+
+    const TX_PIN_BIT: u8 = 2;
+
+    #[test]
+    fn test_encode_8n1() {
+        let cfg = UartConfig::default();
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(TX_PIN_BIT, 0x55, &cfg, &mut frame);
+        
+        assert_eq!(used, 10);
+        assert_eq!(frame[0], 1u32 << 18); // Start LOW
+        assert_eq!(frame[9], 1u32 << 2);  // Stop HIGH
+    }
+
+    #[test]
+    fn test_encode_parity() {
+        let cfg = UartConfig {
+            data_bits: 8,
+            parity: Parity::Even,
+            stop_bits: StopBits::One,
+        };
+        
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(TX_PIN_BIT, 0x00, &cfg, &mut frame);
+        
+        assert_eq!(used, 11);
+    }
+}
--- a/semestralka_1_2hwuart_internal/.cargo/config.toml
+++ b/semestralka_1_2hwuart_internal/.cargo/config.toml
@@ -0,0 +1,15 @@
+[build]
+target = "thumbv8m.main-none-eabihf"
+
+[target.thumbv8m.main-none-eabihf]
+runner = "probe-rs run --chip STM32U575ZITxQ"
+
+rustflags = [
+  "-C", "linker=rust-lld",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "link-arg=-Tdefmt.x",
+  "-C", "link-arg=--nmagic",
+]
+
+[package.metadata.cargo-flash]
+chip = "STM32U575ZIT"
--- a/semestralka_1_2hwuart_internal/.gitignore
+++ b/semestralka_1_2hwuart_internal/.gitignore
@@ -0,0 +1 @@
+/target
--- a/semestralka_1_2hwuart_internal/Cargo.lock
+++ b/semestralka_1_2hwuart_internal/Cargo.lock
--- a/semestralka_1_2hwuart_internal/Cargo.toml
+++ b/semestralka_1_2hwuart_internal/Cargo.toml
@@ -0,0 +1,45 @@
+[package]
+authors = ["Priec <filippriec@gmail.com>"]
+name = "dma_gpio"
+edition = "2024"
+version = "0.1.0"
+
+
+[dependencies]
+cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.5"
+panic-halt = "1.0.0"
+embassy-executor = { path = "/home/priec/programs/embassy/embassy-executor", features = ["arch-cortex-m", "executor-thread"] }
+embassy-futures = { path = "/home/priec/programs/embassy/embassy-futures" }
+embassy-sync = { path = "/home/priec/programs/embassy/embassy-sync" }
+embassy-time = { path = "/home/priec/programs/embassy/embassy-time", features = ["tick-hz-32_768"] }
+embassy-hal-internal = { path = "/home/priec/programs/embassy/embassy-hal-internal" }
+embassy-usb = { path = "/home/priec/programs/embassy/embassy-usb" }
+embassy-stm32 = { path = "/home/priec/programs/embassy/embassy-stm32", features = ["unstable-pac", "stm32u575zi", "time-driver-tim2", "memory-x", "defmt"] }
+
+embedded-hal = "1.0.0"
+embedded-graphics = "0.8.1"
+heapless = { version = "0.9.1", default-features = false }
+micromath = "2.1.0"
+tinybmp = "0.6.0"
+panic-probe = { version = "1.0.0", features = ["defmt"] }
+defmt-rtt = "1.1.0"
+defmt = "1.0.1"
+static_cell = "2.1.1"
+embedded-io = "0.6.1"
+embedded-io-async = "0.6.1"
+
+[dev-dependencies]
+defmt-test = "0.4.0"
+
+[[test]]
+name = "uart_emulation"
+harness = false
+
+[lib]
+test = false
+
+[[bin]]
+name = "main"
+path = "src/bin/main.rs"
+test = false
--- a/semestralka_1_2hwuart_internal/LICENSE-APACHE
+++ b/semestralka_1_2hwuart_internal/LICENSE-APACHE
@@ -0,0 +1,201 @@
+                              Apache License
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+
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--- a/semestralka_1_2hwuart_internal/LICENSE-MIT
+++ b/semestralka_1_2hwuart_internal/LICENSE-MIT
@@ -0,0 +1,23 @@
+Permission is hereby granted, free of charge, to any
+person obtaining a copy of this software and associated
+documentation files (the "Software"), to deal in the
+Software without restriction, including without
+limitation the rights to use, copy, modify, merge,
+publish, distribute, sublicense, and/or sell copies of
+the Software, and to permit persons to whom the Software
+is furnished to do so, subject to the following
+conditions:
+
+The above copyright notice and this permission notice
+shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
+ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
+IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.
--- a/semestralka_1_2hwuart_internal/Makefile
+++ b/semestralka_1_2hwuart_internal/Makefile
@@ -0,0 +1,23 @@
+TARGET = thumbv8m.main-none-eabihf
+CHIP = STM32U575ZI
+BIN = stm32u5-blinky
+MODE ?= release
+TARGET_DIR = target/$(TARGET)/$(MODE)
+ELF = $(TARGET_DIR)/$(BIN)
+PROBE = probe-rs
+
+.PHONY: all build flash clean empty
+
+all: build
+
+build:
+	cargo build --$(MODE)
+
+flash: build
+	$(PROBE) run --chip $(CHIP) $(ELF)
+
+empty:
+	$(PROBE) erase --chip $(CHIP)
+
+clean:
+	cargo clean
--- a/semestralka_1_2hwuart_internal/README.md
+++ b/semestralka_1_2hwuart_internal/README.md
@@ -0,0 +1,232 @@
+# `app-template`
+
+> Quickly set up a [`probe-rs`] + [`defmt`] + [`flip-link`] embedded project
+
+[`probe-rs`]: https://crates.io/crates/probe-rs
+[`defmt`]: https://github.com/knurling-rs/defmt
+[`flip-link`]: https://github.com/knurling-rs/flip-link
+
+## Dependencies
+
+### 1. `flip-link`:
+
+```bash
+cargo install flip-link
+```
+
+### 2. `probe-rs`:
+
+Install probe-rs by following the instructions at <https://probe.rs/docs/getting-started/installation/>.
+
+### 3. [`cargo-generate`]:
+
+```bash
+cargo install cargo-generate
+```
+
+[`cargo-generate`]: https://crates.io/crates/cargo-generate
+
+> *Note:* You can also just clone this repository instead of using `cargo-generate`, but this involves additional manual adjustments.
+
+## Setup
+
+### 1. Initialize the project template
+
+```bash
+cargo generate \
+    --git https://github.com/knurling-rs/app-template \
+    --branch main \
+    --name my-app
+```
+
+If you look into your new `my-app` folder, you'll find that there are a few `TODO`s in the files marking the properties you need to set.
+
+Let's walk through them together now.
+
+### 2. Set `probe-rs` chip
+
+Pick a chip from ` probe-rs chip list` and enter it into `.cargo/config.toml`.
+
+If, for example, you have a nRF52840 Development Kit as used in one of [our exercises], replace `{{chip}}` with `nRF52840_xxAA`.
+
+[our workshops]: https://rust-exercises.ferrous-systems.com
+
+```diff
+ # .cargo/config.toml
+-runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format=oneline"]
+runner = ["probe-rs", "run", "--chip", "nRF52840_xxAA", "--log-format=oneline"]
+```
+
+### 3. Adjust the compilation target
+
+In `.cargo/config.toml`, pick the right compilation target for your board.
+
+```diff
+ # .cargo/config.toml
+ [build]
+-target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
+-# target = "thumbv7m-none-eabi"    # Cortex-M3
+-# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
+-# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
+target = "thumbv7em-none-eabihf" # Cortex-M4F (with FPU)
+```
+
+Add the target with `rustup`.
+
+```bash
+rustup target add thumbv7em-none-eabihf
+```
+
+### 4. Add a HAL as a dependency
+
+In `Cargo.toml`, list the Hardware Abstraction Layer (HAL) for your board as a dependency.
+
+For the nRF52840 you'll want to use the [`nrf52840-hal`].
+
+[`nrf52840-hal`]: https://crates.io/crates/nrf52840-hal
+
+```diff
+ # Cargo.toml
+ [dependencies]
+-# some-hal = "1.2.3"
+nrf52840-hal = "0.14.0"
+```
+
+⚠️ Note for RP2040 users ⚠️
+
+You will need to not just specify the `rp-hal` HAL, but a BSP (board support crate) which includes a second stage bootloader. Please find a list of available BSPs [here](https://github.com/rp-rs/rp-hal-boards#packages).
+
+### 5. Import your HAL
+
+Now that you have selected a HAL, fix the HAL import in `src/lib.rs`
+
+```diff
+ // my-app/src/lib.rs
+-// use some_hal as _; // memory layout
+use nrf52840_hal as _; // memory layout
+```
+
+### (6. Get a linker script)
+
+Some HAL crates require that you manually copy over a file called `memory.x` from the HAL to the root of your project. For nrf52840-hal, this is done automatically so no action is needed. For other HAL crates, see their documentation on where to find an example file.
+
+The `memory.x` file should look something like:
+
+```text
+MEMORY
+{
+  FLASH : ORIGIN = 0x00000000, LENGTH = 1024K
+  RAM   : ORIGIN = 0x20000000, LENGTH = 256K
+}
+```
+
+The `memory.x` file is included in the `cortex-m-rt` linker script `link.x`, and so `link.x` is the one you should tell `rustc` to use (see the `.cargo/config.toml` file where we do that).
+
+### 7. Run!
+
+You are now all set to `cargo-run` your first `defmt`-powered application!
+There are some examples in the `src/bin` directory.
+
+Start by `cargo run`-ning `my-app/src/bin/hello.rs`:
+
+```console
+$ # `rb` is an alias for `run --bin`
+$ cargo rb hello
+    Finished `dev` profile [optimized + debuginfo] target(s) in 0.01s
+     Running `probe-rs run --chip nrf52840_xxaa --log-format=oneline target/thumbv6m-none-eabi/debug/hello`
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.79 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+Hello, world!
+
+$ echo $?
+0
+```
+
+If you're running out of memory (`flip-link` bails with an overflow error), you can decrease the size of the device memory buffer by setting the `DEFMT_RTT_BUFFER_SIZE` environment variable. The default value is 1024 bytes, and powers of two should be used for optimal performance:
+
+```console
+$ DEFMT_RTT_BUFFER_SIZE=64 cargo rb hello
+```
+
+### (8. Set `rust-analyzer.linkedProjects`)
+
+If you are using [rust-analyzer] with VS Code for IDE-like features you can add following configuration to your `.vscode/settings.json` to make it work transparently across workspaces. Find the details of this option in the [RA docs].
+
+```json
+{
+    "rust-analyzer.linkedProjects": [
+        "Cargo.toml",
+        "firmware/Cargo.toml",
+    ]
+}
+```
+
+[RA docs]: https://rust-analyzer.github.io/manual.html#configuration
+[rust-analyzer]: https://rust-analyzer.github.io/
+
+## Running tests
+
+The template comes configured for running unit tests and integration tests on the target.
+
+Unit tests reside in the library crate and can test private API; the initial set of unit tests are in `src/lib.rs`.
+`cargo test --lib` will run those unit tests.
+
+```console
+$ cargo test --lib
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.15s
+     Running unittests src/lib.rs (target/thumbv6m-none-eabi/debug/deps/example-2b0d0e25d141bf57)
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.99 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.33 KiB/s (took 1s)                                                                                                                        Finished in 1.10s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Integration tests reside in the `tests` directory; the initial set of integration tests are in `tests/integration.rs`.
+`cargo test --test integration` will run those integration tests.
+Note that the argument of the `--test` flag must match the name of the test file in the `tests` directory.
+
+```console
+$ cargo test --test integration
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.10s
+     Running tests/integration.rs (target/thumbv6m-none-eabi/debug/deps/integration-aaaff41151f6a722)
+      Erasing ✔ 100% [####################]   8.00 KiB @  16.03 KiB/s (took 0s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Note that to add a new test file to the `tests` directory you also need to add a new `[[test]]` section to `Cargo.toml`.
+
+To run all the tests via `cargo test` the tests need to be explicitly disabled for all the existing binary targets.
+See `Cargo.toml` for details on how to do this.
+
+## Support
+
+`app-template` is part of the [Knurling] project, [Ferrous Systems]' effort at
+improving tooling used to develop for embedded systems.
+
+If you think that our work is useful, consider sponsoring it via [GitHub
+Sponsors].
+
+## License
+
+Licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+  http://www.apache.org/licenses/LICENSE-2.0)
+
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+### Contribution
+
+Unless you explicitly state otherwise, any contribution intentionally submitted
+for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
+licensed as above, without any additional terms or conditions.
+
+[Knurling]: https://knurling.ferrous-systems.com
+[Ferrous Systems]: https://ferrous-systems.com/
+[GitHub Sponsors]: https://github.com/sponsors/knurling-rs
--- a/semestralka_1_2hwuart_internal/src/bin/main.rs
+++ b/semestralka_1_2hwuart_internal/src/bin/main.rs
@@ -0,0 +1,161 @@
+// src/bin/main.rs
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_time::Instant;
+use embassy_stm32::dma::Request;
+use embassy_stm32::gpio::{Input, Output, Level, Pull, Speed};
+use dma_gpio::software_uart::{
+    dma_timer::{init_tim6_for_uart, init_tim7_for_uart},
+    gpio_dma_uart_rx::rx_dma_task,
+    debug::dump_tim6_regs,
+};
+use dma_gpio::config::{BAUD, RX_OVERSAMPLE, TX_OVERSAMPLE};
+use dma_gpio::config::{TX_RING_BYTES, RX_RING_BYTES};
+use dma_gpio::software_uart::gpio_dma_uart_tx::tx_dma_task;
+use static_cell::StaticCell;
+use embassy_futures::yield_now;
+use dma_gpio::hw_uart_pc::usart1;
+use dma_gpio::hw_uart_pc::driver::uart_task;
+use embassy_stm32::usart::{BufferedUart, Config, BufferedInterruptHandler};
+use embassy_stm32::peripherals;
+use embassy_stm32::bind_interrupts;
+use dma_gpio::config::{PIPE_HW_TX, PIPE_HW_RX, PIPE_SW_TX, PIPE_SW_RX};
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use dma_gpio::hw_uart_internal::usart2;
+use dma_gpio::hw_uart_internal::driver::uart_task as uart_task_internal;
+use dma_gpio::config::{PIPE_INT_TX, PIPE_INT_RX};
+use embassy_time::{Duration, Timer};
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    USART1 => BufferedInterruptHandler<peripherals::USART1>;
+});
+bind_interrupts!(struct Irqs2 {
+    USART2 => BufferedInterruptHandler<peripherals::USART2>;
+});
+
+// Software uart
+pub const TIM6_UP_REQ: Request = 4;
+static SW_TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
+static SW_RX_RING: StaticCell<[u8; RX_RING_BYTES]> = StaticCell::new();
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    info!("boot");
+    let p = embassy_stm32::init(Default::default());
+    info!("init m8");
+
+
+    // HARDWARE UART to the PC
+    let mut cfg = Config::default();
+    cfg.baudrate = BAUD;
+    static TX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
+    static RX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
+    let uart = BufferedUart::new(
+        p.USART1,
+        p.PA10, // RX pin
+        p.PA9,  // TX pin
+        TX_BUF.init([0; 256]),
+        RX_BUF.init([0; 256]),
+        Irqs,
+        cfg,
+    ).unwrap();
+    let yield_period = usart1::setup_and_spawn(BAUD);
+    spawner.spawn(uart_task(uart, &PIPE_HW_TX, &PIPE_HW_RX).unwrap());
+    // END OF HARDWARE UART to the PC
+
+    // INTERNAL HARDWARE UART (USART2)
+    let mut cfg2 = Config::default();
+    cfg2.baudrate = BAUD;
+    static TX_BUF2: StaticCell<[u8; 256]> = StaticCell::new();
+    static RX_BUF2: StaticCell<[u8; 256]> = StaticCell::new();
+
+    let uart2 = BufferedUart::new(
+        p.USART2,
+        p.PA3, // RX
+        p.PA2, // TX
+        TX_BUF2.init([0; 256]),
+        RX_BUF2.init([0; 256]),
+        Irqs2,
+        cfg2,
+    ).unwrap();
+
+    let _ = usart2::setup_and_spawn(BAUD);
+    spawner.spawn(uart_task_internal(uart2, &PIPE_INT_TX, &PIPE_INT_RX).unwrap());
+    info!("USART2 ready");
+    // END OF INTERNAL HARDWARE UART (USART2)
+    
+    // USART1 <-> USART2 bridge
+    spawner.spawn(bridge_usart1_rx_to_usart2_tx(&PIPE_HW_RX, &PIPE_INT_TX).unwrap());
+    spawner.spawn(bridge_usart2_rx_to_usart1_tx(&PIPE_INT_RX, &PIPE_HW_TX).unwrap());
+    info!("USART1 <-> USART2 bridge active");
+    // END OF USART1 <-> USART2 bridge 
+
+    // SOFTWARE UART 
+    // let _rx = Input::new(p.PD6, Pull::Up);
+    let rx_pin = Input::new(p.PD6, Pull::Up);
+    // Configure TX as output (PB0)
+
+    let mut tx_pin = Output::new(p.PB0, Level::High, Speed::VeryHigh);
+    init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE);
+    init_tim7_for_uart(p.TIM7, BAUD, RX_OVERSAMPLE);
+    dump_tim6_regs();
+    // EDN OF SOFTWARE UART
+
+
+    let mut last_yield = Instant::now();
+    let mut buf = [0u8; 32];
+
+    let mut last_state: u8 = 0;
+    loop {
+        // info!("tick start");
+        // Timer::after(Duration::from_millis(100)).await;
+        // info!("tick end");
+
+        // let n1 = PIPE_HW_RX.read(&mut buf).await;
+        // if n1 > 0 {
+        //     info!("PC received: {:a}", &buf[..n1]);
+        //     let _ = PIPE_SW_TX.write(&buf[..n1]).await;
+        //     info!("SW UART TX sent echo: {:a}", &buf[..n1]);
+        // }
+        // yield_now().await;
+
+
+        yield_now().await;
+    }
+}
+
+#[embassy_executor::task]
+pub async fn bridge_usart1_rx_to_usart2_tx(
+    usart1_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+    usart2_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut buf = [0u8; 64];
+    loop {
+        let n = usart1_rx.read(&mut buf).await;
+        if n > 0 {
+            let _ = usart2_tx.write(&buf[..n]).await;
+            info!("bridge: USART1 -> USART2 sent {} bytes", n);
+        }
+        yield_now().await;
+    }
+}
+
+#[embassy_executor::task]
+pub async fn bridge_usart2_rx_to_usart1_tx(
+    usart2_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+    usart1_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut buf = [0u8; 64];
+    loop {
+        let n = usart2_rx.read(&mut buf).await;
+        if n > 0 {
+            let _ = usart1_tx.write(&buf[..n]).await;
+            // info!("bridge: USART2 -> USART1 sent {} bytes", n);
+        }
+        yield_now().await;
+    }
+}
--- a/semestralka_1_2hwuart_internal/src/config.rs
+++ b/semestralka_1_2hwuart_internal/src/config.rs
@@ -0,0 +1,35 @@
+// src/config.rs
+use crate::software_uart::uart_emulation::{Parity, StopBits, UartConfig};
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+
+pub const BAUD: u32 = 9_600;
+// pub const TX_PIN_BIT: u8 = 2; // PA2
+// pub const RX_PIN_BIT: u8 = 3; // PA3
+pub const TX_PIN_BIT: u8 = 0; // PB2
+pub const RX_PIN_BIT: u8 = 3; // PC3
+pub const TX_OVERSAMPLE: u16 = 1;
+pub const RX_OVERSAMPLE: u16 = 16;
+
+pub const RX_RING_BYTES: usize = 4096;
+pub const TX_RING_BYTES: usize = 4096;
+
+pub const PIPE_HW_TX_SIZE: usize = 1024;
+pub const PIPE_HW_RX_SIZE: usize = 1024;
+pub const PIPE_SW_TX_SIZE: usize = 1024;
+pub const PIPE_SW_RX_SIZE: usize = 1024;
+pub const PIPE_INT_TX_SIZE: usize = 1024;
+pub const PIPE_INT_RX_SIZE: usize = 1024;
+
+pub static PIPE_HW_TX: Pipe<CriticalSectionRawMutex, PIPE_HW_TX_SIZE> = Pipe::new();
+pub static PIPE_HW_RX: Pipe<CriticalSectionRawMutex, PIPE_HW_RX_SIZE> = Pipe::new();
+pub static PIPE_SW_TX: Pipe<CriticalSectionRawMutex, PIPE_SW_TX_SIZE> = Pipe::new();
+pub static PIPE_SW_RX: Pipe<CriticalSectionRawMutex, PIPE_SW_RX_SIZE> = Pipe::new();
+pub static PIPE_INT_TX: Pipe<CriticalSectionRawMutex, PIPE_INT_TX_SIZE> = Pipe::new();
+pub static PIPE_INT_RX: Pipe<CriticalSectionRawMutex, PIPE_INT_RX_SIZE> = Pipe::new();
+
+pub const UART_CFG: UartConfig = UartConfig {
+    data_bits: 8,
+    parity: Parity::None,
+    stop_bits: StopBits::One,
+};
--- a/semestralka_1_2hwuart_internal/src/hw_uart_internal/driver.rs
+++ b/semestralka_1_2hwuart_internal/src/hw_uart_internal/driver.rs
@@ -0,0 +1,41 @@
+// src/hw_uart_internal/driver.rs
+use defmt::unwrap;
+use embassy_futures::select::{select, Either};
+use embassy_stm32::usart::BufferedUart;
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+use embedded_io_async::{Read, Write};
+use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
+use embassy_futures::yield_now;
+
+#[embassy_executor::task]
+pub async fn uart_task(
+    mut uart: BufferedUart<'static>,
+    tx_pipe: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
+    rx_pipe: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
+) {
+    let mut rx_byte = [0u8; 1];
+    let mut tx_buf = [0u8; 64];
+
+    loop {
+        let rx_fut = uart.read(&mut rx_byte);
+        let tx_fut = async {
+            let n = tx_pipe.read(&mut tx_buf).await;
+            n
+        };
+
+        match select(rx_fut, tx_fut).await {
+            // Incoming data from UART hardware
+            Either::First(res) => {
+                if let Ok(_) = res {
+                    let _ = rx_pipe.write(&rx_byte).await;
+                }
+            }
+            // Outgoing data waiting in TX pipe
+            Either::Second(n) => {
+                unwrap!(uart.write(&tx_buf[..n]).await);
+            }
+        }
+        yield_now().await;
+    }
+}
--- a/semestralka_1_2hwuart_internal/src/hw_uart_internal/mod.rs
+++ b/semestralka_1_2hwuart_internal/src/hw_uart_internal/mod.rs
@@ -0,0 +1,4 @@
+// src/hw_uart_internal/mod.rs
+
+pub mod driver;
+pub mod usart2;
--- a/semestralka_1_2hwuart_internal/src/hw_uart_internal/usart2.rs
+++ b/semestralka_1_2hwuart_internal/src/hw_uart_internal/usart2.rs
@@ -0,0 +1,11 @@
+// src/hw_uart_internal/usart2.rs
+use defmt::info;
+use embassy_time::Duration;
+
+use crate::hw_uart_pc::safety::preflight_and_suggest_yield_period;
+
+pub fn setup_and_spawn(baudrate: u32) -> Duration {
+    let yield_period = preflight_and_suggest_yield_period(baudrate);
+    info!("HW USART2 safe");
+    yield_period
+}
--- a/semestralka_1_2hwuart_internal/src/hw_uart_pc/driver.rs
+++ b/semestralka_1_2hwuart_internal/src/hw_uart_pc/driver.rs
@@ -0,0 +1,41 @@
+// src/hw_uart_pc/driver.rs
+use defmt::unwrap;
+use embassy_futures::select::{select, Either};
+use embassy_stm32::usart::BufferedUart;
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+use embedded_io_async::{Read, Write};
+use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
+use embassy_futures::yield_now;
+
+#[embassy_executor::task]
+pub async fn uart_task(
+    mut uart: BufferedUart<'static>,
+    tx_pipe: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
+    rx_pipe: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
+) {
+    let mut rx_byte = [0u8; 1];
+    let mut tx_buf = [0u8; 64];
+
+    loop {
+        let rx_fut = uart.read(&mut rx_byte);
+        let tx_fut = async {
+            let n = tx_pipe.read(&mut tx_buf).await;
+            n
+        };
+
+        match select(rx_fut, tx_fut).await {
+            // Incoming data from UART hardware
+            Either::First(res) => {
+                if let Ok(_) = res {
+                    let _ = rx_pipe.write(&rx_byte).await;
+                }
+            }
+            // Outgoing data waiting in TX pipe
+            Either::Second(n) => {
+                unwrap!(uart.write(&tx_buf[..n]).await);
+            }
+        }
+        yield_now().await;
+    }
+}
--- a/semestralka_1_2hwuart_internal/src/hw_uart_pc/mod.rs
+++ b/semestralka_1_2hwuart_internal/src/hw_uart_pc/mod.rs
@@ -0,0 +1,4 @@
+// src/hw_uart_pc/mod.rs
+pub mod driver;
+pub mod usart1;
+pub mod safety;
--- a/semestralka_1_2hwuart_internal/src/hw_uart_pc/safety.rs
+++ b/semestralka_1_2hwuart_internal/src/hw_uart_pc/safety.rs
@@ -0,0 +1,57 @@
+// src/safety.rs
+use defmt::info;
+use embassy_time::Duration;
+
+// ISR RX ring capacity = RX_BUF len
+const ISR_RX_BUF_CAP: usize = 256;
+// Yield 1/2 the time it takes to fill ISR RX ring.
+const YIELD_MARGIN_NUM: u32 = 1;
+const YIELD_MARGIN_DEN: u32 = 2;
+// Ensure RX_PIPE_CAP can hold this.
+const WORST_MAIN_LATENCY_MS: u32 = 20;
+
+pub const TX_PIPE_CAP: usize = 1024;
+pub const RX_PIPE_CAP: usize = 1024;
+
+
+
+/// Perform safety checks and compute yield timing to avoid buffer overflow.
+///
+/// # Panics
+/// Panics if pipe capacities are too small for the configured baud.
+pub fn preflight_and_suggest_yield_period(baud: u32) -> Duration {
+    // Approx bytes per second for 8N1 (10 bits per byte on the wire)
+    let bytes_per_sec = (baud / 10).max(1);
+
+    // Time until ISR RX ring fills, in microseconds.
+    let t_fill_us = (ISR_RX_BUF_CAP as u64) * 1_000_000u64 / (bytes_per_sec as u64);
+
+    // Choose a yield period as a fraction of t_fill.
+    let yield_us = (t_fill_us as u64)
+        .saturating_mul(YIELD_MARGIN_NUM as u64)
+        / (YIELD_MARGIN_DEN as u64);
+
+    // Verify RX pipe can absorb a worst-case app latency so uart_task
+    // can always forward without dropping when it runs.
+    let required_rx_pipe = (bytes_per_sec as u64) * (WORST_MAIN_LATENCY_MS as u64) / 1000;
+
+    if (RX_PIPE_CAP as u64) < required_rx_pipe {
+        core::panic!(
+            "RX pipe too small: have {}B, need >= {}B for {}ms at {} bps",
+            RX_PIPE_CAP, required_rx_pipe, WORST_MAIN_LATENCY_MS, baud
+        );
+    }
+
+    info!(
+        "Preflight: baud={}, rx_isr={}B, rx_pipe={}B, bytes/s={}, t_fill_us={}, yield_us={}",
+        baud,
+        ISR_RX_BUF_CAP,
+        RX_PIPE_CAP,
+        bytes_per_sec,
+        t_fill_us,
+        yield_us
+    );
+
+    // Never choose zero.
+    Duration::from_micros(yield_us.max(1) as u64)
+}
--- a/semestralka_1_2hwuart_internal/src/hw_uart_pc/usart1.rs
+++ b/semestralka_1_2hwuart_internal/src/hw_uart_pc/usart1.rs
@@ -0,0 +1,12 @@
+// src/uart/usart1.rs
+use defmt::info;
+use embassy_time::Duration;
+
+use crate::hw_uart_pc::safety::preflight_and_suggest_yield_period;
+
+pub fn setup_and_spawn(baudrate: u32,) -> Duration {
+    let yield_period: Duration = preflight_and_suggest_yield_period(baudrate);
+    info!("HW USART1 safe");
+
+    yield_period
+}
--- a/semestralka_1_2hwuart_internal/src/lib.rs
+++ b/semestralka_1_2hwuart_internal/src/lib.rs
@@ -0,0 +1,6 @@
+#![no_std]
+
+pub mod software_uart;
+pub mod config;
+pub mod hw_uart_pc;
+pub mod hw_uart_internal;
--- a/semestralka_1_2hwuart_internal/src/software_uart/debug.rs
+++ b/semestralka_1_2hwuart_internal/src/software_uart/debug.rs
@@ -0,0 +1,43 @@
+// src/software_uart/debug.rs
+use defmt::info;
+
+pub fn dump_tim6_regs() {
+    use embassy_stm32::pac::timer::TimBasic;
+    let tim = unsafe { TimBasic::from_ptr(0x4000_1000usize as _) };
+    let sr = tim.sr().read();
+    let dier = tim.dier().read();
+    let cr1 = tim.cr1().read();
+    let arr = tim.arr().read().arr();
+    let psc = tim.psc().read();
+    info!(
+        "TIM6: CR1.CEN={} DIER.UDE={} SR.UIF={} PSC={} ARR={}",
+        cr1.cen(),
+        dier.ude(),
+        sr.uif(),
+        psc,
+        arr
+    );
+}
+
+pub fn dump_dma_ch0_regs() {
+    use embassy_stm32::pac::gpdma::Gpdma;
+    let dma = unsafe { Gpdma::from_ptr(0x4002_0000usize as _) };
+    let ch = dma.ch(0);
+    let cr = ch.cr().read();
+    let tr1 = ch.tr1().read();
+    let tr2 = ch.tr2().read();
+    let br1 = ch.br1().read();
+    info!(
+        "GPDMA1_CH0: EN={} PRIO={} SDW={} DDW={} SINC={} DINC={} REQSEL={} SWREQ={} DREQ={} BNDT={}",
+        cr.en(),
+        cr.prio(),
+        tr1.sdw(),
+        tr1.ddw(),
+        tr1.sinc(),
+        tr1.dinc(),
+        tr2.reqsel(),
+        tr2.swreq(),
+        tr2.dreq(),
+        br1.bndt()
+    );
+}
--- a/semestralka_1_2hwuart_internal/src/software_uart/dma_timer.rs
+++ b/semestralka_1_2hwuart_internal/src/software_uart/dma_timer.rs
@@ -0,0 +1,58 @@
+// src/dma_timer.rs
+
+use embassy_stm32::{
+    peripherals::{TIM6, TIM7},
+    rcc,
+    timer::low_level::Timer,
+    Peri,
+};
+use core::mem;
+use embassy_stm32::timer::BasicInstance;
+use embassy_stm32::pac::timer::vals::Urs;
+
+/// Initializes TIM6 to tick at `baud * oversample` frequency.
+/// Each TIM6 update event triggers one DMA beat.
+pub fn init_tim6_for_uart<'d>(tim6: Peri<'d, TIM6>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM6>();
+    let ll = Timer::new(tim6);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+/// Initializes TIM7 to tick at `baud * oversample` frequency.
+/// Each TIM7 update event triggers one DMA beat.
+pub fn init_tim7_for_uart<'d>(tim7: Peri<'d, TIM7>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM7>();
+    let ll = Timer::new(tim7);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+// Shared internal helper — identical CR1/ARR setup
+fn configure_basic_timer<T: BasicInstance>(ll: &Timer<'_, T>, baud: u32, oversample: u16) {
+    let f_timer = rcc::frequency::<T>().0;
+    let target = baud.saturating_mul(oversample.max(1) as u32).max(1);
+
+    // Compute ARR (prescaler = 0)
+    let mut arr = (f_timer / target).saturating_sub(1) as u16;
+    if arr == 0 { arr = 1; }
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_cen(false);
+        w.set_opm(false);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+
+    ll.regs_basic().psc().write_value(0u16);
+    ll.regs_basic().arr().write(|w| w.set_arr(arr));
+    ll.regs_basic().dier().modify(|w| w.set_ude(true));
+    ll.regs_basic().egr().write(|w| w.set_ug(true));
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_opm(false);
+        w.set_cen(true);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+}
--- a/semestralka_1_2hwuart_internal/src/software_uart/gpio_dma_uart_rx.rs
+++ b/semestralka_1_2hwuart_internal/src/software_uart/gpio_dma_uart_rx.rs
@@ -0,0 +1,80 @@
+// src/software_uart/runtime.rs
+use embassy_executor::task;
+use embassy_stm32::{
+    dma::Request,
+    peripherals::GPDMA1_CH1,
+    Peri,
+};
+use crate::config::RX_PIN_BIT;
+use embassy_stm32::dma::{
+    ReadableRingBuffer,
+    TransferOptions,
+};
+use crate::config::{RX_OVERSAMPLE, UART_CFG};
+use crate::software_uart::decode_uart_samples;
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use embassy_futures::yield_now;
+use defmt::info;
+
+// datasheet tabulka 137
+pub const TIM7_UP_REQ: Request = 5;
+
+/// RX DMA task: reads GPIO samples paced by TIM7 and fills PIPE_RX
+#[task]
+pub async fn rx_dma_task(
+    ch: Peri<'static, GPDMA1_CH1>,
+    register: *mut u8,
+    ring: &'static mut [u8],
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut opts = TransferOptions::default();
+    opts.half_transfer_ir = true;
+    opts.complete_transfer_ir = true;
+
+    // SAFETY: ring is exclusive to this task
+    let mut rx = unsafe { ReadableRingBuffer::new(ch, TIM7_UP_REQ, register, ring, opts) };
+    rx.start();
+
+    let mut raw_chunk = [0u8; 256];
+    let mut levels = [0u8; 256];
+    let mut last_bytes: [u8; 16] = [0; 16];   // remember previous 16 samples
+    let mut last_value: u8 = 0;              // remember previous single IDR sample (optional)
+
+    loop {
+        let _ = rx.read_exact(&mut raw_chunk).await;
+
+        // If nothing has changed (all bytes same as previous), skip logging
+        if raw_chunk[..16] == last_bytes[..] {
+            continue;
+        }
+
+        // Save for next comparison
+        last_bytes.copy_from_slice(&raw_chunk[..16]);
+        let current_avg = raw_chunk[0];
+
+        // Optionally only if single sample changed
+        if current_avg != last_value {
+            last_value = current_avg;
+
+            info!(
+                "DMA change detected: IDR[0..16]={=[u8]:02X} bit{}={}",
+                &raw_chunk[..16],
+                RX_PIN_BIT,
+                (current_avg >> RX_PIN_BIT) & 1
+            );
+        }
+
+        // Extract logic levels as before
+        for (i, b) in raw_chunk.iter().enumerate() {
+            levels[i] = ((*b >> RX_PIN_BIT) & 1) as u8;
+        }
+
+        let decoded = decode_uart_samples(&levels, RX_OVERSAMPLE, &UART_CFG);
+        if !decoded.is_empty() {
+            info!("SW RX decoded {:a}", decoded.as_slice());
+            pipe_rx.write(&decoded).await;
+        }
+
+        yield_now().await;
+    }
+}
--- a/semestralka_1_2hwuart_internal/src/software_uart/gpio_dma_uart_tx.rs
+++ b/semestralka_1_2hwuart_internal/src/software_uart/gpio_dma_uart_tx.rs
@@ -0,0 +1,84 @@
+// src/software_uart/gpio_dma_uart_tx.rs
+use embassy_executor::task;
+use embassy_stm32::{
+    dma::{Request, TransferOptions, WritableRingBuffer},
+    peripherals::GPDMA1_CH0,
+    Peri,
+};
+use embassy_futures::yield_now;
+use defmt::info;
+
+use embassy_sync::pipe::Pipe;
+use crate::config::{TX_PIN_BIT, UART_CFG};
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use crate::software_uart::uart_emulation::encode_uart_byte_cfg;
+
+pub const TIM6_UP_REQ: Request = 4;
+
+pub async fn encode_uart_frames<'a>(
+    pin_bit: u8,
+    bytes: &[u8],
+    out_buf: &'a mut [u32],
+) -> usize {
+    let mut offset = 0;
+    for &b in bytes {
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(pin_bit, b, &UART_CFG, &mut frame);
+
+        if offset + used <= out_buf.len() {
+            out_buf[offset..offset + used].copy_from_slice(&frame[..used]);
+            offset += used;
+        } else {
+            break;
+        }
+
+        // cooperative async yield
+        yield_now().await;
+    }
+    offset
+}
+
+/// TX DMA task: encodes UART frames and sends them via DMA at TIM6 rate
+#[task]
+pub async fn tx_dma_task(
+    ch: Peri<'static, GPDMA1_CH0>,
+    register: *mut u32, // Either odr or bsrr
+    tx_ring_mem: &'static mut [u32],
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut tx_opts = TransferOptions::default();
+    tx_opts.half_transfer_ir = true;
+    tx_opts.complete_transfer_ir = true;
+
+    // SAFETY: tx_ring is exclusive to this task
+    let mut tx_ring = unsafe {
+        WritableRingBuffer::new(
+            ch,
+            TIM6_UP_REQ,
+            register,
+            tx_ring_mem,
+            tx_opts,
+        )
+    };
+
+    tx_ring.start();
+    info!("TX DMA ring started");
+
+    let mut frame_buf = [0u32; 4096];
+    let mut rx_buf = [0u8; 256];
+
+    loop {
+        let n = pipe_rx.read(&mut rx_buf).await;
+        if n == 0 {
+            yield_now().await;
+            continue;
+        }
+
+        let used = encode_uart_frames(TX_PIN_BIT, &rx_buf[..n], &mut frame_buf).await;
+        if used > 0 {
+            let _ = tx_ring.write_exact(&frame_buf[..used]).await;
+        }
+        info!("tx_dma_task wrote {} words", used);
+        yield_now().await;
+    }
+}
--- a/semestralka_1_2hwuart_internal/src/software_uart/mod.rs
+++ b/semestralka_1_2hwuart_internal/src/software_uart/mod.rs
@@ -0,0 +1,13 @@
+// src/software_uart/mod.rs
+
+pub mod gpio_dma_uart_tx;
+pub mod gpio_dma_uart_rx;
+pub mod dma_timer;
+pub mod uart_emulation;
+pub mod debug;
+
+pub use gpio_dma_uart_tx::*;
+pub use gpio_dma_uart_rx::*;
+pub use dma_timer::*;
+pub use uart_emulation::*;
+pub use debug::*;
--- a/semestralka_1_2hwuart_internal/src/software_uart/uart_emulation.rs
+++ b/semestralka_1_2hwuart_internal/src/software_uart/uart_emulation.rs
@@ -0,0 +1,151 @@
+// src/software_uart/uart_emulation.rs
+use heapless::Vec;
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Parity {
+    None,
+    Even,
+    Odd,
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum StopBits {
+    One,
+    Two,
+}
+
+#[derive(Clone, Copy, Debug)]
+pub struct UartConfig {
+    pub data_bits: u8,
+    pub parity: Parity,
+    pub stop_bits: StopBits,
+}
+
+impl Default for UartConfig {
+    fn default() -> Self {
+        Self {
+            data_bits: 8,
+            parity: Parity::None,
+            stop_bits: StopBits::One,
+        }
+    }
+}
+
+/// Encodes one byte into a sequence of GPIO BSRR words
+pub fn encode_uart_byte_cfg(
+    pin_bit: u8,
+    data: u8,
+    cfg: &UartConfig,
+    out: &mut [u32; 12],
+) -> usize {
+    // GPIOx_BSRR register str. 636 kap. 13.4.7
+    let set_high = |bit: u8| -> u32 { 1u32 << bit };
+    // let set_low = |bit: u8| -> u32 { 0 }; // ODR
+    let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) }; // BSRR
+
+    let mut idx = 0usize;
+
+    // START bit (LOW)
+    out[idx] = set_low(pin_bit);
+    idx += 1;
+
+    // Data bits, LSB-first
+    let nbits = cfg.data_bits.clamp(5, 8);
+    for i in 0..nbits {
+        let one = ((data >> i) & 1) != 0;
+        out[idx] = if one { set_high(pin_bit) } else { set_low(pin_bit) };
+        idx += 1;
+    }
+
+    // Parity
+    match cfg.parity {
+        Parity::None => {}
+        Parity::Even | Parity::Odd => {
+            let mask: u8 = if nbits == 8 { 0xFF } else { (1u16 << nbits) as u8 - 1 };
+            let ones = (data & mask).count_ones() & 1;
+            let par_bit_is_one = match cfg.parity {
+                Parity::Even => ones == 1,
+                Parity::Odd => ones == 0,
+                _ => false,
+            };
+            out[idx] = if par_bit_is_one {
+                set_high(pin_bit)
+            } else {
+                set_low(pin_bit)
+            };
+            idx += 1;
+        }
+    }
+
+    // STOP bits (HIGH)
+    let stop_ticks = match cfg.stop_bits {
+        StopBits::One => 1usize,
+        StopBits::Two => 2usize,
+    };
+    for _ in 0..stop_ticks {
+        out[idx] = set_high(pin_bit);
+        idx += 1;
+    }
+
+    idx
+}
+
+/// Decode an oversampled stream of logic levels into UART bytes.
+pub fn decode_uart_samples(
+    samples: &[u8],
+    oversample: u16,
+    cfg: &UartConfig,
+) -> heapless::Vec<u8, 256> {
+
+    let mut out = Vec::<u8, 256>::new();
+    let mut idx = 0usize;
+    let nbits = cfg.data_bits as usize;
+
+    while idx + (oversample as usize * (nbits + 3)) < samples.len() {
+        // Wait for start bit (falling edge: high -> low)
+        if samples[idx] != 0 && samples[idx + 1] == 0 {
+            // Align to middle of start bit
+            idx += (oversample / 2) as usize;
+
+            // Sanity check start bit really low
+            if samples.get(idx).copied().unwrap_or(1) != 0 {
+                idx += 1;
+                continue;
+            }
+
+            // Sample data bits
+            let mut data: u8 = 0;
+            for bit in 0..nbits {
+                idx += oversample as usize;
+                let bit_val = samples
+                    .get(idx)
+                    .map(|&b| if b != 0 { 1u8 } else { 0u8 })
+                    .unwrap_or(1);
+                data |= bit_val << bit;
+            }
+
+            // Parity: skip / verify
+            match cfg.parity {
+                Parity::None => {}
+                Parity::Even | Parity::Odd => {
+                    idx += oversample as usize;
+                    // You can optionally add parity check here if needed
+                }
+            }
+
+            // Move past stop bits
+            let stop_skip = match cfg.stop_bits {
+                StopBits::One => oversample as usize,
+                StopBits::Two => (oversample * 2) as usize,
+            };
+            idx += stop_skip;
+
+            // Push decoded byte
+            let _ = out.push(data);
+        } else {
+            idx += 1;
+        }
+    }
+
+    out
+}
--- a/semestralka_1_2hwuart_internal/tests/uart_emulation.rs
+++ b/semestralka_1_2hwuart_internal/tests/uart_emulation.rs
@@ -0,0 +1,41 @@
+#![no_std]
+#![no_main]
+
+use dma_gpio as _;
+use panic_probe as _;
+use defmt_rtt as _;
+
+#[defmt_test::tests]
+mod tests {
+    use defmt::assert_eq;
+    use dma_gpio::software_uart::uart_emulation::{
+        encode_uart_byte_cfg, UartConfig, Parity, StopBits
+    };
+
+    const TX_PIN_BIT: u8 = 2;
+
+    #[test]
+    fn test_encode_8n1() {
+        let cfg = UartConfig::default();
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(TX_PIN_BIT, 0x55, &cfg, &mut frame);
+        
+        assert_eq!(used, 10);
+        assert_eq!(frame[0], 1u32 << 18); // Start LOW
+        assert_eq!(frame[9], 1u32 << 2);  // Stop HIGH
+    }
+
+    #[test]
+    fn test_encode_parity() {
+        let cfg = UartConfig {
+            data_bits: 8,
+            parity: Parity::Even,
+            stop_bits: StopBits::One,
+        };
+        
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(TX_PIN_BIT, 0x00, &cfg, &mut frame);
+        
+        assert_eq!(used, 11);
+    }
+}
--- a/semestralka_1_connected/.cargo/config.toml
+++ b/semestralka_1_connected/.cargo/config.toml
@@ -0,0 +1,15 @@
+[build]
+target = "thumbv8m.main-none-eabihf"
+
+[target.thumbv8m.main-none-eabihf]
+runner = "probe-rs run --chip STM32U575ZITxQ"
+
+rustflags = [
+  "-C", "linker=rust-lld",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "link-arg=-Tdefmt.x",
+  "-C", "link-arg=--nmagic",
+]
+
+[package.metadata.cargo-flash]
+chip = "STM32U575ZIT"
--- a/semestralka_1_connected/.gitignore
+++ b/semestralka_1_connected/.gitignore
@@ -0,0 +1 @@
+/target
--- a/semestralka_1_connected/Cargo.lock
+++ b/semestralka_1_connected/Cargo.lock
--- a/semestralka_1_connected/Cargo.toml
+++ b/semestralka_1_connected/Cargo.toml
@@ -0,0 +1,49 @@
+[package]
+authors = ["Priec <filippriec@gmail.com>"]
+name = "dma_gpio"
+edition = "2024"
+version = "0.1.0"
+
+
+[dependencies]
+cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.5"
+panic-halt = "1.0.0"
+embassy-executor = { path = "/home/priec/programs/embassy/embassy-executor", features = ["arch-cortex-m", "executor-thread"] }
+embassy-futures = { path = "/home/priec/programs/embassy/embassy-futures" }
+embassy-sync = { path = "/home/priec/programs/embassy/embassy-sync" }
+embassy-time = { path = "/home/priec/programs/embassy/embassy-time", features = ["tick-hz-32_768"] }
+embassy-hal-internal = { path = "/home/priec/programs/embassy/embassy-hal-internal" }
+embassy-usb = { path = "/home/priec/programs/embassy/embassy-usb" }
+embassy-stm32 = { path = "/home/priec/programs/embassy/embassy-stm32", features = ["unstable-pac", "stm32u575zi", "time-driver-tim2", "memory-x", "defmt"] }
+
+embedded-hal = "1.0.0"
+embedded-graphics = "0.8.1"
+heapless = { version = "0.9.1", default-features = false }
+micromath = "2.1.0"
+tinybmp = "0.6.0"
+panic-probe = { version = "1.0.0", features = ["defmt"] }
+defmt-rtt = "1.1.0"
+defmt = "1.0.1"
+static_cell = "2.1.1"
+embedded-io = "0.6.1"
+embedded-io-async = "0.6.1"
+
+[dev-dependencies]
+defmt-test = "0.4.0"
+
+[[test]]
+name = "uart_emulation"
+harness = false
+
+[lib]
+test = false
+
+[[bin]]
+name = "main"
+path = "src/bin/main.rs"
+test = false
+
+[profile.dev]
+opt-level = 3
+codegen-units = 1
--- a/semestralka_1_connected/LICENSE-APACHE
+++ b/semestralka_1_connected/LICENSE-APACHE
@@ -0,0 +1,201 @@
+                              Apache License
+                        Version 2.0, January 2004
+                     http://www.apache.org/licenses/
+
+TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
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+
+APPENDIX: How to apply the Apache License to your work.
+
+   To apply the Apache License to your work, attach the following
+   boilerplate notice, with the fields enclosed by brackets "[]"
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+Copyright [yyyy] [name of copyright owner]
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+Licensed under the Apache License, Version 2.0 (the "License");
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+Unless required by applicable law or agreed to in writing, software
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--- a/semestralka_1_connected/LICENSE-MIT
+++ b/semestralka_1_connected/LICENSE-MIT
@@ -0,0 +1,23 @@
+Permission is hereby granted, free of charge, to any
+person obtaining a copy of this software and associated
+documentation files (the "Software"), to deal in the
+Software without restriction, including without
+limitation the rights to use, copy, modify, merge,
+publish, distribute, sublicense, and/or sell copies of
+the Software, and to permit persons to whom the Software
+is furnished to do so, subject to the following
+conditions:
+
+The above copyright notice and this permission notice
+shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
+ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
+IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.
--- a/semestralka_1_connected/Makefile
+++ b/semestralka_1_connected/Makefile
@@ -0,0 +1,23 @@
+TARGET = thumbv8m.main-none-eabihf
+CHIP = STM32U575ZI
+BIN = stm32u5-blinky
+MODE ?= release
+TARGET_DIR = target/$(TARGET)/$(MODE)
+ELF = $(TARGET_DIR)/$(BIN)
+PROBE = probe-rs
+
+.PHONY: all build flash clean empty
+
+all: build
+
+build:
+	cargo build --$(MODE)
+
+flash: build
+	$(PROBE) run --chip $(CHIP) $(ELF)
+
+empty:
+	$(PROBE) erase --chip $(CHIP)
+
+clean:
+	cargo clean
--- a/semestralka_1_connected/README.md
+++ b/semestralka_1_connected/README.md
@@ -0,0 +1,232 @@
+# `app-template`
+
+> Quickly set up a [`probe-rs`] + [`defmt`] + [`flip-link`] embedded project
+
+[`probe-rs`]: https://crates.io/crates/probe-rs
+[`defmt`]: https://github.com/knurling-rs/defmt
+[`flip-link`]: https://github.com/knurling-rs/flip-link
+
+## Dependencies
+
+### 1. `flip-link`:
+
+```bash
+cargo install flip-link
+```
+
+### 2. `probe-rs`:
+
+Install probe-rs by following the instructions at <https://probe.rs/docs/getting-started/installation/>.
+
+### 3. [`cargo-generate`]:
+
+```bash
+cargo install cargo-generate
+```
+
+[`cargo-generate`]: https://crates.io/crates/cargo-generate
+
+> *Note:* You can also just clone this repository instead of using `cargo-generate`, but this involves additional manual adjustments.
+
+## Setup
+
+### 1. Initialize the project template
+
+```bash
+cargo generate \
+    --git https://github.com/knurling-rs/app-template \
+    --branch main \
+    --name my-app
+```
+
+If you look into your new `my-app` folder, you'll find that there are a few `TODO`s in the files marking the properties you need to set.
+
+Let's walk through them together now.
+
+### 2. Set `probe-rs` chip
+
+Pick a chip from ` probe-rs chip list` and enter it into `.cargo/config.toml`.
+
+If, for example, you have a nRF52840 Development Kit as used in one of [our exercises], replace `{{chip}}` with `nRF52840_xxAA`.
+
+[our workshops]: https://rust-exercises.ferrous-systems.com
+
+```diff
+ # .cargo/config.toml
+-runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format=oneline"]
+runner = ["probe-rs", "run", "--chip", "nRF52840_xxAA", "--log-format=oneline"]
+```
+
+### 3. Adjust the compilation target
+
+In `.cargo/config.toml`, pick the right compilation target for your board.
+
+```diff
+ # .cargo/config.toml
+ [build]
+-target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
+-# target = "thumbv7m-none-eabi"    # Cortex-M3
+-# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
+-# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
+target = "thumbv7em-none-eabihf" # Cortex-M4F (with FPU)
+```
+
+Add the target with `rustup`.
+
+```bash
+rustup target add thumbv7em-none-eabihf
+```
+
+### 4. Add a HAL as a dependency
+
+In `Cargo.toml`, list the Hardware Abstraction Layer (HAL) for your board as a dependency.
+
+For the nRF52840 you'll want to use the [`nrf52840-hal`].
+
+[`nrf52840-hal`]: https://crates.io/crates/nrf52840-hal
+
+```diff
+ # Cargo.toml
+ [dependencies]
+-# some-hal = "1.2.3"
+nrf52840-hal = "0.14.0"
+```
+
+⚠️ Note for RP2040 users ⚠️
+
+You will need to not just specify the `rp-hal` HAL, but a BSP (board support crate) which includes a second stage bootloader. Please find a list of available BSPs [here](https://github.com/rp-rs/rp-hal-boards#packages).
+
+### 5. Import your HAL
+
+Now that you have selected a HAL, fix the HAL import in `src/lib.rs`
+
+```diff
+ // my-app/src/lib.rs
+-// use some_hal as _; // memory layout
+use nrf52840_hal as _; // memory layout
+```
+
+### (6. Get a linker script)
+
+Some HAL crates require that you manually copy over a file called `memory.x` from the HAL to the root of your project. For nrf52840-hal, this is done automatically so no action is needed. For other HAL crates, see their documentation on where to find an example file.
+
+The `memory.x` file should look something like:
+
+```text
+MEMORY
+{
+  FLASH : ORIGIN = 0x00000000, LENGTH = 1024K
+  RAM   : ORIGIN = 0x20000000, LENGTH = 256K
+}
+```
+
+The `memory.x` file is included in the `cortex-m-rt` linker script `link.x`, and so `link.x` is the one you should tell `rustc` to use (see the `.cargo/config.toml` file where we do that).
+
+### 7. Run!
+
+You are now all set to `cargo-run` your first `defmt`-powered application!
+There are some examples in the `src/bin` directory.
+
+Start by `cargo run`-ning `my-app/src/bin/hello.rs`:
+
+```console
+$ # `rb` is an alias for `run --bin`
+$ cargo rb hello
+    Finished `dev` profile [optimized + debuginfo] target(s) in 0.01s
+     Running `probe-rs run --chip nrf52840_xxaa --log-format=oneline target/thumbv6m-none-eabi/debug/hello`
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.79 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+Hello, world!
+
+$ echo $?
+0
+```
+
+If you're running out of memory (`flip-link` bails with an overflow error), you can decrease the size of the device memory buffer by setting the `DEFMT_RTT_BUFFER_SIZE` environment variable. The default value is 1024 bytes, and powers of two should be used for optimal performance:
+
+```console
+$ DEFMT_RTT_BUFFER_SIZE=64 cargo rb hello
+```
+
+### (8. Set `rust-analyzer.linkedProjects`)
+
+If you are using [rust-analyzer] with VS Code for IDE-like features you can add following configuration to your `.vscode/settings.json` to make it work transparently across workspaces. Find the details of this option in the [RA docs].
+
+```json
+{
+    "rust-analyzer.linkedProjects": [
+        "Cargo.toml",
+        "firmware/Cargo.toml",
+    ]
+}
+```
+
+[RA docs]: https://rust-analyzer.github.io/manual.html#configuration
+[rust-analyzer]: https://rust-analyzer.github.io/
+
+## Running tests
+
+The template comes configured for running unit tests and integration tests on the target.
+
+Unit tests reside in the library crate and can test private API; the initial set of unit tests are in `src/lib.rs`.
+`cargo test --lib` will run those unit tests.
+
+```console
+$ cargo test --lib
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.15s
+     Running unittests src/lib.rs (target/thumbv6m-none-eabi/debug/deps/example-2b0d0e25d141bf57)
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.99 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.33 KiB/s (took 1s)                                                                                                                        Finished in 1.10s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Integration tests reside in the `tests` directory; the initial set of integration tests are in `tests/integration.rs`.
+`cargo test --test integration` will run those integration tests.
+Note that the argument of the `--test` flag must match the name of the test file in the `tests` directory.
+
+```console
+$ cargo test --test integration
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.10s
+     Running tests/integration.rs (target/thumbv6m-none-eabi/debug/deps/integration-aaaff41151f6a722)
+      Erasing ✔ 100% [####################]   8.00 KiB @  16.03 KiB/s (took 0s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Note that to add a new test file to the `tests` directory you also need to add a new `[[test]]` section to `Cargo.toml`.
+
+To run all the tests via `cargo test` the tests need to be explicitly disabled for all the existing binary targets.
+See `Cargo.toml` for details on how to do this.
+
+## Support
+
+`app-template` is part of the [Knurling] project, [Ferrous Systems]' effort at
+improving tooling used to develop for embedded systems.
+
+If you think that our work is useful, consider sponsoring it via [GitHub
+Sponsors].
+
+## License
+
+Licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+  http://www.apache.org/licenses/LICENSE-2.0)
+
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+### Contribution
+
+Unless you explicitly state otherwise, any contribution intentionally submitted
+for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
+licensed as above, without any additional terms or conditions.
+
+[Knurling]: https://knurling.ferrous-systems.com
+[Ferrous Systems]: https://ferrous-systems.com/
+[GitHub Sponsors]: https://github.com/sponsors/knurling-rs
--- a/semestralka_1_connected/src/bin/main.rs
+++ b/semestralka_1_connected/src/bin/main.rs
@@ -0,0 +1,193 @@
+// src/bin/main.rs
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use core::cell::RefCell;
+use cortex_m::interrupt::Mutex;
+use embassy_executor::Spawner;
+use embassy_futures::yield_now;
+use embassy_sync::{
+    blocking_mutex::raw::CriticalSectionRawMutex,
+    channel::Channel,
+    pipe::Pipe,
+};
+use embassy_time::{Duration, Instant, Timer};
+use embassy_stm32::{
+    bind_interrupts,
+    dma::Request,
+    gpio::{Input, Level, Output, Pull, Speed},
+    interrupt,
+    pac,
+    peripherals,
+    rcc::{self, Pll, PllDiv, PllMul, PllPreDiv, PllSource, Sysclk},
+    usart::{BufferedInterruptHandler, BufferedUart, Config},
+    Config as CPUConfig,
+};
+use static_cell::StaticCell;
+use dma_gpio::config::{
+    BAUD, PIPE_HW_RX, PIPE_HW_TX, PIPE_INT_RX, PIPE_INT_TX, PIPE_SW_RX,
+    PIPE_SW_TX, RX_OVERSAMPLE, RX_RING_BYTES, TX_OVERSAMPLE, TX_RING_BYTES,
+    UART_CFG,
+};
+use dma_gpio::hw_uart_pc::{driver::uart_task, usart1};
+use dma_gpio::hw_uart_internal::{
+    driver::uart_task as uart_task_internal,
+    usart2,
+};
+use dma_gpio::software_uart::{
+    debug::dump_tim6_regs,
+    decode_uart_samples,
+    dma_timer::{init_tim6_for_uart, init_tim7_for_uart},
+    gpio_dma_uart_rx::rx_dma_task,
+    gpio_dma_uart_tx::tx_dma_task,
+};
+use {defmt_rtt as _, panic_probe as _};
+
+static PD6_BITS: Channel<CriticalSectionRawMutex, u8, 16384> = Channel::new();
+
+bind_interrupts!(struct Irqs {
+    USART1 => BufferedInterruptHandler<peripherals::USART1>;
+});
+bind_interrupts!(struct Irqs2 {
+    USART2 => BufferedInterruptHandler<peripherals::USART2>;
+});
+
+// Software uart
+pub const TIM6_UP_REQ: Request = 4;
+static SW_TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
+static SW_RX_RING: StaticCell<[u8; RX_RING_BYTES]> = StaticCell::new();
+static mut RX_PIN: Option<Input<'static>> = None;
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    info!("boot");
+    let mut config = CPUConfig::default();
+    config.rcc.hsi = true;
+    config.rcc.sys = Sysclk::PLL1_R;
+    config.rcc.pll1 = Some(Pll {
+        source: PllSource::HSI,
+        // 16 MHz / 1 × 20 / 2 = 160 MHz
+        prediv: PllPreDiv::DIV1,      // or 1.into()
+        mul:    PllMul::MUL20,        // or 20.into()
+        divp:   None,
+        divq:   None,
+        divr:   Some(PllDiv::DIV2),   // or Some(2.into())
+    });
+    config.enable_independent_io_supply = true;
+    config.enable_independent_analog_supply = true;
+
+    let p = embassy_stm32::init(config);
+    let f_tim7 = rcc::frequency::<embassy_stm32::peripherals::TIM7>().0;
+    info!("TIM7 clock after PLL config = {} Hz", f_tim7);
+    let f_tim6 = rcc::frequency::<embassy_stm32::peripherals::TIM6>().0;
+    info!("TIM6 clock after PLL config = {} Hz", f_tim6);
+
+    // HARDWARE UART to the PC
+    let mut cfg = Config::default();
+    cfg.baudrate = BAUD;
+    static TX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
+    static RX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
+    let uart = BufferedUart::new(
+        p.USART1,
+        p.PA10, // RX pin
+        p.PA9,  // TX pin
+        TX_BUF.init([0; 256]),
+        RX_BUF.init([0; 256]),
+        Irqs,
+        cfg,
+    ).unwrap();
+    let yield_period = usart1::setup_and_spawn(BAUD);
+    spawner.spawn(uart_task(uart, &PIPE_HW_TX, &PIPE_HW_RX).unwrap());
+    // END OF HARDWARE UART to the PC
+
+    // INTERNAL HARDWARE UART (USART2)
+    let mut cfg2 = Config::default();
+    cfg2.baudrate = BAUD;
+    static TX_BUF2: StaticCell<[u8; 256]> = StaticCell::new();
+    static RX_BUF2: StaticCell<[u8; 256]> = StaticCell::new();
+
+    let uart2 = BufferedUart::new(
+        p.USART2,
+        p.PA3, // RX
+        p.PA2, // TX
+        TX_BUF2.init([0; 256]),
+        RX_BUF2.init([0; 256]),
+        Irqs2,
+        cfg2,
+    ).unwrap();
+    let yield_period2 = usart2::setup_and_spawn(BAUD);
+    spawner.spawn(uart_task_internal(uart2, &PIPE_INT_TX, &PIPE_INT_RX).unwrap());
+    info!("USART2 ready");
+    // END OF INTERNAL HARDWARE UART (USART2)
+    
+    // USART1 <-> USART2 bridge
+    spawner.spawn(bridge_usart1_rx_to_usart2_tx(&PIPE_HW_RX, &PIPE_INT_TX).unwrap());
+    spawner.spawn(bridge_usart2_rx_to_usart1_tx(&PIPE_INT_RX, &PIPE_HW_TX).unwrap());
+    info!("USART1 <-> USART2 bridge active");
+    // END OF USART1 <-> USART2 bridge 
+
+    // SOFTWARE UART 
+    let rx_pin = Input::new(p.PD6, Pull::Up);
+    unsafe { RX_PIN = Some(rx_pin) };
+
+    // Configure TX as output (PB0)
+    let mut tx_pin = Output::new(p.PB0, Level::High, Speed::VeryHigh);
+    init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE);
+    init_tim7_for_uart(p.TIM7, BAUD, RX_OVERSAMPLE);
+
+    dump_tim6_regs();
+    let bsrr_ptr = embassy_stm32::pac::GPIOB.bsrr().as_ptr() as *mut u32; // POZOR B REGISTER
+
+    spawner.spawn(tx_dma_task(p.GPDMA1_CH0, bsrr_ptr, SW_TX_RING.init([0; TX_RING_BYTES]), &PIPE_SW_TX).unwrap());
+    // EDN OF SOFTWARE UART
+
+
+    let rx_ring = SW_RX_RING.init([0u8; RX_RING_BYTES]);
+    let gpio_idr = embassy_stm32::pac::GPIOD.idr().as_ptr() as *mut u8;
+    spawner.spawn(rx_dma_task(p.GPDMA1_CH1, gpio_idr, rx_ring, &PIPE_SW_RX).unwrap());
+    info!("SW UART RX DMA started");
+
+    // Process decoded bytes coming from PIPE_SW_RX
+    let mut buf = [0u8; 64];
+    loop {
+        let n = PIPE_SW_RX.read(&mut buf).await;
+        if n > 0 {
+            let _ = PIPE_SW_TX.write(&buf[..n]).await;
+            // info!("SW UART decoded: {:a}", &buf[..n]);
+        }
+        yield_now().await;
+    }
+}
+
+#[embassy_executor::task]
+pub async fn bridge_usart1_rx_to_usart2_tx(
+    usart1_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+    usart2_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut buf = [0u8; 64];
+    loop {
+        let n = usart1_rx.read(&mut buf).await;
+        if n > 0 {
+            let _ = usart2_tx.write(&buf[..n]).await;
+            // info!("bridge USART1 - USART2 sent:{} bytes: {}", n, &buf[..n]);
+        }
+        yield_now().await;
+    }
+}
+
+#[embassy_executor::task]
+pub async fn bridge_usart2_rx_to_usart1_tx(
+    usart2_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+    usart1_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut buf = [0u8; 64];
+    loop {
+        let n = usart2_rx.read(&mut buf).await;
+        if n > 0 {
+            let _ = usart1_tx.write(&buf[..n]).await;
+            // info!("bridge: USART2 -> USART1 sent {} bytes", n);
+        }
+        yield_now().await;
+    }
+}
--- a/semestralka_1_connected/src/config.rs
+++ b/semestralka_1_connected/src/config.rs
@@ -0,0 +1,35 @@
+// src/config.rs
+use crate::software_uart::uart_emulation::{Parity, StopBits, UartConfig};
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+
+pub const BAUD: u32 = 9_600;
+// pub const TX_PIN_BIT: u8 = 2; // PA2
+// pub const RX_PIN_BIT: u8 = 3; // PA3
+pub const TX_PIN_BIT: u8 = 0; // PB2
+pub const RX_PIN_BIT: u8 = 6; // PC3
+pub const TX_OVERSAMPLE: u16 = 1;
+pub const RX_OVERSAMPLE: u16 = 13;
+
+pub const RX_RING_BYTES: usize = 32768;
+pub const TX_RING_BYTES: usize = 4096;
+
+pub const PIPE_HW_TX_SIZE: usize = 1024;
+pub const PIPE_HW_RX_SIZE: usize = 1024;
+pub const PIPE_SW_TX_SIZE: usize = 1024;
+pub const PIPE_SW_RX_SIZE: usize = 4096;
+pub const PIPE_INT_TX_SIZE: usize = 1024;
+pub const PIPE_INT_RX_SIZE: usize = 1024;
+
+pub static PIPE_HW_TX: Pipe<CriticalSectionRawMutex, PIPE_HW_TX_SIZE> = Pipe::new();
+pub static PIPE_HW_RX: Pipe<CriticalSectionRawMutex, PIPE_HW_RX_SIZE> = Pipe::new();
+pub static PIPE_SW_TX: Pipe<CriticalSectionRawMutex, PIPE_SW_TX_SIZE> = Pipe::new();
+pub static PIPE_SW_RX: Pipe<CriticalSectionRawMutex, PIPE_SW_RX_SIZE> = Pipe::new();
+pub static PIPE_INT_TX: Pipe<CriticalSectionRawMutex, PIPE_INT_TX_SIZE> = Pipe::new();
+pub static PIPE_INT_RX: Pipe<CriticalSectionRawMutex, PIPE_INT_RX_SIZE> = Pipe::new();
+
+pub const UART_CFG: UartConfig = UartConfig {
+    data_bits: 8,
+    parity: Parity::None,
+    stop_bits: StopBits::One,
+};
--- a/semestralka_1_connected/src/hw_uart_internal/driver.rs
+++ b/semestralka_1_connected/src/hw_uart_internal/driver.rs
@@ -0,0 +1,41 @@
+// src/hw_uart_internal/driver.rs
+use defmt::unwrap;
+use embassy_futures::select::{select, Either};
+use embassy_stm32::usart::BufferedUart;
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+use embedded_io_async::{Read, Write};
+use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
+use embassy_futures::yield_now;
+
+#[embassy_executor::task]
+pub async fn uart_task(
+    mut uart: BufferedUart<'static>,
+    tx_pipe: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
+    rx_pipe: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
+) {
+    let mut rx_byte = [0u8; 1];
+    let mut tx_buf = [0u8; 64];
+
+    loop {
+        let rx_fut = uart.read(&mut rx_byte);
+        let tx_fut = async {
+            let n = tx_pipe.read(&mut tx_buf).await;
+            n
+        };
+
+        match select(rx_fut, tx_fut).await {
+            // Incoming data from UART hardware
+            Either::First(res) => {
+                if let Ok(_) = res {
+                    let _ = rx_pipe.write(&rx_byte).await;
+                }
+            }
+            // Outgoing data waiting in TX pipe
+            Either::Second(n) => {
+                unwrap!(uart.write(&tx_buf[..n]).await);
+            }
+        }
+        yield_now().await;
+    }
+}
--- a/semestralka_1_connected/src/hw_uart_internal/mod.rs
+++ b/semestralka_1_connected/src/hw_uart_internal/mod.rs
@@ -0,0 +1,4 @@
+// src/hw_uart_internal/mod.rs
+
+pub mod driver;
+pub mod usart2;
--- a/semestralka_1_connected/src/hw_uart_internal/usart2.rs
+++ b/semestralka_1_connected/src/hw_uart_internal/usart2.rs
@@ -0,0 +1,11 @@
+// src/hw_uart_internal/usart2.rs
+use defmt::info;
+use embassy_time::Duration;
+
+use crate::hw_uart_pc::safety::preflight_and_suggest_yield_period;
+
+pub fn setup_and_spawn(baudrate: u32) -> Duration {
+    let yield_period = preflight_and_suggest_yield_period(baudrate);
+    info!("HW USART2 safe");
+    yield_period
+}
--- a/semestralka_1_connected/src/hw_uart_pc/driver.rs
+++ b/semestralka_1_connected/src/hw_uart_pc/driver.rs
@@ -0,0 +1,41 @@
+// src/hw_uart_pc/driver.rs
+use defmt::unwrap;
+use embassy_futures::select::{select, Either};
+use embassy_stm32::usart::BufferedUart;
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+use embedded_io_async::{Read, Write};
+use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
+use embassy_futures::yield_now;
+
+#[embassy_executor::task]
+pub async fn uart_task(
+    mut uart: BufferedUart<'static>,
+    tx_pipe: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
+    rx_pipe: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
+) {
+    let mut rx_byte = [0u8; 1];
+    let mut tx_buf = [0u8; 64];
+
+    loop {
+        let rx_fut = uart.read(&mut rx_byte);
+        let tx_fut = async {
+            let n = tx_pipe.read(&mut tx_buf).await;
+            n
+        };
+
+        match select(rx_fut, tx_fut).await {
+            // Incoming data from UART hardware
+            Either::First(res) => {
+                if let Ok(_) = res {
+                    let _ = rx_pipe.write(&rx_byte).await;
+                }
+            }
+            // Outgoing data waiting in TX pipe
+            Either::Second(n) => {
+                unwrap!(uart.write(&tx_buf[..n]).await);
+            }
+        }
+        yield_now().await;
+    }
+}
--- a/semestralka_1_connected/src/hw_uart_pc/mod.rs
+++ b/semestralka_1_connected/src/hw_uart_pc/mod.rs
@@ -0,0 +1,4 @@
+// src/hw_uart_pc/mod.rs
+pub mod driver;
+pub mod usart1;
+pub mod safety;
--- a/semestralka_1_connected/src/hw_uart_pc/safety.rs
+++ b/semestralka_1_connected/src/hw_uart_pc/safety.rs
@@ -0,0 +1,57 @@
+// src/safety.rs
+use defmt::info;
+use embassy_time::Duration;
+
+// ISR RX ring capacity = RX_BUF len
+const ISR_RX_BUF_CAP: usize = 256;
+// Yield 1/2 the time it takes to fill ISR RX ring.
+const YIELD_MARGIN_NUM: u32 = 1;
+const YIELD_MARGIN_DEN: u32 = 2;
+// Ensure RX_PIPE_CAP can hold this.
+const WORST_MAIN_LATENCY_MS: u32 = 20;
+
+pub const TX_PIPE_CAP: usize = 1024;
+pub const RX_PIPE_CAP: usize = 1024;
+
+
+
+/// Perform safety checks and compute yield timing to avoid buffer overflow.
+///
+/// # Panics
+/// Panics if pipe capacities are too small for the configured baud.
+pub fn preflight_and_suggest_yield_period(baud: u32) -> Duration {
+    // Approx bytes per second for 8N1 (10 bits per byte on the wire)
+    let bytes_per_sec = (baud / 10).max(1);
+
+    // Time until ISR RX ring fills, in microseconds.
+    let t_fill_us = (ISR_RX_BUF_CAP as u64) * 1_000_000u64 / (bytes_per_sec as u64);
+
+    // Choose a yield period as a fraction of t_fill.
+    let yield_us = (t_fill_us as u64)
+        .saturating_mul(YIELD_MARGIN_NUM as u64)
+        / (YIELD_MARGIN_DEN as u64);
+
+    // Verify RX pipe can absorb a worst-case app latency so uart_task
+    // can always forward without dropping when it runs.
+    let required_rx_pipe = (bytes_per_sec as u64) * (WORST_MAIN_LATENCY_MS as u64) / 1000;
+
+    if (RX_PIPE_CAP as u64) < required_rx_pipe {
+        core::panic!(
+            "RX pipe too small: have {}B, need >= {}B for {}ms at {} bps",
+            RX_PIPE_CAP, required_rx_pipe, WORST_MAIN_LATENCY_MS, baud
+        );
+    }
+
+    info!(
+        "Preflight: baud={}, rx_isr={}B, rx_pipe={}B, bytes/s={}, t_fill_us={}, yield_us={}",
+        baud,
+        ISR_RX_BUF_CAP,
+        RX_PIPE_CAP,
+        bytes_per_sec,
+        t_fill_us,
+        yield_us
+    );
+
+    // Never choose zero.
+    Duration::from_micros(yield_us.max(1) as u64)
+}
--- a/semestralka_1_connected/src/hw_uart_pc/usart1.rs
+++ b/semestralka_1_connected/src/hw_uart_pc/usart1.rs
@@ -0,0 +1,12 @@
+// src/uart/usart1.rs
+use defmt::info;
+use embassy_time::Duration;
+
+use crate::hw_uart_pc::safety::preflight_and_suggest_yield_period;
+
+pub fn setup_and_spawn(baudrate: u32,) -> Duration {
+    let yield_period: Duration = preflight_and_suggest_yield_period(baudrate);
+    info!("HW USART1 safe");
+
+    yield_period
+}
--- a/semestralka_1_connected/src/lib.rs
+++ b/semestralka_1_connected/src/lib.rs
@@ -0,0 +1,6 @@
+#![no_std]
+
+pub mod software_uart;
+pub mod config;
+pub mod hw_uart_pc;
+pub mod hw_uart_internal;
--- a/semestralka_1_connected/src/software_uart/debug.rs
+++ b/semestralka_1_connected/src/software_uart/debug.rs
@@ -0,0 +1,43 @@
+// src/software_uart/debug.rs
+use defmt::info;
+
+pub fn dump_tim6_regs() {
+    use embassy_stm32::pac::timer::TimBasic;
+    let tim = unsafe { TimBasic::from_ptr(0x4000_1000usize as _) };
+    let sr = tim.sr().read();
+    let dier = tim.dier().read();
+    let cr1 = tim.cr1().read();
+    let arr = tim.arr().read().arr();
+    let psc = tim.psc().read();
+    info!(
+        "TIM6: CR1.CEN={} DIER.UDE={} SR.UIF={} PSC={} ARR={}",
+        cr1.cen(),
+        dier.ude(),
+        sr.uif(),
+        psc,
+        arr
+    );
+}
+
+pub fn dump_dma_ch0_regs() {
+    use embassy_stm32::pac::gpdma::Gpdma;
+    let dma = unsafe { Gpdma::from_ptr(0x4002_0000usize as _) };
+    let ch = dma.ch(0);
+    let cr = ch.cr().read();
+    let tr1 = ch.tr1().read();
+    let tr2 = ch.tr2().read();
+    let br1 = ch.br1().read();
+    info!(
+        "GPDMA1_CH0: EN={} PRIO={} SDW={} DDW={} SINC={} DINC={} REQSEL={} SWREQ={} DREQ={} BNDT={}",
+        cr.en(),
+        cr.prio(),
+        tr1.sdw(),
+        tr1.ddw(),
+        tr1.sinc(),
+        tr1.dinc(),
+        tr2.reqsel(),
+        tr2.swreq(),
+        tr2.dreq(),
+        br1.bndt()
+    );
+}
--- a/semestralka_1_connected/src/software_uart/dma_timer.rs
+++ b/semestralka_1_connected/src/software_uart/dma_timer.rs
@@ -0,0 +1,66 @@
+// src/dma_timer.rs
+
+use embassy_stm32::{
+    peripherals::{TIM6, TIM7},
+    rcc,
+    timer::low_level::Timer,
+    Peri,
+};
+use core::mem;
+use embassy_stm32::timer::BasicInstance;
+use embassy_stm32::pac::timer::vals::Urs;
+
+/// Initializes TIM6 to tick at `baud * oversample` frequency.
+/// Each TIM6 update event triggers one DMA beat.
+pub fn init_tim6_for_uart<'d>(tim6: Peri<'d, TIM6>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM6>();
+    let ll = Timer::new(tim6);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+/// Initializes TIM7 to tick at `baud * oversample` frequency.
+/// Each TIM7 update event triggers one DMA beat.
+pub fn init_tim7_for_uart<'d>(tim7: Peri<'d, TIM7>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM7>();
+    let ll = Timer::new(tim7);
+    configure_basic_timer(&ll, baud, oversample);
+    // Enable Update Interrupt (UIE)
+    ll.regs_basic().dier().modify(|w| {
+        w.set_ude(true);
+        w.set_uie(false);
+    });
+    mem::forget(ll);
+}
+
+// Shared internal helper — identical CR1/ARR setup
+fn configure_basic_timer<T: BasicInstance>(ll: &Timer<'_, T>, baud: u32, oversample: u16) {
+    let f_timer = rcc::frequency::<T>().0;
+    let target = baud.saturating_mul(oversample.max(1) as u32).max(1);
+
+    // Compute ARR (prescaler = 0)
+    let mut arr = (f_timer / target).saturating_sub(1) as u16;
+    if arr == 0 { arr = 1; }
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_cen(false);
+        w.set_opm(false);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+
+    ll.regs_basic().psc().write_value(0u16);
+    ll.regs_basic().arr().write(|w| w.set_arr(arr));
+    ll.regs_basic().dier().modify(|w| w.set_ude(true));
+    ll.regs_basic().egr().write(|w| w.set_ug(true));
+
+    // Clear spurious UIF from UG trigger
+    ll.regs_basic().sr().modify(|w| w.set_uif(false));
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_opm(false);
+        w.set_cen(true);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+}
--- a/semestralka_1_connected/src/software_uart/gpio_dma_uart_rx.rs
+++ b/semestralka_1_connected/src/software_uart/gpio_dma_uart_rx.rs
@@ -0,0 +1,96 @@
+// src/software_uart/runtime.rs
+use embassy_executor::task;
+use embassy_stm32::{
+    dma::Request,
+    peripherals::GPDMA1_CH1,
+    Peri,
+};
+use crate::config::RX_PIN_BIT;
+use embassy_stm32::dma::{
+    ReadableRingBuffer,
+    TransferOptions,
+};
+use crate::config::{RX_OVERSAMPLE, UART_CFG};
+use crate::software_uart::decode_uart_samples;
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use embassy_futures::yield_now;
+use defmt::info;
+
+// datasheet tabulka 137
+pub const TIM7_UP_REQ: Request = 5;
+
+/// RX DMA task: reads GPIO samples paced by TIM7 and fills PIPE_RX
+#[task]
+pub async fn rx_dma_task(
+    ch: Peri<'static, GPDMA1_CH1>,
+    register: *mut u8,
+    ring: &'static mut [u8],
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 4096>,
+) {
+    let mut opts = TransferOptions::default();
+    opts.half_transfer_ir = true;
+    opts.complete_transfer_ir = true;
+
+    // SAFETY: ring is exclusive to this task
+    let mut rx = unsafe { ReadableRingBuffer::new(ch, TIM7_UP_REQ, register, ring, opts) };
+    rx.start();
+
+    // We read into the second half of a buffer, keeping "leftovers" in the first half.
+    const CHUNK_SIZE: usize = 4096;
+    const HISTORY_SIZE: usize = 512; // Enough to hold a potential split frame
+    const TOTAL_BUF_SIZE: usize = HISTORY_SIZE + CHUNK_SIZE;
+    
+    // Logic level buffer
+    let mut level_buf = [0u8; TOTAL_BUF_SIZE];
+    let mut valid_len = 0usize; 
+
+    let mut raw_chunk = [0u8; CHUNK_SIZE];
+
+    loop {
+        let _ = rx.read_exact(&mut raw_chunk).await;
+
+        for (i, b) in raw_chunk.iter().enumerate() {
+             level_buf[valid_len + i] = ((*b >> RX_PIN_BIT) & 1) as u8;
+        }
+        let current_end = valid_len + CHUNK_SIZE;
+
+        // 3. Decode everything we have
+        let (decoded, consumed) = decode_uart_samples(
+            &level_buf[..current_end], 
+            RX_OVERSAMPLE, 
+            &UART_CFG
+        );
+
+        if !decoded.is_empty() {
+             pipe_rx.write(decoded.as_slice()).await;
+
+             for byte in decoded.as_slice() {
+                 // info!("DMA BUFFER CHAR: {} (ASCII: {})", *byte, *byte as char);
+             }
+        }
+
+        // 4. Shift remaining data to front
+        // We processed 'consumed' samples.
+        // We keep everything from 'consumed' up to 'current_end'.
+        let remaining = current_end - consumed;
+        
+        // Safety check: if remaining > HISTORY_SIZE, we are in trouble (buffer too small / decoder stuck).
+        // But for now, just shift.
+        if remaining > 0 {
+            level_buf.copy_within(consumed..current_end, 0);
+        }
+        valid_len = remaining;
+        
+        // If valid_len grows too large (decoder not consuming), we must discard to avoid panic on next write
+        if valid_len >= HISTORY_SIZE {
+             // Discard oldest to make space
+             // logic: we move the last (HISTORY_SIZE/2) to 0.
+             // This effectively "skips" garbage data.
+             let keep = HISTORY_SIZE / 2;
+             level_buf.copy_within(valid_len - keep..valid_len, 0);
+             valid_len = keep;
+        }
+
+        yield_now().await;
+    }
+}
--- a/semestralka_1_connected/src/software_uart/gpio_dma_uart_tx.rs
+++ b/semestralka_1_connected/src/software_uart/gpio_dma_uart_tx.rs
@@ -0,0 +1,91 @@
+// src/software_uart/gpio_dma_uart_tx.rs
+use embassy_executor::task;
+use embassy_stm32::{
+    dma::{Request, Transfer, TransferOptions},
+    peripherals::GPDMA1_CH0,
+    Peri,
+};
+use embassy_futures::yield_now;
+use defmt::info;
+
+use embassy_sync::pipe::Pipe;
+use crate::config::{TX_PIN_BIT, UART_CFG};
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use crate::software_uart::uart_emulation::encode_uart_byte_cfg;
+
+pub const TIM6_UP_REQ: Request = 4;
+
+pub async fn encode_uart_frames<'a>(
+    pin_bit: u8,
+    bytes: &[u8],
+    out_buf: &'a mut [u32],
+) -> usize {
+    let mut offset = 0;
+    for &b in bytes {
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(pin_bit, b, &UART_CFG, &mut frame);
+
+        if offset + used <= out_buf.len() {
+            out_buf[offset..offset + used].copy_from_slice(&frame[..used]);
+            offset += used;
+        } else {
+            break;
+        }
+
+        yield_now().await;
+    }
+    offset
+}
+
+#[task]
+pub async fn tx_dma_task(
+    mut ch: Peri<'static, GPDMA1_CH0>,
+    register: *mut u32, // GPIOx_BSRR
+    _tx_ring_mem: &'static mut [u32],
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    info!("TX DMA task ready (One‑shot)");
+
+    let mut frame_buf = [0u32; 4096];
+    let mut rx_buf = [0u8; 256];
+    let tim6 = embassy_stm32::pac::TIM6;
+
+    loop {
+        let n = pipe_rx.read(&mut rx_buf).await;
+        if n == 0 {
+            yield_now().await;
+            continue;
+        }
+
+        let used = encode_uart_frames(TX_PIN_BIT, &rx_buf[..n], &mut frame_buf).await;
+        if used > 0 {
+            // Align arming to a clean TIM6 update boundary:
+            // 1) clear any pending UIF
+            tim6.sr().write(|w| w.set_uif(false));
+            // 2) wait for the next UIF (next bit tick)
+            while !tim6.sr().read().uif() {
+                yield_now().await;
+            }
+            // 3) clear UIF so first DMA beat happens on the FOLLOWING tick
+            tim6.sr().write(|w| w.set_uif(false));
+
+            let mut tx_opts = TransferOptions::default();
+            tx_opts.half_transfer_ir = false;
+            tx_opts.complete_transfer_ir = true;
+
+            unsafe {
+                let transfer = Transfer::new_write(
+                    ch.reborrow(),
+                    TIM6_UP_REQ,
+                    &frame_buf[..used],
+                    register,
+                    tx_opts,
+                );
+                transfer.await;
+            }
+        }
+
+        // info!("tx_dma_task sent {} words", used);
+        yield_now().await;
+    }
+}
--- a/semestralka_1_connected/src/software_uart/mod.rs
+++ b/semestralka_1_connected/src/software_uart/mod.rs
@@ -0,0 +1,13 @@
+// src/software_uart/mod.rs
+
+pub mod gpio_dma_uart_tx;
+pub mod gpio_dma_uart_rx;
+pub mod dma_timer;
+pub mod uart_emulation;
+pub mod debug;
+
+pub use gpio_dma_uart_tx::*;
+pub use gpio_dma_uart_rx::*;
+pub use dma_timer::*;
+pub use uart_emulation::*;
+pub use debug::*;
--- a/semestralka_1_connected/src/software_uart/uart_emulation.rs
+++ b/semestralka_1_connected/src/software_uart/uart_emulation.rs
@@ -0,0 +1,204 @@
+// src/software_uart/uart_emulation.rs
+use heapless::Vec;
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Parity {
+    None,
+    Even,
+    Odd,
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum StopBits {
+    One,
+    Two,
+}
+
+#[derive(Clone, Copy, Debug)]
+pub struct UartConfig {
+    pub data_bits: u8,
+    pub parity: Parity,
+    pub stop_bits: StopBits,
+}
+
+impl Default for UartConfig {
+    fn default() -> Self {
+        Self {
+            data_bits: 8,
+            parity: Parity::None,
+            stop_bits: StopBits::One,
+        }
+    }
+}
+
+/// Encodes one byte into a sequence of GPIO BSRR words
+pub fn encode_uart_byte_cfg(
+    pin_bit: u8,
+    data: u8,
+    cfg: &UartConfig,
+    out: &mut [u32; 12],
+) -> usize {
+    // GPIOx_BSRR register str. 636 kap. 13.4.7
+    let set_high = |bit: u8| -> u32 { 1u32 << bit };
+    // let set_low = |bit: u8| -> u32 { 0 }; // ODR
+    let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) }; // BSRR
+
+    let mut idx = 0usize;
+
+    // START bit (LOW)
+    out[idx] = set_low(pin_bit);
+    idx += 1;
+
+    // Data bits, LSB-first
+    let nbits = cfg.data_bits.clamp(5, 8);
+    for i in 0..nbits {
+        let one = ((data >> i) & 1) != 0;
+        out[idx] = if one { set_high(pin_bit) } else { set_low(pin_bit) };
+        idx += 1;
+    }
+
+    // Parity
+    match cfg.parity {
+        Parity::None => {}
+        Parity::Even | Parity::Odd => {
+            let mask: u8 = if nbits == 8 { 0xFF } else { (1u16 << nbits) as u8 - 1 };
+            let ones = (data & mask).count_ones() & 1;
+            let par_bit_is_one = match cfg.parity {
+                Parity::Even => ones == 1,
+                Parity::Odd => ones == 0,
+                _ => false,
+            };
+            out[idx] = if par_bit_is_one {
+                set_high(pin_bit)
+            } else {
+                set_low(pin_bit)
+            };
+            idx += 1;
+        }
+    }
+
+    // STOP bits (HIGH)
+    let stop_ticks = match cfg.stop_bits {
+        StopBits::One => 1usize,
+        StopBits::Two => 2usize,
+    };
+    for _ in 0..stop_ticks {
+        out[idx] = set_high(pin_bit);
+        idx += 1;
+    }
+
+    idx
+}
+
+/// Decode an oversampled stream of logic levels into UART bytes.
+/// Returns (decoded bytes, number of samples consumed/processed).
+pub fn decode_uart_samples(
+    samples: &[u8],
+    oversample: u16,
+    cfg: &UartConfig,
+) -> (heapless::Vec<u8, 256>, usize) {
+    let mut out = Vec::<u8, 256>::new();
+    let mut idx = 0usize;
+    let nbits = cfg.data_bits as usize;
+    let ovs = oversample as usize;
+
+    // Calculate total frame width in samples to ensure we have enough data
+    // 1 start + n data + parity? + stops
+    let parity_bits = match cfg.parity {
+        Parity::None => 0,
+        _ => 1,
+    };
+    let stop_bits_count = match cfg.stop_bits {
+        StopBits::One => 1,
+        StopBits::Two => 2,
+    };
+    let frame_bits = 1 + nbits + parity_bits + stop_bits_count;
+    let frame_len = frame_bits * ovs;
+
+    // Helper: Majority vote over 3 samples centered at `i`
+    let get_bit = |i: usize| -> u8 {
+        let mut votes = 0;
+        // Check i-1, i, i+1. Saturating sub/add handles boundaries roughly.
+        if i > 0 && samples.get(i - 1).map_or(true, |&x| x != 0) {
+            votes += 1;
+        }
+        if samples.get(i).map_or(true, |&x| x != 0) {
+            votes += 1;
+        }
+        if samples.get(i + 1).map_or(true, |&x| x != 0) {
+            votes += 1;
+        }
+
+        if votes >= 2 {
+            1
+        } else {
+            0
+        }
+    };
+
+    // We loop while we have enough remaining samples for a full frame
+    while idx + frame_len <= samples.len() {
+        // Wait for falling edge (High -> Low)
+        // samples[idx] == 1 (Idle/Stop) && samples[idx+1] == 0 (Start)
+        if samples[idx] != 0 && samples[idx + 1] == 0 {
+            // Align to center of START bit
+            // Start bit begins at idx+1. Center is at idx + 1 + (ovs/2)
+            let center_offset = 1 + (ovs / 2);
+            let mut scan_idx = idx + center_offset;
+
+            // 1. Validate Start Bit (Must be 0)
+            if get_bit(scan_idx) != 0 {
+                idx += 1; // False start (noise), move on
+                continue;
+            }
+
+            // Move to center of first data bit
+            scan_idx += ovs;
+
+            // 2. Read Data Bits
+            let mut data: u8 = 0;
+            for bit in 0..nbits {
+                if get_bit(scan_idx) == 1 {
+                    data |= 1 << bit;
+                }
+                scan_idx += ovs;
+            }
+
+            // 3. Skip Parity (if any)
+            if cfg.parity != Parity::None {
+                scan_idx += ovs;
+            }
+
+            // 4. Validate Stop Bit (Must be 1)
+            // If stop bit is 0, it's a framing error. We reject the whole byte.
+            if get_bit(scan_idx) == 0 {
+                idx += 1; // Try to find a real start bit on the next sample
+                continue;
+            }
+
+            // 5. Byte is valid
+            let _ = out.push(data);
+
+            // 6. Active Resync: Fast-forward through the stop bit(s) and idle time
+            // scan_idx is currently at the center of the Stop bit.
+            idx = scan_idx;
+            // Advance while we are reading High (1).
+            // As soon as we see Low (0), we stop. That 0 is the beginning of the NEXT start bit.
+            // The outer loop expects `idx` to be the High *before* the start bit, so we will handle that.
+            while idx < samples.len() && samples[idx] != 0 {
+                idx += 1;
+            }
+            // Back up one step.
+            // The outer loop logic is: `if samples[idx] != 0 && samples[idx+1] == 0`.
+            // If we stopped at `idx` because it was 0, then `idx-1` was the last 1 (Idle).
+            if idx > 0 {
+                idx -= 1;
+            }
+        } else {
+            // No start bit detected here, move to next sample
+            idx += 1;
+        }
+    }
+
+    (out, idx)
+}
--- a/semestralka_1_connected/tests/uart_emulation.rs
+++ b/semestralka_1_connected/tests/uart_emulation.rs
@@ -0,0 +1,41 @@
+#![no_std]
+#![no_main]
+
+use dma_gpio as _;
+use panic_probe as _;
+use defmt_rtt as _;
+
+#[defmt_test::tests]
+mod tests {
+    use defmt::assert_eq;
+    use dma_gpio::software_uart::uart_emulation::{
+        encode_uart_byte_cfg, UartConfig, Parity, StopBits
+    };
+
+    const TX_PIN_BIT: u8 = 2;
+
+    #[test]
+    fn test_encode_8n1() {
+        let cfg = UartConfig::default();
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(TX_PIN_BIT, 0x55, &cfg, &mut frame);
+        
+        assert_eq!(used, 10);
+        assert_eq!(frame[0], 1u32 << 18); // Start LOW
+        assert_eq!(frame[9], 1u32 << 2);  // Stop HIGH
+    }
+
+    #[test]
+    fn test_encode_parity() {
+        let cfg = UartConfig {
+            data_bits: 8,
+            parity: Parity::Even,
+            stop_bits: StopBits::One,
+        };
+        
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(TX_PIN_BIT, 0x00, &cfg, &mut frame);
+        
+        assert_eq!(used, 11);
+    }
+}
--- a/semestralka_1b_rx/.cargo/config.toml
+++ b/semestralka_1b_rx/.cargo/config.toml
@@ -0,0 +1,15 @@
+[build]
+target = "thumbv8m.main-none-eabihf"
+
+[target.thumbv8m.main-none-eabihf]
+runner = "probe-rs run --chip STM32U575ZITxQ"
+
+rustflags = [
+  "-C", "linker=rust-lld",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "link-arg=-Tdefmt.x",
+  "-C", "link-arg=--nmagic",
+]
+
+[package.metadata.cargo-flash]
+chip = "STM32U575ZIT"
--- a/semestralka_1b_rx/.gitignore
+++ b/semestralka_1b_rx/.gitignore
@@ -0,0 +1 @@
+/target
--- a/semestralka_1b_rx/Cargo.lock
+++ b/semestralka_1b_rx/Cargo.lock
--- a/semestralka_1b_rx/Cargo.toml
+++ b/semestralka_1b_rx/Cargo.toml
@@ -0,0 +1,45 @@
+[package]
+authors = ["Priec <filippriec@gmail.com>"]
+name = "dma_gpio"
+edition = "2024"
+version = "0.1.0"
+
+
+[dependencies]
+cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.5"
+panic-halt = "1.0.0"
+embassy-executor = { path = "/home/filip/programs/embassy/embassy-executor", features = ["arch-cortex-m", "executor-thread"] }
+embassy-futures = { path = "/home/filip/programs/embassy/embassy-futures" }
+embassy-sync = { path = "/home/filip/programs/embassy/embassy-sync" }
+embassy-time = { path = "/home/filip/programs/embassy/embassy-time", features = ["tick-hz-32_768"] }
+embassy-hal-internal = { path = "/home/filip/programs/embassy/embassy-hal-internal" }
+embassy-usb = { path = "/home/filip/programs/embassy/embassy-usb" }
+embassy-stm32 = { path = "/home/filip/programs/embassy/embassy-stm32", features = ["unstable-pac", "stm32u575zi", "time-driver-tim2", "memory-x", "defmt"] }
+
+embedded-hal = "1.0.0"
+embedded-graphics = "0.8.1"
+heapless = { version = "0.9.1", default-features = false }
+micromath = "2.1.0"
+tinybmp = "0.6.0"
+panic-probe = { version = "1.0.0", features = ["defmt"] }
+defmt-rtt = "1.1.0"
+defmt = "1.0.1"
+static_cell = "2.1.1"
+embedded-io = "0.6.1"
+embedded-io-async = "0.6.1"
+
+[dev-dependencies]
+defmt-test = "0.4.0"
+
+[[test]]
+name = "uart_emulation"
+harness = false
+
+[lib]
+test = false
+
+[[bin]]
+name = "main"
+path = "src/bin/main.rs"
+test = false
--- a/semestralka_1b_rx/LICENSE-APACHE
+++ b/semestralka_1b_rx/LICENSE-APACHE
@@ -0,0 +1,201 @@
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--- a/semestralka_1b_rx/LICENSE-MIT
+++ b/semestralka_1b_rx/LICENSE-MIT
@@ -0,0 +1,23 @@
+Permission is hereby granted, free of charge, to any
+person obtaining a copy of this software and associated
+documentation files (the "Software"), to deal in the
+Software without restriction, including without
+limitation the rights to use, copy, modify, merge,
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+the Software, and to permit persons to whom the Software
+is furnished to do so, subject to the following
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+
+The above copyright notice and this permission notice
+shall be included in all copies or substantial portions
+of the Software.
+
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+TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
+IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.
--- a/semestralka_1b_rx/Makefile
+++ b/semestralka_1b_rx/Makefile
@@ -0,0 +1,23 @@
+TARGET = thumbv8m.main-none-eabihf
+CHIP = STM32U575ZI
+BIN = stm32u5-blinky
+MODE ?= release
+TARGET_DIR = target/$(TARGET)/$(MODE)
+ELF = $(TARGET_DIR)/$(BIN)
+PROBE = probe-rs
+
+.PHONY: all build flash clean empty
+
+all: build
+
+build:
+	cargo build --$(MODE)
+
+flash: build
+	$(PROBE) run --chip $(CHIP) $(ELF)
+
+empty:
+	$(PROBE) erase --chip $(CHIP)
+
+clean:
+	cargo clean
--- a/semestralka_1b_rx/README.md
+++ b/semestralka_1b_rx/README.md
@@ -0,0 +1,232 @@
+# `app-template`
+
+> Quickly set up a [`probe-rs`] + [`defmt`] + [`flip-link`] embedded project
+
+[`probe-rs`]: https://crates.io/crates/probe-rs
+[`defmt`]: https://github.com/knurling-rs/defmt
+[`flip-link`]: https://github.com/knurling-rs/flip-link
+
+## Dependencies
+
+### 1. `flip-link`:
+
+```bash
+cargo install flip-link
+```
+
+### 2. `probe-rs`:
+
+Install probe-rs by following the instructions at <https://probe.rs/docs/getting-started/installation/>.
+
+### 3. [`cargo-generate`]:
+
+```bash
+cargo install cargo-generate
+```
+
+[`cargo-generate`]: https://crates.io/crates/cargo-generate
+
+> *Note:* You can also just clone this repository instead of using `cargo-generate`, but this involves additional manual adjustments.
+
+## Setup
+
+### 1. Initialize the project template
+
+```bash
+cargo generate \
+    --git https://github.com/knurling-rs/app-template \
+    --branch main \
+    --name my-app
+```
+
+If you look into your new `my-app` folder, you'll find that there are a few `TODO`s in the files marking the properties you need to set.
+
+Let's walk through them together now.
+
+### 2. Set `probe-rs` chip
+
+Pick a chip from ` probe-rs chip list` and enter it into `.cargo/config.toml`.
+
+If, for example, you have a nRF52840 Development Kit as used in one of [our exercises], replace `{{chip}}` with `nRF52840_xxAA`.
+
+[our workshops]: https://rust-exercises.ferrous-systems.com
+
+```diff
+ # .cargo/config.toml
+-runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format=oneline"]
+runner = ["probe-rs", "run", "--chip", "nRF52840_xxAA", "--log-format=oneline"]
+```
+
+### 3. Adjust the compilation target
+
+In `.cargo/config.toml`, pick the right compilation target for your board.
+
+```diff
+ # .cargo/config.toml
+ [build]
+-target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
+-# target = "thumbv7m-none-eabi"    # Cortex-M3
+-# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
+-# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
+target = "thumbv7em-none-eabihf" # Cortex-M4F (with FPU)
+```
+
+Add the target with `rustup`.
+
+```bash
+rustup target add thumbv7em-none-eabihf
+```
+
+### 4. Add a HAL as a dependency
+
+In `Cargo.toml`, list the Hardware Abstraction Layer (HAL) for your board as a dependency.
+
+For the nRF52840 you'll want to use the [`nrf52840-hal`].
+
+[`nrf52840-hal`]: https://crates.io/crates/nrf52840-hal
+
+```diff
+ # Cargo.toml
+ [dependencies]
+-# some-hal = "1.2.3"
+nrf52840-hal = "0.14.0"
+```
+
+⚠️ Note for RP2040 users ⚠️
+
+You will need to not just specify the `rp-hal` HAL, but a BSP (board support crate) which includes a second stage bootloader. Please find a list of available BSPs [here](https://github.com/rp-rs/rp-hal-boards#packages).
+
+### 5. Import your HAL
+
+Now that you have selected a HAL, fix the HAL import in `src/lib.rs`
+
+```diff
+ // my-app/src/lib.rs
+-// use some_hal as _; // memory layout
+use nrf52840_hal as _; // memory layout
+```
+
+### (6. Get a linker script)
+
+Some HAL crates require that you manually copy over a file called `memory.x` from the HAL to the root of your project. For nrf52840-hal, this is done automatically so no action is needed. For other HAL crates, see their documentation on where to find an example file.
+
+The `memory.x` file should look something like:
+
+```text
+MEMORY
+{
+  FLASH : ORIGIN = 0x00000000, LENGTH = 1024K
+  RAM   : ORIGIN = 0x20000000, LENGTH = 256K
+}
+```
+
+The `memory.x` file is included in the `cortex-m-rt` linker script `link.x`, and so `link.x` is the one you should tell `rustc` to use (see the `.cargo/config.toml` file where we do that).
+
+### 7. Run!
+
+You are now all set to `cargo-run` your first `defmt`-powered application!
+There are some examples in the `src/bin` directory.
+
+Start by `cargo run`-ning `my-app/src/bin/hello.rs`:
+
+```console
+$ # `rb` is an alias for `run --bin`
+$ cargo rb hello
+    Finished `dev` profile [optimized + debuginfo] target(s) in 0.01s
+     Running `probe-rs run --chip nrf52840_xxaa --log-format=oneline target/thumbv6m-none-eabi/debug/hello`
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.79 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+Hello, world!
+
+$ echo $?
+0
+```
+
+If you're running out of memory (`flip-link` bails with an overflow error), you can decrease the size of the device memory buffer by setting the `DEFMT_RTT_BUFFER_SIZE` environment variable. The default value is 1024 bytes, and powers of two should be used for optimal performance:
+
+```console
+$ DEFMT_RTT_BUFFER_SIZE=64 cargo rb hello
+```
+
+### (8. Set `rust-analyzer.linkedProjects`)
+
+If you are using [rust-analyzer] with VS Code for IDE-like features you can add following configuration to your `.vscode/settings.json` to make it work transparently across workspaces. Find the details of this option in the [RA docs].
+
+```json
+{
+    "rust-analyzer.linkedProjects": [
+        "Cargo.toml",
+        "firmware/Cargo.toml",
+    ]
+}
+```
+
+[RA docs]: https://rust-analyzer.github.io/manual.html#configuration
+[rust-analyzer]: https://rust-analyzer.github.io/
+
+## Running tests
+
+The template comes configured for running unit tests and integration tests on the target.
+
+Unit tests reside in the library crate and can test private API; the initial set of unit tests are in `src/lib.rs`.
+`cargo test --lib` will run those unit tests.
+
+```console
+$ cargo test --lib
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.15s
+     Running unittests src/lib.rs (target/thumbv6m-none-eabi/debug/deps/example-2b0d0e25d141bf57)
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.99 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.33 KiB/s (took 1s)                                                                                                                        Finished in 1.10s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Integration tests reside in the `tests` directory; the initial set of integration tests are in `tests/integration.rs`.
+`cargo test --test integration` will run those integration tests.
+Note that the argument of the `--test` flag must match the name of the test file in the `tests` directory.
+
+```console
+$ cargo test --test integration
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.10s
+     Running tests/integration.rs (target/thumbv6m-none-eabi/debug/deps/integration-aaaff41151f6a722)
+      Erasing ✔ 100% [####################]   8.00 KiB @  16.03 KiB/s (took 0s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Note that to add a new test file to the `tests` directory you also need to add a new `[[test]]` section to `Cargo.toml`.
+
+To run all the tests via `cargo test` the tests need to be explicitly disabled for all the existing binary targets.
+See `Cargo.toml` for details on how to do this.
+
+## Support
+
+`app-template` is part of the [Knurling] project, [Ferrous Systems]' effort at
+improving tooling used to develop for embedded systems.
+
+If you think that our work is useful, consider sponsoring it via [GitHub
+Sponsors].
+
+## License
+
+Licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+  http://www.apache.org/licenses/LICENSE-2.0)
+
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+### Contribution
+
+Unless you explicitly state otherwise, any contribution intentionally submitted
+for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
+licensed as above, without any additional terms or conditions.
+
+[Knurling]: https://knurling.ferrous-systems.com
+[Ferrous Systems]: https://ferrous-systems.com/
+[GitHub Sponsors]: https://github.com/sponsors/knurling-rs
--- a/semestralka_1b_rx/src/bin/main.rs
+++ b/semestralka_1b_rx/src/bin/main.rs
@@ -0,0 +1,187 @@
+// src/bin/main.rs
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_time::Instant;
+use embassy_stm32::dma::Request;
+use embassy_stm32::gpio::{Input, Output, Level, Pull, Speed};
+use dma_gpio::software_uart::{
+    dma_timer::{init_tim6_for_uart, init_tim7_for_uart},
+    gpio_dma_uart_rx::rx_dma_task,
+    debug::dump_tim6_regs,
+};
+use dma_gpio::config::{BAUD, RX_OVERSAMPLE, TX_OVERSAMPLE};
+use dma_gpio::config::{TX_RING_BYTES, RX_RING_BYTES};
+use dma_gpio::software_uart::gpio_dma_uart_tx::tx_dma_task;
+use static_cell::StaticCell;
+use embassy_futures::yield_now;
+use dma_gpio::hw_uart_pc::usart1;
+use dma_gpio::hw_uart_pc::driver::uart_task;
+use embassy_stm32::usart::{BufferedUart, Config, BufferedInterruptHandler};
+use embassy_stm32::peripherals;
+use embassy_stm32::bind_interrupts;
+use dma_gpio::config::{PIPE_HW_TX, PIPE_HW_RX, PIPE_SW_TX, PIPE_SW_RX};
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use dma_gpio::hw_uart_internal::usart2;
+use dma_gpio::hw_uart_internal::driver::uart_task as uart_task_internal;
+use dma_gpio::config::{PIPE_INT_TX, PIPE_INT_RX};
+use embassy_time::{Duration, Timer};
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    USART1 => BufferedInterruptHandler<peripherals::USART1>;
+});
+bind_interrupts!(struct Irqs2 {
+    USART2 => BufferedInterruptHandler<peripherals::USART2>;
+});
+
+// Software uart
+pub const TIM6_UP_REQ: Request = 4;
+static SW_TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
+static SW_RX_RING: StaticCell<[u8; RX_RING_BYTES]> = StaticCell::new();
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    info!("boot");
+    let p = embassy_stm32::init(Default::default());
+    info!("init m8");
+
+    // HARDWARE UART to the PC
+    let mut cfg = Config::default();
+    cfg.baudrate = BAUD;
+    static TX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
+    static RX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
+    let uart = BufferedUart::new(
+        p.USART1,
+        p.PA10, // RX pin
+        p.PA9,  // TX pin
+        TX_BUF.init([0; 256]),
+        RX_BUF.init([0; 256]),
+        Irqs,
+        cfg,
+    ).unwrap();
+    let yield_period = usart1::setup_and_spawn(BAUD);
+    spawner.spawn(uart_task(uart, &PIPE_HW_TX, &PIPE_HW_RX).unwrap());
+    // END OF HARDWARE UART to the PC
+
+    // INTERNAL HARDWARE UART (USART2)
+    let mut cfg2 = Config::default();
+    cfg2.baudrate = BAUD;
+    static TX_BUF2: StaticCell<[u8; 256]> = StaticCell::new();
+    static RX_BUF2: StaticCell<[u8; 256]> = StaticCell::new();
+
+    let uart2 = BufferedUart::new(
+        p.USART2,
+        p.PA3, // RX
+        p.PA2, // TX
+        TX_BUF2.init([0; 256]),
+        RX_BUF2.init([0; 256]),
+        Irqs2,
+        cfg2,
+    ).unwrap();
+
+    let _ = usart2::setup_and_spawn(BAUD);
+    spawner.spawn(uart_task_internal(uart2, &PIPE_INT_TX, &PIPE_INT_RX).unwrap());
+    info!("USART2 ready");
+    // END OF INTERNAL HARDWARE UART (USART2)
+    
+    // USART1 <-> USART2 bridge
+    spawner.spawn(bridge_usart1_rx_to_usart2_tx(&PIPE_HW_RX, &PIPE_INT_TX).unwrap());
+    spawner.spawn(bridge_usart2_rx_to_usart1_tx(&PIPE_INT_RX, &PIPE_HW_TX).unwrap());
+    info!("USART1 <-> USART2 bridge active");
+    // END OF USART1 <-> USART2 bridge 
+
+    // SOFTWARE UART 
+    // let _rx = Input::new(p.PD6, Pull::Up);
+    let mut rx_pin = Input::new(p.PD6, Pull::Up);
+    let _tx = Output::new(p.PB0, Level::High, Speed::VeryHigh);
+    init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE);
+    init_tim7_for_uart(p.TIM7, BAUD, RX_OVERSAMPLE);
+    dump_tim6_regs();
+
+    // Safe one-time init from StaticCell
+    let sw_rx_ring: &mut [u8; RX_RING_BYTES] = SW_RX_RING.init([0; RX_RING_BYTES]);
+    // let sw_tx_ring: &mut [u32; TX_RING_BYTES] = SW_TX_RING.init([0; TX_RING_BYTES]);
+    
+    let gpio_idr = embassy_stm32::pac::GPIOD.idr().as_ptr() as *mut u8; // POZOR C REGISTER
+    spawner.spawn(rx_dma_task(p.GPDMA1_CH1, gpio_idr, sw_rx_ring, &PIPE_SW_RX).unwrap());
+
+    // Create and start the TX DMA ring in main.
+    let bsrr_ptr = embassy_stm32::pac::GPIOB.bsrr().as_ptr() as *mut u32; // POZOR B REGISTER
+    // let odr_ptr = embassy_stm32::pac::GPIOA.odr().as_ptr() as *mut u32; // NEEDS DECODE CHANGE
+    // spawner.spawn(tx_dma_task(p.GPDMA1_CH0, bsrr_ptr, sw_tx_ring, &PIPE_SW_TX).unwrap());
+    // EDN OF SOFTWARE UART 
+
+
+    let mut last_yield = Instant::now();
+    let mut buf = [0u8; 32];
+
+    let mut last_state: u8 = 0;
+    loop {
+        info!("tick start");
+        // Timer::after(Duration::from_millis(100)).await;
+        // info!("tick end");
+
+        // let n1 = PIPE_HW_RX.read(&mut buf).await;
+        // if n1 > 0 {
+        //     info!("PC received: {:a}", &buf[..n1]);
+        //     let _ = PIPE_SW_TX.write(&buf[..n1]).await;
+        //     info!("SW UART TX sent echo: {:a}", &buf[..n1]);
+        // }
+        // yield_now().await;
+
+        let bit = rx_pin.is_high();
+        if bit as u8 != last_state {
+            info!(
+                "SW RX -> PD6 changed, new state = {}",
+                if bit { "HIGH" } else { "LOW" }
+            );
+            last_state = bit as u8;
+        }
+        Timer::after(Duration::from_millis(1)).await;
+
+        let n2 = PIPE_SW_RX.read(&mut buf).await;
+        if n2 > 0 {
+            info!("SW UART RX pipe: {:a}", &buf[..n2]);
+        }
+        yield_now().await;
+
+        // if Instant::now().duration_since(last_yield) >= yield_period {
+        //     yield_now().await;
+        //     last_yield = Instant::now();
+        // }
+
+    }
+}
+
+#[embassy_executor::task]
+pub async fn bridge_usart1_rx_to_usart2_tx(
+    usart1_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+    usart2_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut buf = [0u8; 64];
+    loop {
+        let n = usart1_rx.read(&mut buf).await;
+        if n > 0 {
+            let _ = usart2_tx.write(&buf[..n]).await;
+            info!("bridge: USART1 -> USART2 sent {} bytes", n);
+        }
+    }
+}
+
+#[embassy_executor::task]
+pub async fn bridge_usart2_rx_to_usart1_tx(
+    usart2_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+    usart1_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut buf = [0u8; 64];
+    loop {
+        let n = usart2_rx.read(&mut buf).await;
+        if n > 0 {
+            let _ = usart1_tx.write(&buf[..n]).await;
+            info!("bridge: USART2 -> USART1 sent {} bytes", n);
+        }
+    }
+}
--- a/semestralka_1b_rx/src/config.rs
+++ b/semestralka_1b_rx/src/config.rs
@@ -0,0 +1,35 @@
+// src/config.rs
+use crate::software_uart::uart_emulation::{Parity, StopBits, UartConfig};
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+
+pub const BAUD: u32 = 9_600;
+// pub const TX_PIN_BIT: u8 = 2; // PA2
+// pub const RX_PIN_BIT: u8 = 3; // PA3
+pub const TX_PIN_BIT: u8 = 0; // PB2
+pub const RX_PIN_BIT: u8 = 3; // PC3
+pub const TX_OVERSAMPLE: u16 = 1;
+pub const RX_OVERSAMPLE: u16 = 16;
+
+pub const RX_RING_BYTES: usize = 4096;
+pub const TX_RING_BYTES: usize = 4096;
+
+pub const PIPE_HW_TX_SIZE: usize = 1024;
+pub const PIPE_HW_RX_SIZE: usize = 1024;
+pub const PIPE_SW_TX_SIZE: usize = 1024;
+pub const PIPE_SW_RX_SIZE: usize = 1024;
+pub const PIPE_INT_TX_SIZE: usize = 1024;
+pub const PIPE_INT_RX_SIZE: usize = 1024;
+
+pub static PIPE_HW_TX: Pipe<CriticalSectionRawMutex, PIPE_HW_TX_SIZE> = Pipe::new();
+pub static PIPE_HW_RX: Pipe<CriticalSectionRawMutex, PIPE_HW_RX_SIZE> = Pipe::new();
+pub static PIPE_SW_TX: Pipe<CriticalSectionRawMutex, PIPE_SW_TX_SIZE> = Pipe::new();
+pub static PIPE_SW_RX: Pipe<CriticalSectionRawMutex, PIPE_SW_RX_SIZE> = Pipe::new();
+pub static PIPE_INT_TX: Pipe<CriticalSectionRawMutex, PIPE_INT_TX_SIZE> = Pipe::new();
+pub static PIPE_INT_RX: Pipe<CriticalSectionRawMutex, PIPE_INT_RX_SIZE> = Pipe::new();
+
+pub const UART_CFG: UartConfig = UartConfig {
+    data_bits: 8,
+    parity: Parity::None,
+    stop_bits: StopBits::One,
+};
--- a/semestralka_1b_rx/src/hw_uart_internal/driver.rs
+++ b/semestralka_1b_rx/src/hw_uart_internal/driver.rs
@@ -0,0 +1,39 @@
+// src/hw_uart_internal/driver.rs
+use defmt::unwrap;
+use embassy_futures::select::{select, Either};
+use embassy_stm32::usart::BufferedUart;
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+use embedded_io_async::{Read, Write};
+use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
+
+#[embassy_executor::task]
+pub async fn uart_task(
+    mut uart: BufferedUart<'static>,
+    tx_pipe: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
+    rx_pipe: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
+) {
+    let mut rx_byte = [0u8; 1];
+    let mut tx_buf = [0u8; 64];
+
+    loop {
+        let rx_fut = uart.read(&mut rx_byte);
+        let tx_fut = async {
+            let n = tx_pipe.read(&mut tx_buf).await;
+            n
+        };
+
+        match select(rx_fut, tx_fut).await {
+            // Incoming data from UART hardware
+            Either::First(res) => {
+                if let Ok(_) = res {
+                    let _ = rx_pipe.write(&rx_byte).await;
+                }
+            }
+            // Outgoing data waiting in TX pipe
+            Either::Second(n) => {
+                unwrap!(uart.write(&tx_buf[..n]).await);
+            }
+        }
+    }
+}
--- a/semestralka_1b_rx/src/hw_uart_internal/mod.rs
+++ b/semestralka_1b_rx/src/hw_uart_internal/mod.rs
@@ -0,0 +1,4 @@
+// src/hw_uart_internal/mod.rs
+
+pub mod driver;
+pub mod usart2;
--- a/semestralka_1b_rx/src/hw_uart_internal/usart2.rs
+++ b/semestralka_1b_rx/src/hw_uart_internal/usart2.rs
@@ -0,0 +1,11 @@
+// src/hw_uart_internal/usart2.rs
+use defmt::info;
+use embassy_time::Duration;
+
+use crate::hw_uart_pc::safety::preflight_and_suggest_yield_period;
+
+pub fn setup_and_spawn(baudrate: u32) -> Duration {
+    let yield_period = preflight_and_suggest_yield_period(baudrate);
+    info!("HW USART2 safe");
+    yield_period
+}
--- a/semestralka_1b_rx/src/hw_uart_pc/driver.rs
+++ b/semestralka_1b_rx/src/hw_uart_pc/driver.rs
@@ -0,0 +1,39 @@
+// src/hw_uart_pc/driver.rs
+use defmt::unwrap;
+use embassy_futures::select::{select, Either};
+use embassy_stm32::usart::BufferedUart;
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+use embedded_io_async::{Read, Write};
+use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
+
+#[embassy_executor::task]
+pub async fn uart_task(
+    mut uart: BufferedUart<'static>,
+    tx_pipe: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
+    rx_pipe: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
+) {
+    let mut rx_byte = [0u8; 1];
+    let mut tx_buf = [0u8; 64];
+
+    loop {
+        let rx_fut = uart.read(&mut rx_byte);
+        let tx_fut = async {
+            let n = tx_pipe.read(&mut tx_buf).await;
+            n
+        };
+
+        match select(rx_fut, tx_fut).await {
+            // Incoming data from UART hardware
+            Either::First(res) => {
+                if let Ok(_) = res {
+                    let _ = rx_pipe.write(&rx_byte).await;
+                }
+            }
+            // Outgoing data waiting in TX pipe
+            Either::Second(n) => {
+                unwrap!(uart.write(&tx_buf[..n]).await);
+            }
+        }
+    }
+}
--- a/semestralka_1b_rx/src/hw_uart_pc/mod.rs
+++ b/semestralka_1b_rx/src/hw_uart_pc/mod.rs
@@ -0,0 +1,4 @@
+// src/hw_uart_pc/mod.rs
+pub mod driver;
+pub mod usart1;
+pub mod safety;
--- a/semestralka_1b_rx/src/hw_uart_pc/safety.rs
+++ b/semestralka_1b_rx/src/hw_uart_pc/safety.rs
@@ -0,0 +1,57 @@
+// src/safety.rs
+use defmt::info;
+use embassy_time::Duration;
+
+// ISR RX ring capacity = RX_BUF len
+const ISR_RX_BUF_CAP: usize = 256;
+// Yield 1/2 the time it takes to fill ISR RX ring.
+const YIELD_MARGIN_NUM: u32 = 1;
+const YIELD_MARGIN_DEN: u32 = 2;
+// Ensure RX_PIPE_CAP can hold this.
+const WORST_MAIN_LATENCY_MS: u32 = 20;
+
+pub const TX_PIPE_CAP: usize = 1024;
+pub const RX_PIPE_CAP: usize = 1024;
+
+
+
+/// Perform safety checks and compute yield timing to avoid buffer overflow.
+///
+/// # Panics
+/// Panics if pipe capacities are too small for the configured baud.
+pub fn preflight_and_suggest_yield_period(baud: u32) -> Duration {
+    // Approx bytes per second for 8N1 (10 bits per byte on the wire)
+    let bytes_per_sec = (baud / 10).max(1);
+
+    // Time until ISR RX ring fills, in microseconds.
+    let t_fill_us = (ISR_RX_BUF_CAP as u64) * 1_000_000u64 / (bytes_per_sec as u64);
+
+    // Choose a yield period as a fraction of t_fill.
+    let yield_us = (t_fill_us as u64)
+        .saturating_mul(YIELD_MARGIN_NUM as u64)
+        / (YIELD_MARGIN_DEN as u64);
+
+    // Verify RX pipe can absorb a worst-case app latency so uart_task
+    // can always forward without dropping when it runs.
+    let required_rx_pipe = (bytes_per_sec as u64) * (WORST_MAIN_LATENCY_MS as u64) / 1000;
+
+    if (RX_PIPE_CAP as u64) < required_rx_pipe {
+        core::panic!(
+            "RX pipe too small: have {}B, need >= {}B for {}ms at {} bps",
+            RX_PIPE_CAP, required_rx_pipe, WORST_MAIN_LATENCY_MS, baud
+        );
+    }
+
+    info!(
+        "Preflight: baud={}, rx_isr={}B, rx_pipe={}B, bytes/s={}, t_fill_us={}, yield_us={}",
+        baud,
+        ISR_RX_BUF_CAP,
+        RX_PIPE_CAP,
+        bytes_per_sec,
+        t_fill_us,
+        yield_us
+    );
+
+    // Never choose zero.
+    Duration::from_micros(yield_us.max(1) as u64)
+}
--- a/semestralka_1b_rx/src/hw_uart_pc/usart1.rs
+++ b/semestralka_1b_rx/src/hw_uart_pc/usart1.rs
@@ -0,0 +1,12 @@
+// src/uart/usart1.rs
+use defmt::info;
+use embassy_time::Duration;
+
+use crate::hw_uart_pc::safety::preflight_and_suggest_yield_period;
+
+pub fn setup_and_spawn(baudrate: u32,) -> Duration {
+    let yield_period: Duration = preflight_and_suggest_yield_period(baudrate);
+    info!("HW USART1 safe");
+
+    yield_period
+}
--- a/semestralka_1b_rx/src/lib.rs
+++ b/semestralka_1b_rx/src/lib.rs
@@ -0,0 +1,6 @@
+#![no_std]
+
+pub mod software_uart;
+pub mod config;
+pub mod hw_uart_pc;
+pub mod hw_uart_internal;
--- a/semestralka_1b_rx/src/software_uart/debug.rs
+++ b/semestralka_1b_rx/src/software_uart/debug.rs
@@ -0,0 +1,43 @@
+// src/software_uart/debug.rs
+use defmt::info;
+
+pub fn dump_tim6_regs() {
+    use embassy_stm32::pac::timer::TimBasic;
+    let tim = unsafe { TimBasic::from_ptr(0x4000_1000usize as _) };
+    let sr = tim.sr().read();
+    let dier = tim.dier().read();
+    let cr1 = tim.cr1().read();
+    let arr = tim.arr().read().arr();
+    let psc = tim.psc().read();
+    info!(
+        "TIM6: CR1.CEN={} DIER.UDE={} SR.UIF={} PSC={} ARR={}",
+        cr1.cen(),
+        dier.ude(),
+        sr.uif(),
+        psc,
+        arr
+    );
+}
+
+pub fn dump_dma_ch0_regs() {
+    use embassy_stm32::pac::gpdma::Gpdma;
+    let dma = unsafe { Gpdma::from_ptr(0x4002_0000usize as _) };
+    let ch = dma.ch(0);
+    let cr = ch.cr().read();
+    let tr1 = ch.tr1().read();
+    let tr2 = ch.tr2().read();
+    let br1 = ch.br1().read();
+    info!(
+        "GPDMA1_CH0: EN={} PRIO={} SDW={} DDW={} SINC={} DINC={} REQSEL={} SWREQ={} DREQ={} BNDT={}",
+        cr.en(),
+        cr.prio(),
+        tr1.sdw(),
+        tr1.ddw(),
+        tr1.sinc(),
+        tr1.dinc(),
+        tr2.reqsel(),
+        tr2.swreq(),
+        tr2.dreq(),
+        br1.bndt()
+    );
+}
--- a/semestralka_1b_rx/src/software_uart/dma_timer.rs
+++ b/semestralka_1b_rx/src/software_uart/dma_timer.rs
@@ -0,0 +1,58 @@
+// src/dma_timer.rs
+
+use embassy_stm32::{
+    peripherals::{TIM6, TIM7},
+    rcc,
+    timer::low_level::Timer,
+    Peri,
+};
+use core::mem;
+use embassy_stm32::timer::BasicInstance;
+use embassy_stm32::pac::timer::vals::Urs;
+
+/// Initializes TIM6 to tick at `baud * oversample` frequency.
+/// Each TIM6 update event triggers one DMA beat.
+pub fn init_tim6_for_uart<'d>(tim6: Peri<'d, TIM6>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM6>();
+    let ll = Timer::new(tim6);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+/// Initializes TIM7 to tick at `baud * oversample` frequency.
+/// Each TIM7 update event triggers one DMA beat.
+pub fn init_tim7_for_uart<'d>(tim7: Peri<'d, TIM7>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM7>();
+    let ll = Timer::new(tim7);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+// Shared internal helper — identical CR1/ARR setup
+fn configure_basic_timer<T: BasicInstance>(ll: &Timer<'_, T>, baud: u32, oversample: u16) {
+    let f_timer = rcc::frequency::<T>().0;
+    let target = baud.saturating_mul(oversample.max(1) as u32).max(1);
+
+    // Compute ARR (prescaler = 0)
+    let mut arr = (f_timer / target).saturating_sub(1) as u16;
+    if arr == 0 { arr = 1; }
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_cen(false);
+        w.set_opm(false);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+
+    ll.regs_basic().psc().write_value(0u16);
+    ll.regs_basic().arr().write(|w| w.set_arr(arr));
+    ll.regs_basic().dier().modify(|w| w.set_ude(true));
+    ll.regs_basic().egr().write(|w| w.set_ug(true));
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_opm(false);
+        w.set_cen(true);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+}
--- a/semestralka_1b_rx/src/software_uart/gpio_dma_uart_rx.rs
+++ b/semestralka_1b_rx/src/software_uart/gpio_dma_uart_rx.rs
@@ -0,0 +1,80 @@
+// src/software_uart/runtime.rs
+use embassy_executor::task;
+use embassy_stm32::{
+    dma::Request,
+    peripherals::GPDMA1_CH1,
+    Peri,
+};
+use crate::config::RX_PIN_BIT;
+use embassy_stm32::dma::{
+    ReadableRingBuffer,
+    TransferOptions,
+};
+use crate::config::{RX_OVERSAMPLE, UART_CFG};
+use crate::software_uart::decode_uart_samples;
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use embassy_futures::yield_now;
+use defmt::info;
+
+// datasheet tabulka 137
+pub const TIM7_UP_REQ: Request = 5;
+
+/// RX DMA task: reads GPIO samples paced by TIM7 and fills PIPE_RX
+#[task]
+pub async fn rx_dma_task(
+    ch: Peri<'static, GPDMA1_CH1>,
+    register: *mut u8,
+    ring: &'static mut [u8],
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut opts = TransferOptions::default();
+    opts.half_transfer_ir = true;
+    opts.complete_transfer_ir = true;
+
+    // SAFETY: ring is exclusive to this task
+    let mut rx = unsafe { ReadableRingBuffer::new(ch, TIM7_UP_REQ, register, ring, opts) };
+    rx.start();
+
+    let mut raw_chunk = [0u8; 256];
+    let mut levels = [0u8; 256];
+    let mut last_bytes: [u8; 16] = [0; 16];   // remember previous 16 samples
+    let mut last_value: u8 = 0;              // remember previous single IDR sample (optional)
+
+    loop {
+        let _ = rx.read_exact(&mut raw_chunk).await;
+
+        // If nothing has changed (all bytes same as previous), skip logging
+        if raw_chunk[..16] == last_bytes[..] {
+            continue;
+        }
+
+        // Save for next comparison
+        last_bytes.copy_from_slice(&raw_chunk[..16]);
+        let current_avg = raw_chunk[0];
+
+        // Optionally only if single sample changed
+        if current_avg != last_value {
+            last_value = current_avg;
+
+            info!(
+                "DMA change detected: IDR[0..16]={=[u8]:02X} bit{}={}",
+                &raw_chunk[..16],
+                RX_PIN_BIT,
+                (current_avg >> RX_PIN_BIT) & 1
+            );
+        }
+
+        // Extract logic levels as before
+        for (i, b) in raw_chunk.iter().enumerate() {
+            levels[i] = ((*b >> RX_PIN_BIT) & 1) as u8;
+        }
+
+        let decoded = decode_uart_samples(&levels, RX_OVERSAMPLE, &UART_CFG);
+        if !decoded.is_empty() {
+            info!("SW RX decoded {:a}", decoded.as_slice());
+            pipe_rx.write(&decoded).await;
+        }
+
+        yield_now().await;
+    }
+}
--- a/semestralka_1b_rx/src/software_uart/gpio_dma_uart_tx.rs
+++ b/semestralka_1b_rx/src/software_uart/gpio_dma_uart_tx.rs
@@ -0,0 +1,84 @@
+// src/software_uart/gpio_dma_uart_tx.rs
+use embassy_executor::task;
+use embassy_stm32::{
+    dma::{Request, TransferOptions, WritableRingBuffer},
+    peripherals::GPDMA1_CH0,
+    Peri,
+};
+use embassy_futures::yield_now;
+use defmt::info;
+
+use embassy_sync::pipe::Pipe;
+use crate::config::{TX_PIN_BIT, UART_CFG};
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use crate::software_uart::uart_emulation::encode_uart_byte_cfg;
+
+pub const TIM6_UP_REQ: Request = 4;
+
+pub async fn encode_uart_frames<'a>(
+    pin_bit: u8,
+    bytes: &[u8],
+    out_buf: &'a mut [u32],
+) -> usize {
+    let mut offset = 0;
+    for &b in bytes {
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(pin_bit, b, &UART_CFG, &mut frame);
+
+        if offset + used <= out_buf.len() {
+            out_buf[offset..offset + used].copy_from_slice(&frame[..used]);
+            offset += used;
+        } else {
+            break;
+        }
+
+        // cooperative async yield
+        yield_now().await;
+    }
+    offset
+}
+
+/// TX DMA task: encodes UART frames and sends them via DMA at TIM6 rate
+#[task]
+pub async fn tx_dma_task(
+    ch: Peri<'static, GPDMA1_CH0>,
+    register: *mut u32, // Either odr or bsrr
+    tx_ring_mem: &'static mut [u32],
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut tx_opts = TransferOptions::default();
+    tx_opts.half_transfer_ir = true;
+    tx_opts.complete_transfer_ir = true;
+
+    // SAFETY: tx_ring is exclusive to this task
+    let mut tx_ring = unsafe {
+        WritableRingBuffer::new(
+            ch,
+            TIM6_UP_REQ,
+            register,
+            tx_ring_mem,
+            tx_opts,
+        )
+    };
+
+    tx_ring.start();
+    info!("TX DMA ring started");
+
+    let mut frame_buf = [0u32; 4096];
+    let mut rx_buf = [0u8; 256];
+
+    loop {
+        let n = pipe_rx.read(&mut rx_buf).await;
+        if n == 0 {
+            yield_now().await;
+            continue;
+        }
+
+        let used = encode_uart_frames(TX_PIN_BIT, &rx_buf[..n], &mut frame_buf).await;
+        if used > 0 {
+            let _ = tx_ring.write_exact(&frame_buf[..used]).await;
+        }
+        info!("tx_dma_task wrote {} words", used);
+        yield_now().await;
+    }
+}
--- a/semestralka_1b_rx/src/software_uart/mod.rs
+++ b/semestralka_1b_rx/src/software_uart/mod.rs
@@ -0,0 +1,13 @@
+// src/software_uart/mod.rs
+
+pub mod gpio_dma_uart_tx;
+pub mod gpio_dma_uart_rx;
+pub mod dma_timer;
+pub mod uart_emulation;
+pub mod debug;
+
+pub use gpio_dma_uart_tx::*;
+pub use gpio_dma_uart_rx::*;
+pub use dma_timer::*;
+pub use uart_emulation::*;
+pub use debug::*;
--- a/semestralka_1b_rx/src/software_uart/uart_emulation.rs
+++ b/semestralka_1b_rx/src/software_uart/uart_emulation.rs
@@ -0,0 +1,151 @@
+// src/software_uart/uart_emulation.rs
+use heapless::Vec;
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Parity {
+    None,
+    Even,
+    Odd,
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum StopBits {
+    One,
+    Two,
+}
+
+#[derive(Clone, Copy, Debug)]
+pub struct UartConfig {
+    pub data_bits: u8,
+    pub parity: Parity,
+    pub stop_bits: StopBits,
+}
+
+impl Default for UartConfig {
+    fn default() -> Self {
+        Self {
+            data_bits: 8,
+            parity: Parity::None,
+            stop_bits: StopBits::One,
+        }
+    }
+}
+
+/// Encodes one byte into a sequence of GPIO BSRR words
+pub fn encode_uart_byte_cfg(
+    pin_bit: u8,
+    data: u8,
+    cfg: &UartConfig,
+    out: &mut [u32; 12],
+) -> usize {
+    // GPIOx_BSRR register str. 636 kap. 13.4.7
+    let set_high = |bit: u8| -> u32 { 1u32 << bit };
+    // let set_low = |bit: u8| -> u32 { 0 }; // ODR
+    let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) }; // BSRR
+
+    let mut idx = 0usize;
+
+    // START bit (LOW)
+    out[idx] = set_low(pin_bit);
+    idx += 1;
+
+    // Data bits, LSB-first
+    let nbits = cfg.data_bits.clamp(5, 8);
+    for i in 0..nbits {
+        let one = ((data >> i) & 1) != 0;
+        out[idx] = if one { set_high(pin_bit) } else { set_low(pin_bit) };
+        idx += 1;
+    }
+
+    // Parity
+    match cfg.parity {
+        Parity::None => {}
+        Parity::Even | Parity::Odd => {
+            let mask: u8 = if nbits == 8 { 0xFF } else { (1u16 << nbits) as u8 - 1 };
+            let ones = (data & mask).count_ones() & 1;
+            let par_bit_is_one = match cfg.parity {
+                Parity::Even => ones == 1,
+                Parity::Odd => ones == 0,
+                _ => false,
+            };
+            out[idx] = if par_bit_is_one {
+                set_high(pin_bit)
+            } else {
+                set_low(pin_bit)
+            };
+            idx += 1;
+        }
+    }
+
+    // STOP bits (HIGH)
+    let stop_ticks = match cfg.stop_bits {
+        StopBits::One => 1usize,
+        StopBits::Two => 2usize,
+    };
+    for _ in 0..stop_ticks {
+        out[idx] = set_high(pin_bit);
+        idx += 1;
+    }
+
+    idx
+}
+
+/// Decode an oversampled stream of logic levels into UART bytes.
+pub fn decode_uart_samples(
+    samples: &[u8],
+    oversample: u16,
+    cfg: &UartConfig,
+) -> heapless::Vec<u8, 256> {
+
+    let mut out = Vec::<u8, 256>::new();
+    let mut idx = 0usize;
+    let nbits = cfg.data_bits as usize;
+
+    while idx + (oversample as usize * (nbits + 3)) < samples.len() {
+        // Wait for start bit (falling edge: high -> low)
+        if samples[idx] != 0 && samples[idx + 1] == 0 {
+            // Align to middle of start bit
+            idx += (oversample / 2) as usize;
+
+            // Sanity check start bit really low
+            if samples.get(idx).copied().unwrap_or(1) != 0 {
+                idx += 1;
+                continue;
+            }
+
+            // Sample data bits
+            let mut data: u8 = 0;
+            for bit in 0..nbits {
+                idx += oversample as usize;
+                let bit_val = samples
+                    .get(idx)
+                    .map(|&b| if b != 0 { 1u8 } else { 0u8 })
+                    .unwrap_or(1);
+                data |= bit_val << bit;
+            }
+
+            // Parity: skip / verify
+            match cfg.parity {
+                Parity::None => {}
+                Parity::Even | Parity::Odd => {
+                    idx += oversample as usize;
+                    // You can optionally add parity check here if needed
+                }
+            }
+
+            // Move past stop bits
+            let stop_skip = match cfg.stop_bits {
+                StopBits::One => oversample as usize,
+                StopBits::Two => (oversample * 2) as usize,
+            };
+            idx += stop_skip;
+
+            // Push decoded byte
+            let _ = out.push(data);
+        } else {
+            idx += 1;
+        }
+    }
+
+    out
+}
--- a/semestralka_1b_rx/tests/uart_emulation.rs
+++ b/semestralka_1b_rx/tests/uart_emulation.rs
@@ -0,0 +1,41 @@
+#![no_std]
+#![no_main]
+
+use dma_gpio as _;
+use panic_probe as _;
+use defmt_rtt as _;
+
+#[defmt_test::tests]
+mod tests {
+    use defmt::assert_eq;
+    use dma_gpio::software_uart::uart_emulation::{
+        encode_uart_byte_cfg, UartConfig, Parity, StopBits
+    };
+
+    const TX_PIN_BIT: u8 = 2;
+
+    #[test]
+    fn test_encode_8n1() {
+        let cfg = UartConfig::default();
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(TX_PIN_BIT, 0x55, &cfg, &mut frame);
+        
+        assert_eq!(used, 10);
+        assert_eq!(frame[0], 1u32 << 18); // Start LOW
+        assert_eq!(frame[9], 1u32 << 2);  // Stop HIGH
+    }
+
+    #[test]
+    fn test_encode_parity() {
+        let cfg = UartConfig {
+            data_bits: 8,
+            parity: Parity::Even,
+            stop_bits: StopBits::One,
+        };
+        
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(TX_PIN_BIT, 0x00, &cfg, &mut frame);
+        
+        assert_eq!(used, 11);
+    }
+}
--- a/semestralka_1c_tx/.cargo/config.toml
+++ b/semestralka_1c_tx/.cargo/config.toml
@@ -0,0 +1,15 @@
+[build]
+target = "thumbv8m.main-none-eabihf"
+
+[target.thumbv8m.main-none-eabihf]
+runner = "probe-rs run --chip STM32U575ZITxQ"
+
+rustflags = [
+  "-C", "linker=rust-lld",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "link-arg=-Tdefmt.x",
+  "-C", "link-arg=--nmagic",
+]
+
+[package.metadata.cargo-flash]
+chip = "STM32U575ZIT"
--- a/semestralka_1c_tx/.gitignore
+++ b/semestralka_1c_tx/.gitignore
@@ -0,0 +1 @@
+/target
--- a/semestralka_1c_tx/Cargo.lock
+++ b/semestralka_1c_tx/Cargo.lock
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Priec	179bec6ed6	finished and fully functional	2025-11-19 23:30:55 +01:00
Priec	8e1c2ec29f	time to do final merge	2025-11-19 21:46:07 +01:00
Priec	e569fbc39d	dma used to transfer Tx	2025-11-19 21:41:08 +01:00
Priec	24d1da44aa	working at the baud rate 600	2025-11-19 21:12:41 +01:00
Priec	ef56483016	improved parsing of software uart	2025-11-19 20:40:13 +01:00
Priec	de4e04787b	max frequency fixed it all	2025-11-19 20:28:24 +01:00
Priec	78c85c7982	tweaked parameters, storing before increasing frequencies	2025-11-19 19:43:10 +01:00
Priec	bf34ff1bcb	faster and smarter DMA	2025-11-19 18:48:09 +01:00
Priec	e2378cd436	working with DMA at 9600	2025-11-19 18:32:18 +01:00
Priec	110ddc0dcf	working, overhead is down a bit	2025-11-19 17:50:33 +01:00
Priec	0cd40eb5e2	uart rx working fully	2025-11-19 15:59:14 +01:00
Priec	46486a6e74	working data catch	2025-11-19 14:51:42 +01:00
Priec	89ee552da3	working only at 600 baud, we are reading data of the pin in the interrupt	2025-11-19 14:41:39 +01:00
Priec	28d041873c	starting fresh again 1d rx bez dma	2025-11-19 13:03:28 +01:00
Priec	2ef75c319d	working buffer transfer, lets build from in here	2025-11-19 12:56:47 +01:00
Priec	da2f011682	1d needs to be builded again from scratch	2025-11-19 12:51:45 +01:00
Priec	b339b34e4d	toggling bit and reading it now works properly well	2025-11-19 12:11:19 +01:00
Priec	9c26a0ca81	not working interrupt via tim7 to read data	2025-11-19 11:57:28 +01:00
Priec	c5bee53a30	toggle in the interrupt is working	2025-11-19 11:39:55 +01:00
Priec	7a8a308620	now im reading proper buffer	2025-11-18 23:23:33 +01:00
Priec	516309aed2	proper printing of the pipe_int tx_pipe	2025-11-18 22:56:28 +01:00
Filipriec	45df1e87e4	testing, not owrking 1d yet	2025-11-18 19:39:51 +01:00
Filipriec	0a0ff0f38a	debugging more	2025-11-18 16:55:42 +01:00
Filipriec	1909497403	hopefuly working CPU transfer to bsrr	2025-11-18 13:36:07 +01:00
Priec	c01a908b25	cpu polling instead of dma	2025-11-18 10:29:29 +01:00
Priec	c0bc36bec2	rx bez dma ready for testing	2025-11-18 10:12:02 +01:00
Priec	66c4741afa	blbosti	2025-11-18 09:20:57 +01:00
Priec	fa343624e7	tx stale nefunguje	2025-11-12 23:37:32 +01:00
Priec	66521896b3	moving things around, time to debug crap out of it	2025-11-12 19:07:00 +01:00
Priec	a0c30894ee	better registers for Rx	2025-11-12 18:54:42 +01:00
Priec	16c66ee1ff	final debug	2025-11-12 18:22:07 +01:00
Priec	8c6f703de9	bridge between usart1 and usart2	2025-11-12 17:33:34 +01:00
Priec	05662a45d0	there is some bug	2025-11-12 16:07:59 +01:00
Priec	829cff872f	using correct pipes now	2025-11-12 14:15:33 +01:00
Priec	2fb198ceb8	fully built, time to make it work	2025-11-12 13:03:17 +01:00
Priec	2a97cbbd38	forgotten	2025-11-11 23:34:48 +01:00
Priec	a35d1df67f	small naming conventions	2025-11-11 23:30:03 +01:00
Priec	c1d0fa9d04	i can read HW uart in the terminal via info	2025-11-11 22:34:16 +01:00
Priec	347d10fb27	priec - filip user	2025-11-11 22:08:59 +01:00
Filipriec	19536dde78	compiled hw and sw uart in semestralka	2025-11-11 21:39:46 +01:00
Filipriec	17c205f23b	adding hardware uart	2025-11-11 17:16:18 +01:00
Filipriec	c738fabac7	software rx and tx are now using data, transmitting on the Tx and receiving on the Rx side	2025-11-11 16:15:59 +01:00
Filipriec	bc68e30ead	its a separate task now	2025-11-11 16:03:46 +01:00
Filipriec	541173bfcb	semestralka joinig all worlds together	2025-11-11 15:51:37 +01:00
Filipriec	25c6d3d265	restored Rx ring properly well with the dma_gpio2 initialized	2025-11-10 18:11:28 +01:00
Filipriec	f4e59d977b	revert this commit its only to make it work on the notebook	2025-11-10 17:40:23 +01:00
				`@@ -1 +0,0 @@`
				`https://www.ti.com/lit/ug/sprugp1/sprugp1.pdf?ts=1761641486453`