Priec
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9451bc5ae9
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timer HAL
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2025-11-23 21:44:01 +01:00 |
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Priec
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e5e4d13ff6
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prod1
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2025-11-23 21:02:36 +01:00 |
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Priec
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d0ddea119d
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Add global target ignore
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2025-11-23 16:24:28 +01:00 |
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Priec
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348c4e63d9
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library now fully functional and working
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2025-11-23 16:01:01 +01:00 |
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Priec
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3218714d8c
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software uart lib errors fixed
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2025-11-23 15:54:20 +01:00 |
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Priec
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4097ce1c7a
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software uart is now a library
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2025-11-23 15:48:54 +01:00 |
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Priec
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685067a75f
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jsut minor changes, UNTESTED DMA TIMER CHANGE
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2025-11-20 13:28:09 +01:00 |
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Priec
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179bec6ed6
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finished and fully functional
v1.9.0
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2025-11-19 23:30:55 +01:00 |
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Priec
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8e1c2ec29f
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time to do final merge
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2025-11-19 21:46:07 +01:00 |
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Priec
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e569fbc39d
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dma used to transfer Tx
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2025-11-19 21:41:08 +01:00 |
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Priec
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24d1da44aa
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working at the baud rate 600
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2025-11-19 21:12:41 +01:00 |
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Priec
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ef56483016
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improved parsing of software uart
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2025-11-19 20:40:13 +01:00 |
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Priec
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de4e04787b
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max frequency fixed it all
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2025-11-19 20:28:24 +01:00 |
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Priec
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78c85c7982
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tweaked parameters, storing before increasing frequencies
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2025-11-19 19:43:10 +01:00 |
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Priec
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bf34ff1bcb
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faster and smarter DMA
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2025-11-19 18:48:09 +01:00 |
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Priec
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e2378cd436
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working with DMA at 9600
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2025-11-19 18:32:18 +01:00 |
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Priec
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110ddc0dcf
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working, overhead is down a bit
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2025-11-19 17:50:33 +01:00 |
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Priec
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0cd40eb5e2
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uart rx working fully
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2025-11-19 15:59:14 +01:00 |
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Priec
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46486a6e74
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working data catch
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2025-11-19 14:51:42 +01:00 |
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Priec
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89ee552da3
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working only at 600 baud, we are reading data of the pin in the interrupt
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2025-11-19 14:41:39 +01:00 |
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Priec
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28d041873c
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starting fresh again 1d rx bez dma
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2025-11-19 13:03:28 +01:00 |
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Priec
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2ef75c319d
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working buffer transfer, lets build from in here
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2025-11-19 12:56:47 +01:00 |
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Priec
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da2f011682
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1d needs to be builded again from scratch
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2025-11-19 12:51:45 +01:00 |
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Priec
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b339b34e4d
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toggling bit and reading it now works properly well
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2025-11-19 12:11:19 +01:00 |
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Priec
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9c26a0ca81
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not working interrupt via tim7 to read data
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2025-11-19 11:57:28 +01:00 |
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Priec
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c5bee53a30
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toggle in the interrupt is working
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2025-11-19 11:39:55 +01:00 |
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Priec
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7a8a308620
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now im reading proper buffer
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2025-11-18 23:23:33 +01:00 |
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Priec
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516309aed2
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proper printing of the pipe_int tx_pipe
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2025-11-18 22:56:28 +01:00 |
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Filipriec
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45df1e87e4
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testing, not owrking 1d yet
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2025-11-18 19:39:51 +01:00 |
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Filipriec
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0a0ff0f38a
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debugging more
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2025-11-18 16:55:42 +01:00 |
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Filipriec
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1909497403
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hopefuly working CPU transfer to bsrr
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2025-11-18 13:36:07 +01:00 |
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Priec
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c01a908b25
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cpu polling instead of dma
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2025-11-18 10:29:29 +01:00 |
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Priec
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c0bc36bec2
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rx bez dma ready for testing
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2025-11-18 10:12:02 +01:00 |
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Priec
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66c4741afa
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blbosti
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2025-11-18 09:20:57 +01:00 |
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Priec
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fa343624e7
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tx stale nefunguje
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2025-11-12 23:37:32 +01:00 |
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Priec
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66521896b3
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moving things around, time to debug crap out of it
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2025-11-12 19:07:00 +01:00 |
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Priec
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a0c30894ee
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better registers for Rx
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2025-11-12 18:54:42 +01:00 |
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Priec
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16c66ee1ff
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final debug
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2025-11-12 18:22:07 +01:00 |
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Priec
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8c6f703de9
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bridge between usart1 and usart2
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2025-11-12 17:33:34 +01:00 |
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Priec
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05662a45d0
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there is some bug
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2025-11-12 16:07:59 +01:00 |
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Priec
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829cff872f
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using correct pipes now
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2025-11-12 14:15:33 +01:00 |
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Priec
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2fb198ceb8
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fully built, time to make it work
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2025-11-12 13:03:17 +01:00 |
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Priec
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2a97cbbd38
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forgotten
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2025-11-11 23:34:48 +01:00 |
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Priec
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a35d1df67f
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small naming conventions
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2025-11-11 23:30:03 +01:00 |
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Priec
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c1d0fa9d04
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i can read HW uart in the terminal via info
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2025-11-11 22:34:16 +01:00 |
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Priec
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347d10fb27
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priec - filip user
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2025-11-11 22:08:59 +01:00 |
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Filipriec
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19536dde78
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compiled hw and sw uart in semestralka
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2025-11-11 21:39:46 +01:00 |
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Filipriec
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17c205f23b
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adding hardware uart
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2025-11-11 17:16:18 +01:00 |
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Filipriec
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c738fabac7
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software rx and tx are now using data, transmitting on the Tx and receiving on the Rx side
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2025-11-11 16:15:59 +01:00 |
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Filipriec
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bc68e30ead
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its a separate task now
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2025-11-11 16:03:46 +01:00 |
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