Priec
|
110ddc0dcf
|
working, overhead is down a bit
|
2025-11-19 17:50:33 +01:00 |
|
Priec
|
0cd40eb5e2
|
uart rx working fully
|
2025-11-19 15:59:14 +01:00 |
|
Priec
|
46486a6e74
|
working data catch
|
2025-11-19 14:51:42 +01:00 |
|
Priec
|
89ee552da3
|
working only at 600 baud, we are reading data of the pin in the interrupt
|
2025-11-19 14:41:39 +01:00 |
|
Priec
|
28d041873c
|
starting fresh again 1d rx bez dma
|
2025-11-19 13:03:28 +01:00 |
|
Priec
|
2ef75c319d
|
working buffer transfer, lets build from in here
|
2025-11-19 12:56:47 +01:00 |
|
Priec
|
da2f011682
|
1d needs to be builded again from scratch
|
2025-11-19 12:51:45 +01:00 |
|
Priec
|
b339b34e4d
|
toggling bit and reading it now works properly well
|
2025-11-19 12:11:19 +01:00 |
|
Priec
|
9c26a0ca81
|
not working interrupt via tim7 to read data
|
2025-11-19 11:57:28 +01:00 |
|
Priec
|
c5bee53a30
|
toggle in the interrupt is working
|
2025-11-19 11:39:55 +01:00 |
|
Priec
|
7a8a308620
|
now im reading proper buffer
|
2025-11-18 23:23:33 +01:00 |
|
Priec
|
516309aed2
|
proper printing of the pipe_int tx_pipe
|
2025-11-18 22:56:28 +01:00 |
|
Filipriec
|
45df1e87e4
|
testing, not owrking 1d yet
|
2025-11-18 19:39:51 +01:00 |
|
Filipriec
|
0a0ff0f38a
|
debugging more
|
2025-11-18 16:55:42 +01:00 |
|
Filipriec
|
1909497403
|
hopefuly working CPU transfer to bsrr
|
2025-11-18 13:36:07 +01:00 |
|
Priec
|
c01a908b25
|
cpu polling instead of dma
|
2025-11-18 10:29:29 +01:00 |
|
Priec
|
c0bc36bec2
|
rx bez dma ready for testing
|
2025-11-18 10:12:02 +01:00 |
|
Priec
|
66c4741afa
|
blbosti
|
2025-11-18 09:20:57 +01:00 |
|
Priec
|
fa343624e7
|
tx stale nefunguje
|
2025-11-12 23:37:32 +01:00 |
|
Priec
|
66521896b3
|
moving things around, time to debug crap out of it
|
2025-11-12 19:07:00 +01:00 |
|
Priec
|
a0c30894ee
|
better registers for Rx
|
2025-11-12 18:54:42 +01:00 |
|
Priec
|
16c66ee1ff
|
final debug
|
2025-11-12 18:22:07 +01:00 |
|
Priec
|
8c6f703de9
|
bridge between usart1 and usart2
|
2025-11-12 17:33:34 +01:00 |
|
Priec
|
05662a45d0
|
there is some bug
|
2025-11-12 16:07:59 +01:00 |
|
Priec
|
829cff872f
|
using correct pipes now
|
2025-11-12 14:15:33 +01:00 |
|
Priec
|
2fb198ceb8
|
fully built, time to make it work
|
2025-11-12 13:03:17 +01:00 |
|
Priec
|
2a97cbbd38
|
forgotten
|
2025-11-11 23:34:48 +01:00 |
|
Priec
|
a35d1df67f
|
small naming conventions
|
2025-11-11 23:30:03 +01:00 |
|
Priec
|
c1d0fa9d04
|
i can read HW uart in the terminal via info
|
2025-11-11 22:34:16 +01:00 |
|
Priec
|
347d10fb27
|
priec - filip user
|
2025-11-11 22:08:59 +01:00 |
|
Filipriec
|
19536dde78
|
compiled hw and sw uart in semestralka
|
2025-11-11 21:39:46 +01:00 |
|
Filipriec
|
17c205f23b
|
adding hardware uart
|
2025-11-11 17:16:18 +01:00 |
|
Filipriec
|
c738fabac7
|
software rx and tx are now using data, transmitting on the Tx and receiving on the Rx side
|
2025-11-11 16:15:59 +01:00 |
|
Filipriec
|
bc68e30ead
|
its a separate task now
|
2025-11-11 16:03:46 +01:00 |
|
Filipriec
|
541173bfcb
|
semestralka joinig all worlds together
|
2025-11-11 15:51:37 +01:00 |
|
Filipriec
|
25c6d3d265
|
restored Rx ring properly well with the dma_gpio2 initialized
|
2025-11-10 18:11:28 +01:00 |
|
Filipriec
|
f4e59d977b
|
revert this commit its only to make it work on the notebook
|
2025-11-10 17:40:23 +01:00 |
|
Priec
|
fa6b217bc4
|
working with the dma library
|
2025-11-09 21:24:58 +01:00 |
|
Priec
|
ef98b7e4e9
|
fixing and working nonstop without timout
|
2025-11-09 19:29:49 +01:00 |
|
Priec
|
6620f9ad2b
|
working write immidiate
|
2025-11-07 21:23:31 +01:00 |
|
Priec
|
f2fda10c7a
|
Tx only does not work
not_working_dmaLLI_write_exact
|
2025-11-05 21:03:30 +01:00 |
|
Priec
|
f7fdd72d7f
|
timer stuff, yield now added, still hard fault error
|
2025-11-05 16:38:26 +01:00 |
|
Priec
|
41c31f6b2a
|
only improvements
|
2025-11-05 14:45:36 +01:00 |
|
Priec
|
d57d16935d
|
compiled, config in src/config, but i get hardfault crash at runtime
|
2025-11-05 09:44:41 +01:00 |
|
Filipriec
|
44f154e289
|
comment
|
2025-11-04 22:00:34 +01:00 |
|
Priec
|
92e27ad076
|
Last moves, comments and file organization
|
2025-11-03 23:26:39 +01:00 |
|
Priec
|
93c43dee11
|
redesigned, removed redundancy
|
2025-11-03 22:41:16 +01:00 |
|
Priec
|
096fe5e2b9
|
working now pushing to the ring buffer
|
2025-11-02 22:46:42 +01:00 |
|
Priec
|
fef7de2045
|
working, but data are in pipe, but we read ringbuffer, critical bug, fix now
|
2025-11-02 22:39:01 +01:00 |
|
Priec
|
15b3b96b68
|
compiled and working
v0.1.1b
|
2025-11-01 23:47:15 +01:00 |
|