Priec
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68d13ebbbc
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sram2 standby working
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2025-12-03 18:33:07 +01:00 |
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Priec
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434e2b3d21
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shutdown added
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2025-12-03 17:57:10 +01:00 |
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Priec
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33543099c2
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split the wakeup now, properly working
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2025-12-03 16:52:30 +01:00 |
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Priec
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9be1d514fb
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ready for feature based split
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2025-12-03 13:36:56 +01:00 |
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Priec
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9ab8f94f92
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standby from C HAL is working
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2025-12-03 13:05:13 +01:00 |
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Priec
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60d1ae9a45
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blinking working
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2025-12-03 11:40:19 +01:00 |
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Filipriec
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b44ede04cb
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not working, fix at home, init hal from C was removed
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2025-12-02 18:00:49 +01:00 |
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Filipriec
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ab932d1698
|
hal working
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2025-12-02 15:40:13 +01:00 |
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Filipriec
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af781eb1f8
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added C hal into the project successfuly
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2025-12-02 13:44:47 +01:00 |
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Priec
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f7063f877d
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working buffered hardware uart from previous project is now on
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2025-11-29 19:30:13 +01:00 |
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Priec
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9c7f67b071
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template for semestralka2
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2025-11-28 19:28:31 +01:00 |
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Filipriec
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6f27f98a38
|
final uml
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2025-11-25 17:45:39 +01:00 |
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Filipriec
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a61b808176
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finalized plantuml
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2025-11-25 15:19:06 +01:00 |
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Filipriec
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4ff73644c6
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uml
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2025-11-25 15:10:25 +01:00 |
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Filipriec
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f6d83a0acc
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updated lock file
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2025-11-25 07:56:51 +01:00 |
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Filipriec
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3e2ad6eb7d
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timing uml diagrams added
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2025-11-24 09:41:46 +01:00 |
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Priec
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6d694c840b
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cleanup
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2025-11-24 00:21:58 +01:00 |
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Priec
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522236e20c
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removed redundant code
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2025-11-23 23:12:32 +01:00 |
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Priec
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804dc66a4b
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sampling only in the middle
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2025-11-23 22:16:36 +01:00 |
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Priec
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9451bc5ae9
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timer HAL
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2025-11-23 21:44:01 +01:00 |
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Priec
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e5e4d13ff6
|
prod1
|
2025-11-23 21:02:36 +01:00 |
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Priec
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d0ddea119d
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Add global target ignore
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2025-11-23 16:24:28 +01:00 |
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Priec
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348c4e63d9
|
library now fully functional and working
|
2025-11-23 16:01:01 +01:00 |
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Priec
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3218714d8c
|
software uart lib errors fixed
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2025-11-23 15:54:20 +01:00 |
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Priec
|
4097ce1c7a
|
software uart is now a library
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2025-11-23 15:48:54 +01:00 |
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Priec
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685067a75f
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jsut minor changes, UNTESTED DMA TIMER CHANGE
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2025-11-20 13:28:09 +01:00 |
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Priec
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179bec6ed6
|
finished and fully functional
v1.9.0
|
2025-11-19 23:30:55 +01:00 |
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Priec
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8e1c2ec29f
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time to do final merge
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2025-11-19 21:46:07 +01:00 |
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Priec
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e569fbc39d
|
dma used to transfer Tx
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2025-11-19 21:41:08 +01:00 |
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Priec
|
24d1da44aa
|
working at the baud rate 600
|
2025-11-19 21:12:41 +01:00 |
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Priec
|
ef56483016
|
improved parsing of software uart
|
2025-11-19 20:40:13 +01:00 |
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Priec
|
de4e04787b
|
max frequency fixed it all
|
2025-11-19 20:28:24 +01:00 |
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Priec
|
78c85c7982
|
tweaked parameters, storing before increasing frequencies
|
2025-11-19 19:43:10 +01:00 |
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Priec
|
bf34ff1bcb
|
faster and smarter DMA
|
2025-11-19 18:48:09 +01:00 |
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Priec
|
e2378cd436
|
working with DMA at 9600
|
2025-11-19 18:32:18 +01:00 |
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Priec
|
110ddc0dcf
|
working, overhead is down a bit
|
2025-11-19 17:50:33 +01:00 |
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Priec
|
0cd40eb5e2
|
uart rx working fully
|
2025-11-19 15:59:14 +01:00 |
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Priec
|
46486a6e74
|
working data catch
|
2025-11-19 14:51:42 +01:00 |
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Priec
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89ee552da3
|
working only at 600 baud, we are reading data of the pin in the interrupt
|
2025-11-19 14:41:39 +01:00 |
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Priec
|
28d041873c
|
starting fresh again 1d rx bez dma
|
2025-11-19 13:03:28 +01:00 |
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Priec
|
2ef75c319d
|
working buffer transfer, lets build from in here
|
2025-11-19 12:56:47 +01:00 |
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Priec
|
da2f011682
|
1d needs to be builded again from scratch
|
2025-11-19 12:51:45 +01:00 |
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Priec
|
b339b34e4d
|
toggling bit and reading it now works properly well
|
2025-11-19 12:11:19 +01:00 |
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Priec
|
9c26a0ca81
|
not working interrupt via tim7 to read data
|
2025-11-19 11:57:28 +01:00 |
|
Priec
|
c5bee53a30
|
toggle in the interrupt is working
|
2025-11-19 11:39:55 +01:00 |
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Priec
|
7a8a308620
|
now im reading proper buffer
|
2025-11-18 23:23:33 +01:00 |
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Priec
|
516309aed2
|
proper printing of the pipe_int tx_pipe
|
2025-11-18 22:56:28 +01:00 |
|
Filipriec
|
45df1e87e4
|
testing, not owrking 1d yet
|
2025-11-18 19:39:51 +01:00 |
|
Filipriec
|
0a0ff0f38a
|
debugging more
|
2025-11-18 16:55:42 +01:00 |
|
Filipriec
|
1909497403
|
hopefuly working CPU transfer to bsrr
|
2025-11-18 13:36:07 +01:00 |
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