77 lines
2.1 KiB
VHDL
77 lines
2.1 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 09.03.2026 15:14:35
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-- Design Name:
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-- Module Name: counter - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity counter is
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Generic ( MAX_LIMIT : STD_LOGIC_VECTOR(3 downto 0) := "1001" ); -- Default to 9
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Port ( CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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CE : in STD_LOGIC;
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PE : in STD_LOGIC;
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DIN : in STD_LOGIC_VECTOR(3 downto 0);
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TC : out STD_LOGIC;
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COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
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end counter;
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architecture Behavioral of counter is
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-- Internal signal to keep track of the current number
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signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
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begin
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-- Main counting logic
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process(CLK)
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begin
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if rising_edge(CLK) then
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if RST = '1' then
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s_cnt <= "0000";
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TC <= '0'; -- Reset TC
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elsif PE = '1' then
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s_cnt <= DIN;
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TC <= '0';
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elsif CE = '1' then
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if s_cnt = MAX_LIMIT then
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s_cnt <= "0000"; -- Reset to 0 when limit is hit
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TC <= '1';
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else
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s_cnt <= s_cnt + 1; -- Otherwise increment
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TC <= '0';
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end if;
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else
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TC <= '0';
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end if;
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end if;
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end process;
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COUNT_OUT <= s_cnt;
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end Behavioral; |