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-- Company: 
-- Engineer: 
-- 
-- Create Date: 09.03.2026 15:14:35
-- Design Name: 
-- Module Name: counter - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter is
    Generic ( MAX_LIMIT : STD_LOGIC_VECTOR(3 downto 0) := "1001" ); -- Default to 9
    Port ( CLK : in STD_LOGIC;
           RST : in STD_LOGIC;
           CE : in STD_LOGIC;
           PE : in  STD_LOGIC;
           DIN : in  STD_LOGIC_VECTOR(3 downto 0); 
           TC : out STD_LOGIC;
           COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end counter;

architecture Behavioral of counter is
    -- Internal signal to keep track of the current number
    signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin

    -- Main counting logic
    process(CLK)
    begin
        if rising_edge(CLK) then
            if RST = '1' then
                s_cnt <= "0000";
                TC    <= '0'; -- Reset TC
            elsif PE = '1' then
                s_cnt <= DIN;
                TC    <= '0';
            elsif CE = '1' then
                if s_cnt = MAX_LIMIT then
                    s_cnt <= "0000";   -- Reset to 0 when limit is hit
                    TC    <= '1';
                else
                    s_cnt <= s_cnt + 1; -- Otherwise increment
                    TC    <= '0';
                end if;
            else
                TC <= '0';
            end if;
        end if;
    end process;

    COUNT_OUT <= s_cnt;

end Behavioral;