filipriec/FPGA---VHDL
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Filipriec 93c5b504fb counting up to 9999 now
2026-03-16 16:12:29 +01:00
project_1
working z predoslych hodin
2026-03-09 14:04:31 +01:00
project_2
working z predoslych hodin
2026-03-09 14:04:31 +01:00
project_3_nzio
working z predoslych hodin
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project_4
nakreslene zadanie
2026-03-09 14:05:17 +01:00
project_5
hotovy priklad 5 funguje uplne bez problemov
2026-03-09 17:03:42 +01:00
project_6/project_6.srcs
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.gitignore
working z predoslych hodin
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Description
To co sme robili v skole
1.3 MiB
Languages
Tcl 54.4%
VHDL 45.6%