Compare commits
3 Commits
| Author | SHA1 | Date | |
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dd7d083112 | ||
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93c5b504fb | ||
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6af72b448a |
117
project_6/proj.mermaid
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117
project_6/proj.mermaid
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flowchart TD
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%% ── External ports ──────────────────────────────────────────
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CLK([CLK])
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RST([RST])
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START([START])
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SEGMENTS([SEGMENTS\nout])
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ANODS([ANODS\nout])
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%% ════════════════════════════════════════════════════════════
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%% FILE: divider.vhd
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%% ════════════════════════════════════════════════════════════
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subgraph FILE_DIV["📄 divider.vhd — entity: divider"]
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direction TB
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DIV["U_DIV\ndivider\n─────────────\nIN: CLK, RST\nOUT: CLK_1_Hz"]
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end
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%% ════════════════════════════════════════════════════════════
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%% FILE: divider_400Hz.vhd
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%% ════════════════════════════════════════════════════════════
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subgraph FILE_DIV400["📄 divider_400Hz.vhd — entity: divider_400Hz"]
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direction TB
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DIV400["U_DIV_400Hz\ndivider_400Hz\n─────────────\nIN: CLK, RST\nOUT: CLK_400_Hz"]
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end
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%% ════════════════════════════════════════════════════════════
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%% FILE: counter.vhd
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%% ════════════════════════════════════════════════════════════
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subgraph FILE_CNT["📄 counter.vhd — entity: counter (reused 4x)"]
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direction TB
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CNT_U["U_CNT_TOP\ncounter - Units\n─────────────\nIN: CLK, RST, CE\nOUT: COUNT_OUT, TC"]
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CNT_T["U_CNT_BOTTOM\ncounter - Tens\n─────────────\nIN: CLK, RST, CE\nOUT: COUNT_OUT, TC"]
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CNT_H["U_CNT_3\ncounter - Hundreds\n─────────────\nIN: CLK, RST, CE\nOUT: COUNT_OUT, TC"]
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CNT_K["U_CNT_4\ncounter - Thousands\n─────────────\nIN: CLK, RST, CE\nOUT: COUNT_OUT, TC=open"]
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end
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%% ════════════════════════════════════════════════════════════
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%% FILE: counter_2bit.vhd
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%% ════════════════════════════════════════════════════════════
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subgraph FILE_CNT2["📄 counter_2bit.vhd — entity: counter_2bit"]
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direction TB
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CNT2["U_CNT_2BIT\ncounter_2bit\n─────────────\nIN: CLK=clk_400Hz, RST\nOUT: COUNT_OUT 2-bit"]
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end
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%% ════════════════════════════════════════════════════════════
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%% FILE: decoder_bottom.vhd
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%% ════════════════════════════════════════════════════════════
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subgraph FILE_DEC_AN["📄 decoder_bottom.vhd — entity: decoder_an"]
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direction TB
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DEC_AN["U_DEC_ANODES\ndecoder_an\n─────────────\nIN: SEL 2-bit\nOUT: ANODES 4-bit"]
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end
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%% ════════════════════════════════════════════════════════════
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%% FILE: mux.vhd
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%% ════════════════════════════════════════════════════════════
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subgraph FILE_MUX["📄 mux.vhd — entity: mux"]
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direction TB
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MUX["U_MUX\nmux 4x4-bit\n─────────────\nIN: I0,I1,I2,I3, S 2-bit\nOUT: Y 4-bit"]
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end
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%% ════════════════════════════════════════════════════════════
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%% FILE: dec2.vhd
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%% ════════════════════════════════════════════════════════════
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subgraph FILE_DEC_SEG["📄 dec2.vhd — entity: dec_seg"]
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direction TB
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DEC_SEG["U_DEC_SEG\ndec_seg\n─────────────\nIN: BCD 4-bit\nOUT: SEG 8-bit"]
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end
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%% ════════════════════════════════════════════════════════════
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%% top_modul.vhd — glue logic defined directly in this file
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%% ════════════════════════════════════════════════════════════
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subgraph FILE_TOP["📄 top_modul.vhd — glue signals defined here"]
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direction TB
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AND_START{"s_ce_units\nclk_1_Hz AND START"}
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AND2{"CE for Hundreds\ns_tc_units AND s_tc_tens"}
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AND3{"CE for Thousands\ns_tc_units AND s_tc_tens\nAND s_tc_hundreds"}
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end
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%% ── Clock / Reset wiring ─────────────────────────────────────
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CLK --> DIV
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RST --> DIV
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CLK --> DIV400
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||||||
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RST --> DIV400
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||||||
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CLK --> CNT_U & CNT_T & CNT_H & CNT_K
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RST --> CNT_U & CNT_T & CNT_H & CNT_K & CNT2
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%% ── 1 Hz chain ───────────────────────────────────────────────
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DIV -->|"clk_1_Hz"| AND_START
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START --> AND_START
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AND_START -->|"s_ce_units (CE)"| CNT_U
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%% ── BCD carry chain ──────────────────────────────────────────
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CNT_U -->|"s_tc_units (TC->CE)"| CNT_T
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CNT_U -->|"s_tc_units"| AND2
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CNT_T -->|"s_tc_tens"| AND2
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AND2 -->|"CE"| CNT_H
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CNT_U -->|"s_tc_units"| AND3
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CNT_T -->|"s_tc_tens"| AND3
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CNT_H -->|"s_tc_hundreds"| AND3
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AND3 -->|"CE"| CNT_K
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%% ── 400 Hz display scan ──────────────────────────────────────
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||||||
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DIV400 -->|"clk_400_Hz"| CNT2
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CNT2 -->|"s_cnt_2bit (SEL)"| DEC_AN
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||||||
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CNT2 -->|"s_cnt_2bit (S)"| MUX
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||||||
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DEC_AN -->|"ANODES"| ANODS
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||||||
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%% ── MUX inputs from counters ─────────────────────────────────
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CNT_U -->|"s_cnt_units (I0)"| MUX
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CNT_T -->|"s_cnt_tens (I1)"| MUX
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CNT_H -->|"s_cnt_hundreds (I2)"| MUX
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||||||
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CNT_K -->|"s_cnt_thousands (I3)"| MUX
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%% ── Segment decode ───────────────────────────────────────────
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||||||
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MUX -->|"s_mux_out (BCD)"| DEC_SEG
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||||||
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DEC_SEG -->|"SEG"| SEGMENTS
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||||||
1
project_6/proj.mermaid.svg
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1
project_6/proj.mermaid.svg
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File diff suppressed because one or more lines are too long
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After Width: | Height: | Size: 281 KiB |
82
project_6/proj2.mermaid
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82
project_6/proj2.mermaid
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@@ -0,0 +1,82 @@
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flowchart LR
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||||||
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%% ── Inputs ───────────────────────────────────────────────────
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||||||
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CLK([CLK])
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||||||
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RST([RST])
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||||||
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START([START])
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||||||
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%% ── Outputs ──────────────────────────────────────────────────
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||||||
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SEGMENTS([SEGMENTS])
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ANODS([ANODS])
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||||||
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%% ── Clock dividers ───────────────────────────────────────────
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subgraph FILE_DIV["📄 divider.vhd"]
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DIV["divider\n──────────\n100MHz → 1Hz pulse"]
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||||||
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end
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||||||
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||||||
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subgraph FILE_DIV400["📄 divider_400Hz.vhd"]
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||||||
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DIV400["divider_400Hz\n──────────\n100MHz → 400Hz pulse"]
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||||||
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end
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||||||
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%% ── Glue in top_modul ────────────────────────────────────────
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AND_CE(["⚡ top_modul.vhd\ns_ce_units =\nclk_1_Hz AND START"])
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%% ── BCD counter chain ────────────────────────────────────────
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||||||
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subgraph FILE_CNT["📄 counter.vhd (entity reused 4×)"]
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||||||
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direction LR
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||||||
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CNT_U["U_CNT_TOP\n── Units ──\nCE=s_ce_units\nTC→s_tc_units"]
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||||||
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CNT_T["U_CNT_BOTTOM\n── Tens ──\nCE=s_tc_units\nTC→s_tc_tens"]
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||||||
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CNT_H["U_CNT_3\n── Hundreds ──\nCE=tc_u AND tc_t\nTC→s_tc_hundreds"]
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||||||
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CNT_K["U_CNT_4\n── Thousands ──\nCE=tc_u AND tc_t\n AND tc_h\nTC=open"]
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||||||
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||||||
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CNT_U -->|"s_tc_units"| CNT_T
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||||||
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CNT_T -->|"s_tc_tens"| CNT_H
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||||||
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CNT_H -->|"s_tc_hundreds"| CNT_K
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||||||
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end
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||||||
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||||||
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%% ── Display scan chain ───────────────────────────────────────
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||||||
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subgraph FILE_CNT2["📄 counter_2bit.vhd"]
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||||||
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CNT2["counter_2bit\n──────────\nIN: clk_400Hz\nOUT: s_cnt_2bit"]
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||||||
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end
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||||||
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||||||
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subgraph FILE_DEC_AN["📄 decoder_bottom.vhd"]
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||||||
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DEC_AN["decoder_an\n──────────\nIN: SEL 2-bit\nOUT: ANODES 4-bit"]
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||||||
|
end
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||||||
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||||||
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%% ── Mux + segment decode ─────────────────────────────────────
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||||||
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subgraph FILE_MUX["📄 mux.vhd"]
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||||||
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MUX["mux 4×4-bit\n──────────\nI0–I3: digit values\nS: s_cnt_2bit\nY: s_mux_out"]
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||||||
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end
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||||||
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||||||
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subgraph FILE_DEC_SEG["📄 dec2.vhd"]
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||||||
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DEC_SEG["dec_seg\n──────────\nBCD 4-bit\n→ SEG 8-bit"]
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||||||
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end
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||||||
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||||||
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%% ═══════════════════════════════════════════════════════
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||||||
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%% WIRING
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||||||
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%% ═══════════════════════════════════════════════════════
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||||||
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||||||
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%% Clock sources
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||||||
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CLK -->|"100 MHz"| DIV
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||||||
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CLK -->|"100 MHz"| DIV400
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||||||
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||||||
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%% 1 Hz counting path
|
||||||
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DIV -->|"clk_1_Hz"| AND_CE
|
||||||
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START --> AND_CE
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||||||
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AND_CE -->|"s_ce_units"| CNT_U
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||||||
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|
||||||
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%% 400 Hz display scan path
|
||||||
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DIV400 -->|"clk_400_Hz"| CNT2
|
||||||
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CNT2 -->|"s_cnt_2bit"| DEC_AN
|
||||||
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CNT2 -->|"s_cnt_2bit (S)"| MUX
|
||||||
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DEC_AN -->|"ANODES"| ANODS
|
||||||
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|
||||||
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%% Counter digits into mux
|
||||||
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CNT_U -->|"s_cnt_units (I0)"| MUX
|
||||||
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CNT_T -->|"s_cnt_tens (I1)"| MUX
|
||||||
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CNT_H -->|"s_cnt_hundreds (I2)"| MUX
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||||||
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CNT_K -->|"s_cnt_thousands (I3)"| MUX
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||||||
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|
||||||
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%% Segment output
|
||||||
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MUX -->|"s_mux_out"| DEC_SEG
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||||||
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DEC_SEG -->|"SEG"| SEGMENTS
|
||||||
1
project_6/proj2.mermaid.svg
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1
project_6/proj2.mermaid.svg
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File diff suppressed because one or more lines are too long
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After Width: | Height: | Size: 293 KiB |
@@ -1,281 +0,0 @@
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<?xml version="1.0" encoding="UTF-8"?>
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||||||
<!-- Product Version: Vivado v2022.2 (64-bit) -->
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|
||||||
<!-- -->
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|
||||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
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|
||||||
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|
||||||
<Project Version="7" Minor="61" Path="C:/Users/student/Documents/priecinok/project_6/project_5.xpr">
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|
||||||
<DefaultLaunch Dir="$PRUNDIR"/>
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|
||||||
<Configuration>
|
|
||||||
<Option Name="Id" Val="e38d1a4c4a2f4256841e587df17ee164"/>
|
|
||||||
<Option Name="Part" Val="xc7a35tcpg236-1"/>
|
|
||||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
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|
||||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
|
||||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
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|
||||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
|
||||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
|
||||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
|
||||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
|
||||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
|
||||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
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|
||||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
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|
||||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
|
||||||
<Option Name="SimulatorVersionXsim" Val="2022.2"/>
|
|
||||||
<Option Name="SimulatorVersionModelSim" Val="2022.2"/>
|
|
||||||
<Option Name="SimulatorVersionQuesta" Val="2022.2"/>
|
|
||||||
<Option Name="SimulatorVersionXcelium" Val="21.09.009"/>
|
|
||||||
<Option Name="SimulatorVersionVCS" Val="S-2021.09"/>
|
|
||||||
<Option Name="SimulatorVersionRiviera" Val="2022.04"/>
|
|
||||||
<Option Name="SimulatorVersionActiveHdl" Val="13.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
|
||||||
<Option Name="TargetLanguage" Val="VHDL"/>
|
|
||||||
<Option Name="SimulatorLanguage" Val="VHDL"/>
|
|
||||||
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
|
|
||||||
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../AppData/Roaming/Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/>
|
|
||||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
|
||||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
|
||||||
<Option Name="ProjectType" Val="Default"/>
|
|
||||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
|
||||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
|
||||||
<Option Name="IPCachePermission" Val="read"/>
|
|
||||||
<Option Name="IPCachePermission" Val="write"/>
|
|
||||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
|
||||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
|
||||||
<Option Name="SimCompileState" Val="TRUE"/>
|
|
||||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
|
||||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
|
||||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
|
||||||
<Option Name="EnableBDX" Val="FALSE"/>
|
|
||||||
<Option Name="DSABoardId" Val="basys3"/>
|
|
||||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTXSimExportSim" Val="0"/>
|
|
||||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
|
||||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
|
||||||
<Option Name="WTIesExportSim" Val="0"/>
|
|
||||||
<Option Name="WTVcsExportSim" Val="0"/>
|
|
||||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
|
||||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
|
||||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
|
||||||
<Option Name="XSimRadix" Val="hex"/>
|
|
||||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
|
||||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
|
||||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
|
||||||
<Option Name="SimTypes" Val="rtl"/>
|
|
||||||
<Option Name="SimTypes" Val="bfm"/>
|
|
||||||
<Option Name="SimTypes" Val="tlm"/>
|
|
||||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
|
||||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
|
||||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
|
||||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
|
||||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
|
||||||
</Configuration>
|
|
||||||
<FileSets Version="1" Minor="31">
|
|
||||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
|
||||||
<Filter Type="Srcs"/>
|
|
||||||
<File Path="$PSRCDIR/sources_1/new/counter.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/new/counter_2bit.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/new/dec2.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/new/decoder_bottom.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/new/divider.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/new/divider_400Hz.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/new/mux.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/new/top_modul.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<Config>
|
|
||||||
<Option Name="DesignMode" Val="RTL"/>
|
|
||||||
<Option Name="TopModule" Val="top_modul"/>
|
|
||||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
|
||||||
<Filter Type="Constrs"/>
|
|
||||||
<File Path="$PSRCDIR/constrs_1/new/projekt_5.xdc">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/constrs_1/imports/Downloads/Basys-3-Master.xdc">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="ImportPath" Val="$PPRDIR/../../../Downloads/Basys-3-Master.xdc"/>
|
|
||||||
<Attr Name="ImportTime" Val="1771253458"/>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<Config>
|
|
||||||
<Option Name="ConstrsType" Val="XDC"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
|
||||||
<Filter Type="Srcs"/>
|
|
||||||
<Config>
|
|
||||||
<Option Name="DesignMode" Val="RTL"/>
|
|
||||||
<Option Name="TopModule" Val="top_modul"/>
|
|
||||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
|
||||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
|
||||||
<Option Name="TransportPathDelay" Val="0"/>
|
|
||||||
<Option Name="TransportIntDelay" Val="0"/>
|
|
||||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
|
||||||
<Option Name="PamDesignTestbench" Val=""/>
|
|
||||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
|
||||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
|
||||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
|
||||||
<Option Name="SrcSet" Val="sources_1"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
|
||||||
<Filter Type="Utils"/>
|
|
||||||
<File Path="$PSRCDIR/utils_1/imports/synth_1/top_modul.dcp">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
<Attr Name="UsedInSteps" Val="synth_1"/>
|
|
||||||
<Attr Name="AutoDcp" Val="1"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<Config>
|
|
||||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
</FileSets>
|
|
||||||
<Simulators>
|
|
||||||
<Simulator Name="XSim">
|
|
||||||
<Option Name="Description" Val="Vivado Simulator"/>
|
|
||||||
<Option Name="CompiledLib" Val="0"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="ModelSim">
|
|
||||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="Questa">
|
|
||||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="Riviera">
|
|
||||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="ActiveHDL">
|
|
||||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
|
||||||
</Simulator>
|
|
||||||
</Simulators>
|
|
||||||
<Runs Version="1" Minor="19">
|
|
||||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top_modul.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
|
||||||
<Step Id="synth_design"/>
|
|
||||||
</Strategy>
|
|
||||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
||||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
|
||||||
<Step Id="init_design"/>
|
|
||||||
<Step Id="opt_design"/>
|
|
||||||
<Step Id="power_opt_design"/>
|
|
||||||
<Step Id="place_design"/>
|
|
||||||
<Step Id="post_place_power_opt_design"/>
|
|
||||||
<Step Id="phys_opt_design"/>
|
|
||||||
<Step Id="route_design"/>
|
|
||||||
<Step Id="post_route_phys_opt_design"/>
|
|
||||||
<Step Id="write_bitstream"/>
|
|
||||||
</Strategy>
|
|
||||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
||||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
</Runs>
|
|
||||||
<Board>
|
|
||||||
<Jumpers/>
|
|
||||||
</Board>
|
|
||||||
<DashboardSummary Version="1" Minor="0">
|
|
||||||
<Dashboards>
|
|
||||||
<Dashboard Name="default_dashboard">
|
|
||||||
<Gadgets>
|
|
||||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
|
||||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
|
||||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
</Gadgets>
|
|
||||||
</Dashboard>
|
|
||||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
|
||||||
</Dashboards>
|
|
||||||
</DashboardSummary>
|
|
||||||
</Project>
|
|
||||||
@@ -61,10 +61,11 @@ begin
|
|||||||
end if;
|
end if;
|
||||||
end process;
|
end process;
|
||||||
|
|
||||||
|
|
||||||
-- Terminal Count logic (The red line connection)
|
-- Terminal Count logic (The red line connection)
|
||||||
-- TC is '1' ONLY when we are at 9 AND the enable pulse is active.
|
-- TC is '1' ONLY when we are at 9 AND the enable pulse is active.
|
||||||
-- This ensures the next counter only moves once per rollover.
|
-- This ensures the next counter only moves once per rollover.
|
||||||
TC <= '1' when (s_cnt = "1001" and CE = '1') else '0';
|
-- TC <= '1' when (s_cnt = "1001" and CE = '1') else '0'; / TODO
|
||||||
|
|
||||||
-- Drive the output ports
|
-- Drive the output ports
|
||||||
COUNT_OUT <= s_cnt;
|
COUNT_OUT <= s_cnt;
|
||||||
@@ -48,7 +48,7 @@ begin
|
|||||||
if RST = '1' then
|
if RST = '1' then
|
||||||
s_cnt <= (others => '0');
|
s_cnt <= (others => '0');
|
||||||
CLK_1_Hz <= '0';
|
CLK_1_Hz <= '0';
|
||||||
elsif s_cnt = 5_000_000 then
|
elsif s_cnt = 99_999_999 then
|
||||||
s_cnt <= (others => '0');
|
s_cnt <= (others => '0');
|
||||||
CLK_1_Hz <= '1'; -- The pulse
|
CLK_1_Hz <= '1'; -- The pulse
|
||||||
else
|
else
|
||||||
@@ -167,24 +167,24 @@ begin
|
|||||||
|
|
||||||
U_DEC_ANODES : decoder_an
|
U_DEC_ANODES : decoder_an
|
||||||
port map (
|
port map (
|
||||||
SEL => s_cnt_2bit, -- 2-bitov<6F> sign<67>l
|
SEL => s_cnt_2bit, -- 2-bitový signál
|
||||||
ANODES => ANODS -- V<>stupn<70> port top modulu
|
ANODES => ANODS -- Výstupný port top modulu
|
||||||
);
|
);
|
||||||
|
|
||||||
U_MUX : mux
|
U_MUX : mux
|
||||||
port map (
|
port map (
|
||||||
I0 => s_cnt_units, -- V<>stup z prv<72>ho <20><>ta<74>a
|
I0 => s_cnt_units, -- Výstup z prvého èítaèa
|
||||||
I1 => s_cnt_tens, -- V<>stup z druh<75>ho <20><>ta<74>a
|
I1 => s_cnt_tens, -- Výstup z druhého èítaèa
|
||||||
I2 => s_cnt_hundreds,
|
I2 => s_cnt_hundreds,
|
||||||
I3 => s_cnt_thousands,
|
I3 => s_cnt_thousands,
|
||||||
S => s_cnt_2bit, -- Sign<67>l zo zelen<65>ho <20><>ta<74>a (v<>ber an<61>dy)
|
S => s_cnt_2bit, -- Signál zo zeleného èítaèa (výber anódy)
|
||||||
Y => s_mux_out -- Vybran<61> <20><>slica pre segmenty
|
Y => s_mux_out -- Vybraná èíslica pre segmenty
|
||||||
);
|
);
|
||||||
|
|
||||||
U_DEC_SEG : dec_seg
|
U_DEC_SEG : dec_seg
|
||||||
port map (
|
port map (
|
||||||
BCD => s_mux_out, -- <20><>slica vybran<61> multiplexerom
|
BCD => s_mux_out, -- Èíslica vybraná multiplexerom
|
||||||
SEG => SEGMENTS -- V<>stupn<70> port top modulu (8 bitov)
|
SEG => SEGMENTS -- Výstupný port top modulu (8 bitov)
|
||||||
);
|
);
|
||||||
|
|
||||||
end Behavioral;
|
end Behavioral;
|
||||||
Binary file not shown.
|
Before Width: | Height: | Size: 1.2 MiB |
@@ -1,77 +0,0 @@
|
|||||||
----------------------------------------------------------------------------------
|
|
||||||
-- Company:
|
|
||||||
-- Engineer:
|
|
||||||
--
|
|
||||||
-- Create Date: 09.03.2026 15:14:35
|
|
||||||
-- Design Name:
|
|
||||||
-- Module Name: counter - Behavioral
|
|
||||||
-- Project Name:
|
|
||||||
-- Target Devices:
|
|
||||||
-- Tool Versions:
|
|
||||||
-- Description:
|
|
||||||
--
|
|
||||||
-- Dependencies:
|
|
||||||
--
|
|
||||||
-- Revision:
|
|
||||||
-- Revision 0.01 - File Created
|
|
||||||
-- Additional Comments:
|
|
||||||
--
|
|
||||||
----------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
|
|
||||||
library IEEE;
|
|
||||||
use IEEE.STD_LOGIC_1164.ALL;
|
|
||||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
|
||||||
|
|
||||||
-- Uncomment the following library declaration if using
|
|
||||||
-- arithmetic functions with Signed or Unsigned values
|
|
||||||
--use IEEE.NUMERIC_STD.ALL;
|
|
||||||
|
|
||||||
-- Uncomment the following library declaration if instantiating
|
|
||||||
-- any Xilinx leaf cells in this code.
|
|
||||||
--library UNISIM;
|
|
||||||
--use UNISIM.VComponents.all;
|
|
||||||
|
|
||||||
entity counter is
|
|
||||||
Generic ( MAX_LIMIT : STD_LOGIC_VECTOR(3 downto 0) := "1001" ); -- Default to 9
|
|
||||||
Port ( CLK : in STD_LOGIC;
|
|
||||||
RST : in STD_LOGIC;
|
|
||||||
CE : in STD_LOGIC;
|
|
||||||
PE : in STD_LOGIC;
|
|
||||||
DIN : in STD_LOGIC_VECTOR(3 downto 0);
|
|
||||||
TC : out STD_LOGIC;
|
|
||||||
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
|
|
||||||
end counter;
|
|
||||||
|
|
||||||
architecture Behavioral of counter is
|
|
||||||
-- Internal signal to keep track of the current number
|
|
||||||
signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
|
||||||
begin
|
|
||||||
|
|
||||||
-- Main counting logic
|
|
||||||
process(CLK)
|
|
||||||
begin
|
|
||||||
if rising_edge(CLK) then
|
|
||||||
if RST = '1' then
|
|
||||||
s_cnt <= "0000";
|
|
||||||
TC <= '0'; -- Reset TC
|
|
||||||
elsif PE = '1' then
|
|
||||||
s_cnt <= DIN;
|
|
||||||
TC <= '0';
|
|
||||||
elsif CE = '1' then
|
|
||||||
if s_cnt = MAX_LIMIT then
|
|
||||||
s_cnt <= "0000"; -- Reset to 0 when limit is hit
|
|
||||||
TC <= '1';
|
|
||||||
else
|
|
||||||
s_cnt <= s_cnt + 1; -- Otherwise increment
|
|
||||||
TC <= '0';
|
|
||||||
end if;
|
|
||||||
else
|
|
||||||
TC <= '0';
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end process;
|
|
||||||
|
|
||||||
COUNT_OUT <= s_cnt;
|
|
||||||
|
|
||||||
end Behavioral;
|
|
||||||
@@ -1,302 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
|
||||||
<!-- Product Version: Vivado v2022.2 (64-bit) -->
|
|
||||||
<!-- -->
|
|
||||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
|
||||||
|
|
||||||
<Project Version="7" Minor="61" Path="C:/Users/student/Documents/priecinok/project_7/project_5.xpr">
|
|
||||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
|
||||||
<Configuration>
|
|
||||||
<Option Name="Id" Val="e38d1a4c4a2f4256841e587df17ee164"/>
|
|
||||||
<Option Name="Part" Val="xc7a35tcpg236-1"/>
|
|
||||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
|
||||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
|
||||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
|
||||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
|
||||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
|
||||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
|
||||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
|
||||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
|
||||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
|
||||||
<Option Name="SimulatorVersionXsim" Val="2022.2"/>
|
|
||||||
<Option Name="SimulatorVersionModelSim" Val="2022.2"/>
|
|
||||||
<Option Name="SimulatorVersionQuesta" Val="2022.2"/>
|
|
||||||
<Option Name="SimulatorVersionXcelium" Val="21.09.009"/>
|
|
||||||
<Option Name="SimulatorVersionVCS" Val="S-2021.09"/>
|
|
||||||
<Option Name="SimulatorVersionRiviera" Val="2022.04"/>
|
|
||||||
<Option Name="SimulatorVersionActiveHdl" Val="13.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
|
||||||
<Option Name="TargetLanguage" Val="VHDL"/>
|
|
||||||
<Option Name="SimulatorLanguage" Val="VHDL"/>
|
|
||||||
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
|
|
||||||
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../AppData/Roaming/Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/>
|
|
||||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
|
||||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
|
||||||
<Option Name="ProjectType" Val="Default"/>
|
|
||||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
|
||||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
|
||||||
<Option Name="IPCachePermission" Val="read"/>
|
|
||||||
<Option Name="IPCachePermission" Val="write"/>
|
|
||||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
|
||||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
|
||||||
<Option Name="SimCompileState" Val="TRUE"/>
|
|
||||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
|
||||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
|
||||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
|
||||||
<Option Name="EnableBDX" Val="FALSE"/>
|
|
||||||
<Option Name="DSABoardId" Val="basys3"/>
|
|
||||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTXSimExportSim" Val="0"/>
|
|
||||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
|
||||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
|
||||||
<Option Name="WTIesExportSim" Val="0"/>
|
|
||||||
<Option Name="WTVcsExportSim" Val="0"/>
|
|
||||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
|
||||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
|
||||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
|
||||||
<Option Name="XSimRadix" Val="hex"/>
|
|
||||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
|
||||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
|
||||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
|
||||||
<Option Name="SimTypes" Val="rtl"/>
|
|
||||||
<Option Name="SimTypes" Val="bfm"/>
|
|
||||||
<Option Name="SimTypes" Val="tlm"/>
|
|
||||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
|
||||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
|
||||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
|
||||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
|
||||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
|
||||||
</Configuration>
|
|
||||||
<FileSets Version="1" Minor="31">
|
|
||||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
|
||||||
<Filter Type="Srcs"/>
|
|
||||||
<File Path="$PSRCDIR/sources_1/new/counter.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/new/counter_2bit.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/new/dec2.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/new/decoder_bottom.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/new/divider.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/new/divider_400Hz.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/new/mux.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/new/top_modul.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/new/counter_hour_tens.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="AutoDisabled" Val="1"/>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/new/counter_minute_tens.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="AutoDisabled" Val="1"/>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/new/counter_ones.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="AutoDisabled" Val="1"/>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<Config>
|
|
||||||
<Option Name="DesignMode" Val="RTL"/>
|
|
||||||
<Option Name="TopModule" Val="top_modul"/>
|
|
||||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
|
||||||
<Filter Type="Constrs"/>
|
|
||||||
<File Path="$PSRCDIR/constrs_1/new/projekt_5.xdc">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/constrs_1/imports/Downloads/Basys-3-Master.xdc">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="ImportPath" Val="$PPRDIR/../../../Downloads/Basys-3-Master.xdc"/>
|
|
||||||
<Attr Name="ImportTime" Val="1771253458"/>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<Config>
|
|
||||||
<Option Name="ConstrsType" Val="XDC"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
|
||||||
<Filter Type="Srcs"/>
|
|
||||||
<Config>
|
|
||||||
<Option Name="DesignMode" Val="RTL"/>
|
|
||||||
<Option Name="TopModule" Val="top_modul"/>
|
|
||||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
|
||||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
|
||||||
<Option Name="TransportPathDelay" Val="0"/>
|
|
||||||
<Option Name="TransportIntDelay" Val="0"/>
|
|
||||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
|
||||||
<Option Name="PamDesignTestbench" Val=""/>
|
|
||||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
|
||||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
|
||||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
|
||||||
<Option Name="SrcSet" Val="sources_1"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
|
||||||
<Filter Type="Utils"/>
|
|
||||||
<File Path="$PSRCDIR/utils_1/imports/synth_1/top_modul.dcp">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
<Attr Name="UsedInSteps" Val="synth_1"/>
|
|
||||||
<Attr Name="AutoDcp" Val="1"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<Config>
|
|
||||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
</FileSets>
|
|
||||||
<Simulators>
|
|
||||||
<Simulator Name="XSim">
|
|
||||||
<Option Name="Description" Val="Vivado Simulator"/>
|
|
||||||
<Option Name="CompiledLib" Val="0"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="ModelSim">
|
|
||||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="Questa">
|
|
||||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="Riviera">
|
|
||||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="ActiveHDL">
|
|
||||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
|
||||||
</Simulator>
|
|
||||||
</Simulators>
|
|
||||||
<Runs Version="1" Minor="19">
|
|
||||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top_modul.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
|
||||||
<Step Id="synth_design"/>
|
|
||||||
</Strategy>
|
|
||||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
||||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
|
||||||
<Step Id="init_design"/>
|
|
||||||
<Step Id="opt_design"/>
|
|
||||||
<Step Id="power_opt_design"/>
|
|
||||||
<Step Id="place_design"/>
|
|
||||||
<Step Id="post_place_power_opt_design"/>
|
|
||||||
<Step Id="phys_opt_design"/>
|
|
||||||
<Step Id="route_design"/>
|
|
||||||
<Step Id="post_route_phys_opt_design"/>
|
|
||||||
<Step Id="write_bitstream"/>
|
|
||||||
</Strategy>
|
|
||||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
||||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
</Runs>
|
|
||||||
<Board>
|
|
||||||
<Jumpers/>
|
|
||||||
</Board>
|
|
||||||
<DashboardSummary Version="1" Minor="0">
|
|
||||||
<Dashboards>
|
|
||||||
<Dashboard Name="default_dashboard">
|
|
||||||
<Gadgets>
|
|
||||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
|
||||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
|
||||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
</Gadgets>
|
|
||||||
</Dashboard>
|
|
||||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
|
||||||
</Dashboards>
|
|
||||||
</DashboardSummary>
|
|
||||||
</Project>
|
|
||||||
Binary file not shown.
|
Before Width: | Height: | Size: 1.2 MiB |
@@ -11,7 +11,6 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK
|
|||||||
## Switches
|
## Switches
|
||||||
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {RST}]
|
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {RST}]
|
||||||
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {START}]
|
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {START}]
|
||||||
|
|
||||||
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {sw[2]}]
|
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {sw[2]}]
|
||||||
#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports {sw[3]}]
|
#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports {sw[3]}]
|
||||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {sw[4]}]
|
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {sw[4]}]
|
||||||
@@ -22,10 +21,10 @@ set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {START}]
|
|||||||
#set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports {sw[9]}]
|
#set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports {sw[9]}]
|
||||||
#set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports {sw[10]}]
|
#set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports {sw[10]}]
|
||||||
#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {sw[11]}]
|
#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {sw[11]}]
|
||||||
set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[0]}]
|
#set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports {sw[12]}]
|
||||||
set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[1]}]
|
#set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports {sw[13]}]
|
||||||
set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[2]}]
|
#set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {sw[14]}]
|
||||||
set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[3]}]
|
#set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {sw[15]}]
|
||||||
|
|
||||||
|
|
||||||
## LEDs
|
## LEDs
|
||||||
@@ -65,14 +64,10 @@ set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports {ANODS[3]
|
|||||||
|
|
||||||
##Buttons
|
##Buttons
|
||||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports btnC]
|
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports btnC]
|
||||||
# btnU -> Hours Tens
|
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports btnU]
|
||||||
set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports {BTN_LOAD[3]}]
|
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports btnL]
|
||||||
# btnL -> Hours Units
|
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports btnR]
|
||||||
set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports {BTN_LOAD[2]}]
|
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports btnD]
|
||||||
# btnR -> Minutes Tens
|
|
||||||
set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports {BTN_LOAD[1]}]
|
|
||||||
# btnD -> Minutes Units
|
|
||||||
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports {BTN_LOAD[0]}]
|
|
||||||
|
|
||||||
|
|
||||||
##Pmod Header JA
|
##Pmod Header JA
|
||||||
@@ -3,17 +3,17 @@ library IEEE;
|
|||||||
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||||
|
|
||||||
entity cnt_0_2 is
|
entity counter is
|
||||||
Port ( CLK : in STD_LOGIC;
|
Port ( CLK : in STD_LOGIC;
|
||||||
-- DIN : in STD_LOGIC_VECTOR (3 downto 0); -- teraz nas nezaujima
|
DIN : in STD_LOGIC_VECTOR (3 downto 0); -- teraz nas nezaujima
|
||||||
-- PE : in STD_LOGIC; -- teraz nas nezaujima
|
PE : in STD_LOGIC; -- teraz nas nezaujima
|
||||||
CE : in STD_LOGIC;
|
CE : in STD_LOGIC;
|
||||||
RST : in STD_LOGIC;
|
RST : in STD_LOGIC;
|
||||||
TC : out STD_LOGIC;
|
TC : out STD_LOGIC;
|
||||||
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
|
COUNT_OUT : out STD_LOGIC_VECTOR (2 downto 0));
|
||||||
end cnt_0_2;
|
end counter;
|
||||||
|
|
||||||
architecture Behavioral of cnt_0_2 is
|
architecture Behavioral of counter is
|
||||||
-- Internal signal to keep track of the current number
|
-- Internal signal to keep track of the current number
|
||||||
signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
||||||
begin
|
begin
|
||||||
@@ -3,15 +3,15 @@ library IEEE;
|
|||||||
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||||
|
|
||||||
entity cnt_0_5 is
|
entity counter is
|
||||||
Port ( CLK : in STD_LOGIC;
|
Port ( CLK : in STD_LOGIC;
|
||||||
RST : in STD_LOGIC;
|
RST : in STD_LOGIC;
|
||||||
CE : in STD_LOGIC;
|
CE : in STD_LOGIC;
|
||||||
TC : out STD_LOGIC;
|
TC : out STD_LOGIC;
|
||||||
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
|
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
|
||||||
end cnt_0_5;
|
end counter;
|
||||||
|
|
||||||
architecture Behavioral of cnt_0_5 is
|
architecture Behavioral of counter is
|
||||||
-- Internal signal to keep track of the current number
|
-- Internal signal to keep track of the current number
|
||||||
signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
||||||
begin
|
begin
|
||||||
@@ -4,15 +4,15 @@ library IEEE;
|
|||||||
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||||
|
|
||||||
entity cnt_0_9 is
|
entity counter is
|
||||||
Port ( CLK : in STD_LOGIC;
|
Port ( CLK : in STD_LOGIC;
|
||||||
CE : in STD_LOGIC;
|
CE : in STD_LOGIC;
|
||||||
RST : in STD_LOGIC;
|
RST : in STD_LOGIC;
|
||||||
TC : out STD_LOGIC;
|
TC : out STD_LOGIC;
|
||||||
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
|
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
|
||||||
end cnt_0_9;
|
end counter;
|
||||||
|
|
||||||
architecture Behavioral of cnt_0_9 is
|
architecture Behavioral of counter is
|
||||||
-- Internal signal to keep track of the current number
|
-- Internal signal to keep track of the current number
|
||||||
signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
||||||
begin
|
begin
|
||||||
@@ -48,7 +48,7 @@ begin
|
|||||||
if RST = '1' then
|
if RST = '1' then
|
||||||
s_cnt <= (others => '0');
|
s_cnt <= (others => '0');
|
||||||
CLK_1_Hz <= '0';
|
CLK_1_Hz <= '0';
|
||||||
elsif s_cnt = 5_000_000 then
|
elsif s_cnt = 99_999_999 then
|
||||||
s_cnt <= (others => '0');
|
s_cnt <= (others => '0');
|
||||||
CLK_1_Hz <= '1'; -- The pulse
|
CLK_1_Hz <= '1'; -- The pulse
|
||||||
else
|
else
|
||||||
@@ -1,42 +1,12 @@
|
|||||||
----------------------------------------------------------------------------------
|
|
||||||
-- Company:
|
|
||||||
-- Engineer:
|
|
||||||
--
|
|
||||||
-- Create Date: 09.03.2026 14:40:14
|
|
||||||
-- Design Name:
|
|
||||||
-- Module Name: top_modul - Behavioral
|
|
||||||
-- Project Name:
|
|
||||||
-- Target Devices:
|
|
||||||
-- Tool Versions:
|
|
||||||
-- Description:
|
|
||||||
--
|
|
||||||
-- Dependencies:
|
|
||||||
--
|
|
||||||
-- Revision:
|
|
||||||
-- Revision 0.01 - File Created
|
|
||||||
-- Additional Comments:
|
|
||||||
--
|
|
||||||
----------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
|
|
||||||
library IEEE;
|
library IEEE;
|
||||||
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
|
||||||
-- Uncomment the following library declaration if using
|
|
||||||
-- arithmetic functions with Signed or Unsigned values
|
|
||||||
--use IEEE.NUMERIC_STD.ALL;
|
|
||||||
|
|
||||||
-- Uncomment the following library declaration if instantiating
|
|
||||||
-- any Xilinx leaf cells in this code.
|
|
||||||
--library UNISIM;
|
|
||||||
--use UNISIM.VComponents.all;
|
|
||||||
|
|
||||||
entity top_modul is
|
entity top_modul is
|
||||||
Port ( CLK : in STD_LOGIC;
|
Port ( CLK : in STD_LOGIC;
|
||||||
RST : in STD_LOGIC;
|
RST : in STD_LOGIC;
|
||||||
START : in STD_LOGIC;
|
START : in STD_LOGIC;
|
||||||
SW_DIN : in STD_LOGIC_VECTOR (3 downto 0); -- The value to set
|
|
||||||
BTN_LOAD : in STD_LOGIC_VECTOR (3 downto 0); -- Which digit to set
|
|
||||||
SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
|
SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
|
||||||
ANODS : out STD_LOGIC_VECTOR (3 downto 0));
|
ANODS : out STD_LOGIC_VECTOR (3 downto 0));
|
||||||
end top_modul;
|
end top_modul;
|
||||||
@@ -55,12 +25,25 @@ architecture Behavioral of top_modul is
|
|||||||
CLK_400_Hz : out STD_LOGIC); -- This will be our enable pulse
|
CLK_400_Hz : out STD_LOGIC); -- This will be our enable pulse
|
||||||
end component;
|
end component;
|
||||||
|
|
||||||
component counter is
|
component cnt_0_9 is
|
||||||
Generic ( MAX_LIMIT : STD_LOGIC_VECTOR(3 downto 0) := "1001" ); -- Default to 9
|
Port ( CLK : in STD_LOGIC;
|
||||||
|
CE : in STD_LOGIC;
|
||||||
|
RST : in STD_LOGIC;
|
||||||
|
TC : out STD_LOGIC;
|
||||||
|
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
|
||||||
|
end component;
|
||||||
|
|
||||||
|
component cnt_0_5 is
|
||||||
|
Port ( CLK : in STD_LOGIC;
|
||||||
|
CE : in STD_LOGIC;
|
||||||
|
RST : in STD_LOGIC;
|
||||||
|
TC : out STD_LOGIC;
|
||||||
|
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
|
||||||
|
end component;
|
||||||
|
|
||||||
|
component cnt_0_2 is
|
||||||
Port ( CLK : in STD_LOGIC;
|
Port ( CLK : in STD_LOGIC;
|
||||||
CE : in STD_LOGIC;
|
CE : in STD_LOGIC;
|
||||||
PE : in STD_LOGIC;
|
|
||||||
DIN : in STD_LOGIC_VECTOR(3 downto 0);
|
|
||||||
RST : in STD_LOGIC;
|
RST : in STD_LOGIC;
|
||||||
TC : out STD_LOGIC;
|
TC : out STD_LOGIC;
|
||||||
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
|
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
|
||||||
@@ -94,7 +77,6 @@ architecture Behavioral of top_modul is
|
|||||||
signal clk_1_Hz : std_logic;
|
signal clk_1_Hz : std_logic;
|
||||||
signal clk_400_Hz : std_logic;
|
signal clk_400_Hz : std_logic;
|
||||||
|
|
||||||
signal s_ce_units : std_logic;
|
|
||||||
-- Internal signals to connect the counters
|
-- Internal signals to connect the counters
|
||||||
signal sig_m_units : std_logic_vector(3 downto 0);
|
signal sig_m_units : std_logic_vector(3 downto 0);
|
||||||
signal sig_m_tens : std_logic_vector(3 downto 0);
|
signal sig_m_tens : std_logic_vector(3 downto 0);
|
||||||
@@ -125,58 +107,45 @@ begin
|
|||||||
CLK_400_Hz => clk_400_Hz
|
CLK_400_Hz => clk_400_Hz
|
||||||
);
|
);
|
||||||
|
|
||||||
s_ce_units <= clk_1_Hz and START;
|
|
||||||
-- MINUTES UNITS (0-9)
|
-- MINUTES UNITS (0-9)
|
||||||
U_CNT_MIN_UNITS : counter
|
U_CNT_MIN_UNITS : cnt_0_9
|
||||||
generic map ( MAX_LIMIT => "1001" ) -- To 9
|
|
||||||
port map (
|
port map (
|
||||||
CLK => CLK,
|
CLK => CLK,
|
||||||
RST => RST,
|
RST => RST,
|
||||||
CE => s_ce_units,
|
CE => clk_1_Hz and START,
|
||||||
PE => BTN_LOAD(0),
|
|
||||||
DIN => SW_DIN,
|
|
||||||
TC => tc_mu,
|
TC => tc_mu,
|
||||||
COUNT_OUT => sig_m_units
|
COUNT_OUT => sig_m_units
|
||||||
);
|
);
|
||||||
|
|
||||||
-- MINUTES TENS (0-5)
|
-- MINUTES TENS (0-5)
|
||||||
U_CNT_MIN_TENS : counter
|
U_CNT_MIN_TENS : cnt_0_5
|
||||||
generic map ( MAX_LIMIT => "0101" ) -- To 5
|
|
||||||
port map (
|
port map (
|
||||||
CLK => CLK,
|
CLK => CLK,
|
||||||
RST => RST,
|
RST => RST,
|
||||||
CE => tc_mu,
|
CE => tc_mu,
|
||||||
PE => BTN_LOAD(1),
|
|
||||||
DIN => SW_DIN,
|
|
||||||
TC => tc_mt,
|
TC => tc_mt,
|
||||||
COUNT_OUT => sig_m_tens
|
COUNT_OUT => sig_m_tens
|
||||||
);
|
);
|
||||||
|
|
||||||
-- Logic to reset hours at 24:00
|
-- Logic to reset hours at 24:00
|
||||||
hour_reset <= '1' when (RST = '1' or (sig_h_tens = "0010" and sig_h_units = "0011" and tc_mt = '1')) else '0';
|
hour_reset <= '1' when (RST = '1' or (sig_h_tens = "0010" and sig_h_units = "0100")) else '0';
|
||||||
|
|
||||||
-- HOURS UNITS (0-9)
|
-- HOURS UNITS (0-9)
|
||||||
U_CNT_HOR_UNITS : counter
|
U_CNT_HOR_UNITS : cnt_0_9
|
||||||
generic map ( MAX_LIMIT => "1001" ) -- To 9
|
|
||||||
port map (
|
port map (
|
||||||
CLK => CLK,
|
CLK => CLK,
|
||||||
RST => hour_reset,
|
RST => hour_reset,
|
||||||
CE => tc_mt,
|
CE => tc_mt,
|
||||||
PE => BTN_LOAD(2),
|
|
||||||
DIN => SW_DIN,
|
|
||||||
TC => tc_hu,
|
TC => tc_hu,
|
||||||
COUNT_OUT => sig_h_units
|
COUNT_OUT => sig_h_units
|
||||||
);
|
);
|
||||||
|
|
||||||
-- HOURS TENS (0-2)
|
-- HOURS TENS (0-2)
|
||||||
U_CNT_HOR_TENS : counter
|
U_CNT_HOR_TENS : cnt_0_2
|
||||||
generic map ( MAX_LIMIT => "0010" ) -- To 2
|
|
||||||
port map (
|
port map (
|
||||||
CLK => CLK,
|
CLK => CLK,
|
||||||
RST => hour_reset,
|
RST => hour_reset,
|
||||||
CE => tc_hu,
|
CE => tc_hu,
|
||||||
PE => BTN_LOAD(3),
|
|
||||||
DIN => SW_DIN,
|
|
||||||
TC => open,
|
TC => open,
|
||||||
COUNT_OUT => sig_h_tens
|
COUNT_OUT => sig_h_tens
|
||||||
);
|
);
|
||||||
@@ -190,13 +159,13 @@ begin
|
|||||||
|
|
||||||
U_DEC_ANODES : decoder_an
|
U_DEC_ANODES : decoder_an
|
||||||
port map (
|
port map (
|
||||||
SEL => s_cnt_2bit,
|
SEL => s_cnt_2bit, -- 2-bitový signál
|
||||||
ANODES => ANODS
|
ANODES => ANODS -- Výstupný port top modulu
|
||||||
);
|
);
|
||||||
|
|
||||||
U_MUX : mux
|
U_MUX : mux
|
||||||
port map (
|
port map (
|
||||||
I0 => sig_m_units,
|
I0 => sig_m_units, -- Corrected signal names
|
||||||
I1 => sig_m_tens,
|
I1 => sig_m_tens,
|
||||||
I2 => sig_h_units,
|
I2 => sig_h_units,
|
||||||
I3 => sig_h_tens,
|
I3 => sig_h_tens,
|
||||||
Reference in New Issue
Block a user