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FPGA---VHDL
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6af72b448af4c62a1990e595dba99e45c1d94e7a
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Filipriec
6af72b448a
basys 3 imported to project 6
2026-03-16 12:35:52 +01:00
project_1
working z predoslych hodin
2026-03-09 14:04:31 +01:00
project_2
working z predoslych hodin
2026-03-09 14:04:31 +01:00
project_3_nzio
working z predoslych hodin
2026-03-09 14:04:31 +01:00
project_4
nakreslene zadanie
2026-03-09 14:05:17 +01:00
project_5
hotovy priklad 5 funguje uplne bez problemov
2026-03-09 17:03:42 +01:00
project_6/project_6.srcs/constrs_1/imports
/Downloads
basys 3 imported to project 6
2026-03-16 12:35:52 +01:00
.gitignore
working z predoslych hodin
2026-03-09 14:04:31 +01:00
Description
To co sme robili v skole
2.8
MiB
Languages
VHDL
52.4%
Tcl
42.4%
Mermaid
5.2%
