working buttons and DIN to control display

project_6/proj.mermaid

@@ -1,117 +0,0 @@
-flowchart TD
-
-    %% ── External ports ──────────────────────────────────────────
-    CLK([CLK])
-    RST([RST])
-    START([START])
-    SEGMENTS([SEGMENTS\nout])
-    ANODS([ANODS\nout])
-
-    %% ════════════════════════════════════════════════════════════
-    %% FILE: divider.vhd
-    %% ════════════════════════════════════════════════════════════
-    subgraph FILE_DIV["📄 divider.vhd — entity: divider"]
-        direction TB
-        DIV["U_DIV\ndivider\n─────────────\nIN:  CLK, RST\nOUT: CLK_1_Hz"]
-    end
-
-    %% ════════════════════════════════════════════════════════════
-    %% FILE: divider_400Hz.vhd
-    %% ════════════════════════════════════════════════════════════
-    subgraph FILE_DIV400["📄 divider_400Hz.vhd — entity: divider_400Hz"]
-        direction TB
-        DIV400["U_DIV_400Hz\ndivider_400Hz\n─────────────\nIN:  CLK, RST\nOUT: CLK_400_Hz"]
-    end
-
-    %% ════════════════════════════════════════════════════════════
-    %% FILE: counter.vhd
-    %% ════════════════════════════════════════════════════════════
-    subgraph FILE_CNT["📄 counter.vhd — entity: counter  (reused 4x)"]
-        direction TB
-        CNT_U["U_CNT_TOP\ncounter - Units\n─────────────\nIN:  CLK, RST, CE\nOUT: COUNT_OUT, TC"]
-        CNT_T["U_CNT_BOTTOM\ncounter - Tens\n─────────────\nIN:  CLK, RST, CE\nOUT: COUNT_OUT, TC"]
-        CNT_H["U_CNT_3\ncounter - Hundreds\n─────────────\nIN:  CLK, RST, CE\nOUT: COUNT_OUT, TC"]
-        CNT_K["U_CNT_4\ncounter - Thousands\n─────────────\nIN:  CLK, RST, CE\nOUT: COUNT_OUT, TC=open"]
-    end
-
-    %% ════════════════════════════════════════════════════════════
-    %% FILE: counter_2bit.vhd
-    %% ════════════════════════════════════════════════════════════
-    subgraph FILE_CNT2["📄 counter_2bit.vhd — entity: counter_2bit"]
-        direction TB
-        CNT2["U_CNT_2BIT\ncounter_2bit\n─────────────\nIN:  CLK=clk_400Hz, RST\nOUT: COUNT_OUT 2-bit"]
-    end
-
-    %% ════════════════════════════════════════════════════════════
-    %% FILE: decoder_bottom.vhd
-    %% ════════════════════════════════════════════════════════════
-    subgraph FILE_DEC_AN["📄 decoder_bottom.vhd — entity: decoder_an"]
-        direction TB
-        DEC_AN["U_DEC_ANODES\ndecoder_an\n─────────────\nIN:  SEL 2-bit\nOUT: ANODES 4-bit"]
-    end
-
-    %% ════════════════════════════════════════════════════════════
-    %% FILE: mux.vhd
-    %% ════════════════════════════════════════════════════════════
-    subgraph FILE_MUX["📄 mux.vhd — entity: mux"]
-        direction TB
-        MUX["U_MUX\nmux 4x4-bit\n─────────────\nIN:  I0,I1,I2,I3, S 2-bit\nOUT: Y 4-bit"]
-    end
-
-    %% ════════════════════════════════════════════════════════════
-    %% FILE: dec2.vhd
-    %% ════════════════════════════════════════════════════════════
-    subgraph FILE_DEC_SEG["📄 dec2.vhd — entity: dec_seg"]
-        direction TB
-        DEC_SEG["U_DEC_SEG\ndec_seg\n─────────────\nIN:  BCD 4-bit\nOUT: SEG 8-bit"]
-    end
-
-    %% ════════════════════════════════════════════════════════════
-    %% top_modul.vhd — glue logic defined directly in this file
-    %% ════════════════════════════════════════════════════════════
-    subgraph FILE_TOP["📄 top_modul.vhd — glue signals defined here"]
-        direction TB
-        AND_START{"s_ce_units\nclk_1_Hz AND START"}
-        AND2{"CE for Hundreds\ns_tc_units AND s_tc_tens"}
-        AND3{"CE for Thousands\ns_tc_units AND s_tc_tens\nAND s_tc_hundreds"}
-    end
-
-    %% ── Clock / Reset wiring ─────────────────────────────────────
-    CLK --> DIV
-    RST --> DIV
-    CLK --> DIV400
-    RST --> DIV400
-    CLK --> CNT_U & CNT_T & CNT_H & CNT_K
-    RST --> CNT_U & CNT_T & CNT_H & CNT_K & CNT2
-
-    %% ── 1 Hz chain ───────────────────────────────────────────────
-    DIV  -->|"clk_1_Hz"| AND_START
-    START --> AND_START
-    AND_START -->|"s_ce_units (CE)"| CNT_U
-
-    %% ── BCD carry chain ──────────────────────────────────────────
-    CNT_U -->|"s_tc_units (TC->CE)"| CNT_T
-    CNT_U -->|"s_tc_units"| AND2
-    CNT_T -->|"s_tc_tens"| AND2
-    AND2  -->|"CE"| CNT_H
-
-    CNT_U -->|"s_tc_units"| AND3
-    CNT_T -->|"s_tc_tens"| AND3
-    CNT_H -->|"s_tc_hundreds"| AND3
-    AND3  -->|"CE"| CNT_K
-
-    %% ── 400 Hz display scan ──────────────────────────────────────
-    DIV400 -->|"clk_400_Hz"| CNT2
-    CNT2   -->|"s_cnt_2bit (SEL)"| DEC_AN
-    CNT2   -->|"s_cnt_2bit (S)"| MUX
-    DEC_AN -->|"ANODES"| ANODS
-
-    %% ── MUX inputs from counters ─────────────────────────────────
-    CNT_U -->|"s_cnt_units (I0)"| MUX
-    CNT_T -->|"s_cnt_tens (I1)"| MUX
-    CNT_H -->|"s_cnt_hundreds (I2)"| MUX
-    CNT_K -->|"s_cnt_thousands (I3)"| MUX
-
-    %% ── Segment decode ───────────────────────────────────────────
-    MUX     -->|"s_mux_out (BCD)"| DEC_SEG
-    DEC_SEG -->|"SEG"| SEGMENTS

project_6/proj2.mermaid

@@ -1,82 +0,0 @@
-flowchart LR
-
-    %% ── Inputs ───────────────────────────────────────────────────
-    CLK([CLK])
-    RST([RST])
-    START([START])
-
-    %% ── Outputs ──────────────────────────────────────────────────
-    SEGMENTS([SEGMENTS])
-    ANODS([ANODS])
-
-    %% ── Clock dividers ───────────────────────────────────────────
-    subgraph FILE_DIV["📄 divider.vhd"]
-        DIV["divider\n──────────\n100MHz → 1Hz pulse"]
-    end
-
-    subgraph FILE_DIV400["📄 divider_400Hz.vhd"]
-        DIV400["divider_400Hz\n──────────\n100MHz → 400Hz pulse"]
-    end
-
-    %% ── Glue in top_modul ────────────────────────────────────────
-    AND_CE(["⚡ top_modul.vhd\ns_ce_units =\nclk_1_Hz AND START"])
-
-    %% ── BCD counter chain ────────────────────────────────────────
-    subgraph FILE_CNT["📄 counter.vhd   (entity reused 4×)"]
-        direction LR
-        CNT_U["U_CNT_TOP\n── Units ──\nCE=s_ce_units\nTC→s_tc_units"]
-        CNT_T["U_CNT_BOTTOM\n── Tens ──\nCE=s_tc_units\nTC→s_tc_tens"]
-        CNT_H["U_CNT_3\n── Hundreds ──\nCE=tc_u AND tc_t\nTC→s_tc_hundreds"]
-        CNT_K["U_CNT_4\n── Thousands ──\nCE=tc_u AND tc_t\n    AND tc_h\nTC=open"]
-
-        CNT_U -->|"s_tc_units"| CNT_T
-        CNT_T -->|"s_tc_tens"| CNT_H
-        CNT_H -->|"s_tc_hundreds"| CNT_K
-    end
-
-    %% ── Display scan chain ───────────────────────────────────────
-    subgraph FILE_CNT2["📄 counter_2bit.vhd"]
-        CNT2["counter_2bit\n──────────\nIN: clk_400Hz\nOUT: s_cnt_2bit"]
-    end
-
-    subgraph FILE_DEC_AN["📄 decoder_bottom.vhd"]
-        DEC_AN["decoder_an\n──────────\nIN: SEL 2-bit\nOUT: ANODES 4-bit"]
-    end
-
-    %% ── Mux + segment decode ─────────────────────────────────────
-    subgraph FILE_MUX["📄 mux.vhd"]
-        MUX["mux  4×4-bit\n──────────\nI0–I3: digit values\nS: s_cnt_2bit\nY: s_mux_out"]
-    end
-
-    subgraph FILE_DEC_SEG["📄 dec2.vhd"]
-        DEC_SEG["dec_seg\n──────────\nBCD 4-bit\n→ SEG 8-bit"]
-    end
-
-    %% ═══════════════════════════════════════════════════════
-    %% WIRING
-    %% ═══════════════════════════════════════════════════════
-
-    %% Clock sources
-    CLK -->|"100 MHz"| DIV
-    CLK -->|"100 MHz"| DIV400
-
-    %% 1 Hz counting path
-    DIV  -->|"clk_1_Hz"| AND_CE
-    START --> AND_CE
-    AND_CE -->|"s_ce_units"| CNT_U
-
-    %% 400 Hz display scan path
-    DIV400 -->|"clk_400_Hz"| CNT2
-    CNT2   -->|"s_cnt_2bit"| DEC_AN
-    CNT2   -->|"s_cnt_2bit (S)"| MUX
-    DEC_AN -->|"ANODES"| ANODS
-
-    %% Counter digits into mux
-    CNT_U -->|"s_cnt_units  (I0)"| MUX
-    CNT_T -->|"s_cnt_tens   (I1)"| MUX
-    CNT_H -->|"s_cnt_hundreds (I2)"| MUX
-    CNT_K -->|"s_cnt_thousands (I3)"| MUX
-
-    %% Segment output
-    MUX     -->|"s_mux_out"| DEC_SEG
-    DEC_SEG -->|"SEG"| SEGMENTS

project_6/project_5.srcs/sources_1/new/counter.vhd

@@ -61,11 +61,10 @@ begin
         end if;
     end process;
 
-
     -- Terminal Count logic (The red line connection)
     -- TC is '1' ONLY when we are at 9 AND the enable pulse is active.
     -- This ensures the next counter only moves once per rollover.
-    -- TC <= '1' when (s_cnt = "1001" and CE = '1') else '0'; / TODO
+    TC <= '1' when (s_cnt = "1001" and CE = '1') else '0';
 
     -- Drive the output ports
     COUNT_OUT <= s_cnt;

project_6/project_5.srcs/sources_1/new/divider.vhd

@@ -48,7 +48,7 @@ begin
             if RST = '1' then
                 s_cnt <= (others => '0');
                 CLK_1_Hz <= '0';
-            elsif s_cnt = 99_999_999 then 
+            elsif s_cnt = 5_000_000 then 
                 s_cnt <= (others => '0');
                 CLK_1_Hz <= '1'; -- The pulse
             else

project_6/project_5.srcs/sources_1/new/top_modul.vhd

@@ -167,24 +167,24 @@ begin
         
     U_DEC_ANODES : decoder_an
         port map (
-            SEL    => s_cnt_2bit, -- 2-bitový signál 
-            ANODES => ANODS       -- Výstupný port top modulu
+            SEL    => s_cnt_2bit, -- 2-bitov<6F> sign<67>l 
+            ANODES => ANODS       -- V<>stupn<70> port top modulu
         );
 
     U_MUX : mux
         port map (
-            I0 => s_cnt_units, -- Výstup z prvého èítaèa
-            I1 => s_cnt_tens,  -- Výstup z druhého èítaèa
+            I0 => s_cnt_units, -- V<>stup z prv<72>ho <20><>ta<74>a
+            I1 => s_cnt_tens,  -- V<>stup z druh<75>ho <20><>ta<74>a
             I2 => s_cnt_hundreds,
             I3 => s_cnt_thousands,
-            S  => s_cnt_2bit,  -- Signál zo zeleného èítaèa (výber anódy)
-            Y  => s_mux_out    -- Vybraná èíslica pre segmenty
+            S  => s_cnt_2bit,  -- Sign<67>l zo zelen<65>ho <20><>ta<74>a (v<>ber an<61>dy)
+            Y  => s_mux_out    -- Vybran<61> <20><>slica pre segmenty
         );
         
     U_DEC_SEG : dec_seg
         port map (
-            BCD => s_mux_out, -- Èíslica vybraná multiplexerom
-            SEG => SEGMENTS   -- Výstupný port top modulu (8 bitov)
+            BCD => s_mux_out, -- <20><>slica vybran<61> multiplexerom
+            SEG => SEGMENTS   -- V<>stupn<70> port top modulu (8 bitov)
         );        
                 
 end Behavioral;

project_6/project_5.xpr

@@ -0,0 +1,281 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2022.2 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="61" Path="C:/Users/student/Documents/priecinok/project_6/project_5.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="e38d1a4c4a2f4256841e587df17ee164"/>
+    <Option Name="Part" Val="xc7a35tcpg236-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2022.2"/>
+    <Option Name="SimulatorVersionModelSim" Val="2022.2"/>
+    <Option Name="SimulatorVersionQuesta" Val="2022.2"/>
+    <Option Name="SimulatorVersionXcelium" Val="21.09.009"/>
+    <Option Name="SimulatorVersionVCS" Val="S-2021.09"/>
+    <Option Name="SimulatorVersionRiviera" Val="2022.04"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="13.0"/>
+    <Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+    <Option Name="TargetLanguage" Val="VHDL"/>
+    <Option Name="SimulatorLanguage" Val="VHDL"/>
+    <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
+    <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../AppData/Roaming/Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="EnableResourceEstimation" Val="FALSE"/>
+    <Option Name="SimCompileState" Val="TRUE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSABoardId" Val="basys3"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+    <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/new/counter.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/counter_2bit.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/dec2.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/decoder_bottom.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/divider.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/divider_400Hz.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/mux.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/top_modul.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="top_modul"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PSRCDIR/constrs_1/new/projekt_5.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/constrs_1/imports/Downloads/Basys-3-Master.xdc">
+        <FileInfo>
+          <Attr Name="ImportPath" Val="$PPRDIR/../../../Downloads/Basys-3-Master.xdc"/>
+          <Attr Name="ImportTime" Val="1771253458"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="top_modul"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <File Path="$PSRCDIR/utils_1/imports/synth_1/top_modul.dcp">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedInSteps" Val="synth_1"/>
+          <Attr Name="AutoDcp" Val="1"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="19">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top_modul.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board>
+    <Jumpers/>
+  </Board>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>

project_7/project_5.srcs/constrs_1/imports/Downloads/Basys-3-Master.xdc

@@ -11,6 +11,7 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK
 ## Switches
 set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports {RST}]
 set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports {START}]
+
 #set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports {sw[2]}]
 #set_property -dict { PACKAGE_PIN W17   IOSTANDARD LVCMOS33 } [get_ports {sw[3]}]
 #set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports {sw[4]}]
@@ -21,10 +22,10 @@ set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports {START}]
 #set_property -dict { PACKAGE_PIN T3    IOSTANDARD LVCMOS33 } [get_ports {sw[9]}]
 #set_property -dict { PACKAGE_PIN T2    IOSTANDARD LVCMOS33 } [get_ports {sw[10]}]
 #set_property -dict { PACKAGE_PIN R3    IOSTANDARD LVCMOS33 } [get_ports {sw[11]}]
-#set_property -dict { PACKAGE_PIN W2    IOSTANDARD LVCMOS33 } [get_ports {sw[12]}]
-#set_property -dict { PACKAGE_PIN U1    IOSTANDARD LVCMOS33 } [get_ports {sw[13]}]
-#set_property -dict { PACKAGE_PIN T1    IOSTANDARD LVCMOS33 } [get_ports {sw[14]}]
-#set_property -dict { PACKAGE_PIN R2    IOSTANDARD LVCMOS33 } [get_ports {sw[15]}]
+set_property -dict { PACKAGE_PIN W2    IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[0]}]
+set_property -dict { PACKAGE_PIN U1    IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[1]}]
+set_property -dict { PACKAGE_PIN T1    IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[2]}]
+set_property -dict { PACKAGE_PIN R2    IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[3]}]
 
 
 ## LEDs
@@ -64,10 +65,14 @@ set_property -dict { PACKAGE_PIN W4   IOSTANDARD LVCMOS33 } [get_ports {ANODS[3]
 
 ##Buttons
 #set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports btnC]
-#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports btnU]
-#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports btnL]
-#set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports btnR]
-#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports btnD]
+# btnU -> Hours Tens
+set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports {BTN_LOAD[3]}]
+# btnL -> Hours Units
+set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports {BTN_LOAD[2]}]
+# btnR -> Minutes Tens
+set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports {BTN_LOAD[1]}]
+# btnD -> Minutes Units
+set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports {BTN_LOAD[0]}]
 
 
 ##Pmod Header JA

project_7/project_5.srcs/sources_1/new/counter.vhd

@@ -0,0 +1,77 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09.03.2026 15:14:35
+-- Design Name: 
+-- Module Name: counter - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity counter is
+    Generic ( MAX_LIMIT : STD_LOGIC_VECTOR(3 downto 0) := "1001" ); -- Default to 9
+    Port ( CLK : in STD_LOGIC;
+           RST : in STD_LOGIC;
+           CE : in STD_LOGIC;
+           PE : in  STD_LOGIC;
+           DIN : in  STD_LOGIC_VECTOR(3 downto 0); 
+           TC : out STD_LOGIC;
+           COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
+end counter;
+
+architecture Behavioral of counter is
+    -- Internal signal to keep track of the current number
+    signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
+begin
+
+    -- Main counting logic
+    process(CLK)
+    begin
+        if rising_edge(CLK) then
+            if RST = '1' then
+                s_cnt <= "0000";
+                TC    <= '0'; -- Reset TC
+            elsif PE = '1' then
+                s_cnt <= DIN;
+                TC    <= '0';
+            elsif CE = '1' then
+                if s_cnt = MAX_LIMIT then
+                    s_cnt <= "0000";   -- Reset to 0 when limit is hit
+                    TC    <= '1';
+                else
+                    s_cnt <= s_cnt + 1; -- Otherwise increment
+                    TC    <= '0';
+                end if;
+            else
+                TC <= '0';
+            end if;
+        end if;
+    end process;
+
+    COUNT_OUT <= s_cnt;
+
+end Behavioral;

project_7/project_5.srcs/sources_1/new/counter_hour_tens.vhd

@@ -3,17 +3,17 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-entity counter is
+entity cnt_0_2 is
     Port ( CLK : in STD_LOGIC;
-           DIN : in STD_LOGIC_VECTOR (3 downto 0); -- teraz nas nezaujima
-           PE : in STD_LOGIC; -- teraz nas nezaujima
+           -- DIN : in STD_LOGIC_VECTOR (3 downto 0); -- teraz nas nezaujima
+           -- PE : in STD_LOGIC; -- teraz nas nezaujima
            CE : in STD_LOGIC;
            RST : in STD_LOGIC;
            TC : out STD_LOGIC;
-           COUNT_OUT : out STD_LOGIC_VECTOR (2 downto 0));
-end counter;
+           COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
+end cnt_0_2;
 
-architecture Behavioral of counter is
+architecture Behavioral of cnt_0_2 is
     -- Internal signal to keep track of the current number
     signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
 begin

project_7/project_5.srcs/sources_1/new/counter_minute_tens.vhd

@@ -3,15 +3,15 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-entity counter is
+entity cnt_0_5 is
     Port ( CLK : in STD_LOGIC;
            RST : in STD_LOGIC;
            CE : in STD_LOGIC;
            TC : out STD_LOGIC;
            COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
-end counter;
+end cnt_0_5;
 
-architecture Behavioral of counter is
+architecture Behavioral of cnt_0_5 is
     -- Internal signal to keep track of the current number
     signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
 begin

project_7/project_5.srcs/sources_1/new/counter_ones.vhd

@@ -4,15 +4,15 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-entity counter is
+entity cnt_0_9 is
     Port ( CLK : in STD_LOGIC;
            CE : in STD_LOGIC;
            RST : in STD_LOGIC;
            TC : out STD_LOGIC;
            COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
-end counter;
+end cnt_0_9;
 
-architecture Behavioral of counter is
+architecture Behavioral of cnt_0_9 is
     -- Internal signal to keep track of the current number
     signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
 begin

project_7/project_5.srcs/sources_1/new/divider.vhd

@@ -48,7 +48,7 @@ begin
             if RST = '1' then
                 s_cnt <= (others => '0');
                 CLK_1_Hz <= '0';
-            elsif s_cnt = 99_999_999 then 
+            elsif s_cnt = 5_000_000 then 
                 s_cnt <= (others => '0');
                 CLK_1_Hz <= '1'; -- The pulse
             else

project_7/project_5.srcs/sources_1/new/top_modul.vhd

@@ -1,12 +1,42 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09.03.2026 14:40:14
+-- Design Name: 
+-- Module Name: top_modul - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
 
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
 entity top_modul is
     Port ( CLK : in STD_LOGIC;
            RST : in STD_LOGIC;
            START : in STD_LOGIC;
+           SW_DIN   : in STD_LOGIC_VECTOR (3 downto 0); -- The value to set
+           BTN_LOAD : in STD_LOGIC_VECTOR (3 downto 0); -- Which digit to set
            SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
            ANODS : out STD_LOGIC_VECTOR (3 downto 0));
 end top_modul;
@@ -25,25 +55,12 @@ architecture Behavioral of top_modul is
                CLK_400_Hz : out STD_LOGIC); -- This will be our enable pulse
     end component;
     
-    component cnt_0_9 is
-        Port ( CLK : in STD_LOGIC;
-               CE : in STD_LOGIC;
-               RST : in STD_LOGIC;
-               TC : out STD_LOGIC;
-               COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
-    end component;
-
-    component cnt_0_5 is
-        Port ( CLK : in STD_LOGIC;
-               CE : in STD_LOGIC;
-               RST : in STD_LOGIC;
-               TC : out STD_LOGIC;
-               COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
-    end component;
-
-    component cnt_0_2 is
+	component counter is
+	    Generic ( MAX_LIMIT : STD_LOGIC_VECTOR(3 downto 0) := "1001" ); -- Default to 9
         Port ( CLK : in STD_LOGIC;
                CE : in STD_LOGIC;
+               PE : in STD_LOGIC;
+               DIN : in STD_LOGIC_VECTOR(3 downto 0);
                RST : in STD_LOGIC;
                TC : out STD_LOGIC;
                COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
@@ -77,7 +94,8 @@ architecture Behavioral of top_modul is
     signal clk_1_Hz   : std_logic;
     signal clk_400_Hz : std_logic;
 
-    -- Internal signals to connect the counters
+    signal s_ce_units   : std_logic;
+	-- Internal signals to connect the counters
     signal sig_m_units : std_logic_vector(3 downto 0);
     signal sig_m_tens  : std_logic_vector(3 downto 0);
     signal sig_h_units : std_logic_vector(3 downto 0);
@@ -107,45 +125,58 @@ begin
             CLK_400_Hz => clk_400_Hz
         );
         
-    -- MINUTES UNITS (0-9)
-    U_CNT_MIN_UNITS : cnt_0_9
+    s_ce_units <= clk_1_Hz and START;
+	-- MINUTES UNITS (0-9)
+    U_CNT_MIN_UNITS : counter
+        generic map ( MAX_LIMIT => "1001" ) -- To 9
         port map (
             CLK       => CLK,
             RST       => RST,
-            CE        => clk_1_Hz and START,
+            CE        => s_ce_units,
+            PE => BTN_LOAD(0),
+            DIN => SW_DIN,
             TC        => tc_mu,
             COUNT_OUT => sig_m_units
         );
 
     -- MINUTES TENS (0-5)
-    U_CNT_MIN_TENS : cnt_0_5
+    U_CNT_MIN_TENS : counter
+        generic map ( MAX_LIMIT => "0101" ) -- To 5
         port map (
             CLK       => CLK,
             RST       => RST,
             CE        => tc_mu,
+            PE => BTN_LOAD(1),
+            DIN => SW_DIN,
             TC        => tc_mt,
             COUNT_OUT => sig_m_tens
         );
 
     -- Logic to reset hours at 24:00
-    hour_reset <= '1' when (RST = '1' or (sig_h_tens = "0010" and sig_h_units = "0100")) else '0';
+    hour_reset <= '1' when (RST = '1' or (sig_h_tens = "0010" and sig_h_units = "0011" and tc_mt = '1')) else '0';
     
     -- HOURS UNITS (0-9)
-    U_CNT_HOR_UNITS : cnt_0_9
+    U_CNT_HOR_UNITS : counter
+        generic map ( MAX_LIMIT => "1001" ) -- To 9
         port map (
             CLK       => CLK,
             RST       => hour_reset,
             CE        => tc_mt,
+            PE => BTN_LOAD(2),
+            DIN => SW_DIN,
             TC        => tc_hu,
             COUNT_OUT => sig_h_units
         );
 
     -- HOURS TENS (0-2)
-    U_CNT_HOR_TENS : cnt_0_2
+    U_CNT_HOR_TENS : counter
+        generic map ( MAX_LIMIT => "0010" ) -- To 2
         port map (
             CLK       => CLK,
             RST       => hour_reset,
             CE        => tc_hu,
+            PE => BTN_LOAD(3),
+            DIN => SW_DIN,
             TC        => open,
             COUNT_OUT => sig_h_tens
         );
@@ -159,13 +190,13 @@ begin
         
     U_DEC_ANODES : decoder_an
         port map (
-            SEL    => s_cnt_2bit, -- 2-bitový signál 
-            ANODES => ANODS       -- Výstupný port top modulu
+            SEL    => s_cnt_2bit,
+            ANODES => ANODS  
         );
 
     U_MUX : mux
         port map (
-            I0 => sig_m_units, -- Corrected signal names
+	        I0 => sig_m_units,
             I1 => sig_m_tens,
             I2 => sig_h_units,
             I3 => sig_h_tens,

project_7/project_5.xpr

@@ -0,0 +1,302 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2022.2 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="61" Path="C:/Users/student/Documents/priecinok/project_7/project_5.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="e38d1a4c4a2f4256841e587df17ee164"/>
+    <Option Name="Part" Val="xc7a35tcpg236-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2022.2"/>
+    <Option Name="SimulatorVersionModelSim" Val="2022.2"/>
+    <Option Name="SimulatorVersionQuesta" Val="2022.2"/>
+    <Option Name="SimulatorVersionXcelium" Val="21.09.009"/>
+    <Option Name="SimulatorVersionVCS" Val="S-2021.09"/>
+    <Option Name="SimulatorVersionRiviera" Val="2022.04"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="13.0"/>
+    <Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+    <Option Name="TargetLanguage" Val="VHDL"/>
+    <Option Name="SimulatorLanguage" Val="VHDL"/>
+    <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
+    <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../AppData/Roaming/Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="EnableResourceEstimation" Val="FALSE"/>
+    <Option Name="SimCompileState" Val="TRUE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSABoardId" Val="basys3"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+    <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/new/counter.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/counter_2bit.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/dec2.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/decoder_bottom.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/divider.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/divider_400Hz.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/mux.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/top_modul.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/counter_hour_tens.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/counter_minute_tens.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/counter_ones.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="top_modul"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PSRCDIR/constrs_1/new/projekt_5.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/constrs_1/imports/Downloads/Basys-3-Master.xdc">
+        <FileInfo>
+          <Attr Name="ImportPath" Val="$PPRDIR/../../../Downloads/Basys-3-Master.xdc"/>
+          <Attr Name="ImportTime" Val="1771253458"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="top_modul"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <File Path="$PSRCDIR/utils_1/imports/synth_1/top_modul.dcp">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedInSteps" Val="synth_1"/>
+          <Attr Name="AutoDcp" Val="1"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="19">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top_modul.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board>
+    <Jumpers/>
+  </Board>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>