38 lines
901 B
VHDL
38 lines
901 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity cnt_0_9 is
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Port ( CLK : in STD_LOGIC;
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CE : in STD_LOGIC;
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RST : in STD_LOGIC;
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TC : out STD_LOGIC;
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COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
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end cnt_0_9;
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architecture Behavioral of cnt_0_9 is
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-- Internal signal to keep track of the current number
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signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
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begin
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process(CLK)
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begin
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if rising_edge(CLK) then
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if RST = '1' then
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s_cnt <= "0000";
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elsif CE = '1' then
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if s_cnt = "1001" then -- If we are at 9
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s_cnt <= "0000"; -- Reset to 0
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else
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s_cnt <= s_cnt + 1;
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end if;
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end if;
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end if;
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end process;
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COUNT_OUT <= s_cnt;
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end Behavioral;
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