issue fixed, needs some redesign tho

.gitignore

@@ -29,3 +29,5 @@
 # Windows specific
 Thumbs.db
 Desktop.ini
+
+project_7/hx.exe

project_7/project_5.srcs/constrs_1/imports/Downloads/Basys-3-Master.xdc

@@ -13,15 +13,17 @@ set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports {RST}]
 set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports {START}]
 
 set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports {SW_MODE}]
-#set_property -dict { PACKAGE_PIN W17   IOSTANDARD LVCMOS33 } [get_ports {sw[3]}]
-#set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports {sw[4]}]
+set_property -dict { PACKAGE_PIN W17   IOSTANDARD LVCMOS33 } [get_ports {SW_STOP_SET}]
+set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports {SW_ALARM_SET}]
 #set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports {sw[5]}]
 #set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports {sw[6]}]
 #set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports {sw[7]}]
-#set_property -dict { PACKAGE_PIN V2    IOSTANDARD LVCMOS33 } [get_ports {sw[8]}]
-#set_property -dict { PACKAGE_PIN T3    IOSTANDARD LVCMOS33 } [get_ports {sw[9]}]
-#set_property -dict { PACKAGE_PIN T2    IOSTANDARD LVCMOS33 } [get_ports {sw[10]}]
-#set_property -dict { PACKAGE_PIN R3    IOSTANDARD LVCMOS33 } [get_ports {sw[11]}]
+#set_property -dict { PACKAGE_PIN V2    IOSTANDARD LVCMOS33 } [get_ports {RST_B}]
+#set_property -dict { PACKAGE_PIN T3    IOSTANDARD LVCMOS33 } [get_ports {RST_C}]
+# Stopky
+set_property -dict { PACKAGE_PIN T2    IOSTANDARD LVCMOS33 } [get_ports {RST_C}]
+# Budik 
+set_property -dict { PACKAGE_PIN R3    IOSTANDARD LVCMOS33 } [get_ports {RST_B}]
 set_property -dict { PACKAGE_PIN W2    IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[0]}]
 set_property -dict { PACKAGE_PIN U1    IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[1]}]
 set_property -dict { PACKAGE_PIN T1    IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[2]}]
@@ -29,7 +31,7 @@ set_property -dict { PACKAGE_PIN R2    IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[
 
 
 ## LEDs
-#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports {led[0]}]
+set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports {ALARM_LED}]
 #set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS33 } [get_ports {led[1]}]
 #set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports {led[2]}]
 #set_property -dict { PACKAGE_PIN V19   IOSTANDARD LVCMOS33 } [get_ports {led[3]}]

project_7/project_5.srcs/sources_1/new/clock_logic.vhd

@@ -4,21 +4,13 @@
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
 
 entity clock_logic is
     Port ( 
         CLK        : in  STD_LOGIC;
         RST        : in  STD_LOGIC;
         CE_1HZ     : in  STD_LOGIC; -- Enable signal from the divider
-        SW_DIN     : in  STD_LOGIC_VECTOR (3 downto 0);
+        SW_DIN     : in  STD_LOGIC_VECTOR (3 downto 0); -- set data on btn_load
         BTN_LOAD   : in  STD_LOGIC_VECTOR (3 downto 0);
         -- Outputs to the top module/display
         S_UNITS    : out STD_LOGIC_VECTOR (3 downto 0);
@@ -32,7 +24,8 @@ end clock_logic;
 
 
 architecture Behavioral of clock_logic is
-	component counter is
+    -- TODO CHECK AGAINST COUNTER.VHD IF NEEDED
+    component counter is
 	    Generic ( MAX_LIMIT : STD_LOGIC_VECTOR(3 downto 0) := "1001" ); -- Default to 9
         Port ( CLK : in STD_LOGIC;
                CE : in STD_LOGIC;
@@ -43,8 +36,8 @@ architecture Behavioral of clock_logic is
                COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
     end component;
 
-	-- Internal signals to connect the counters
-	signal sig_s_units, sig_s_tens  : std_logic_vector(3 downto 0);
+	  -- Internal signals to connect the counters
+	  signal sig_s_units, sig_s_tens  : std_logic_vector(3 downto 0);
     signal sig_m_units, sig_m_tens : std_logic_vector(3 downto 0);
     signal sig_h_units, sig_h_tens : std_logic_vector(3 downto 0);
     -- Carry signals (TC)
@@ -84,18 +77,26 @@ begin
     U_CNT_SEC_UNITS : counter
         generic map ( MAX_LIMIT => "1001" ) -- do 9
         port map (
-            CLK => CLK, RST => RST, CE => CE_1HZ,
-            PE => '0', DIN => "0000", -- Seconds usually don't need manual load
-            TC => tc_su, COUNT_OUT => sig_s_units
+            CLK => CLK,
+            RST => RST,
+            CE => CE_1HZ,
+            PE => '0',
+            DIN => "0000", -- Seconds usually don't need manual load
+            TC => tc_su,
+            COUNT_OUT => sig_s_units
         );
 
     -- SECONDS TENS (0-5) - Triggered when Sec Units reach 9
     U_CNT_SEC_TENS : counter
         generic map ( MAX_LIMIT => "0101" ) -- do 5
         port map (
-            CLK => CLK, RST => RST, CE => tc_su,
-            PE => '0', DIN => "0000",
-            TC => tc_st, COUNT_OUT => sig_s_tens
+            CLK => CLK,
+            RST => RST,
+            CE => tc_su,
+            PE => '0',
+            DIN => "0000",
+            TC => tc_st,
+            COUNT_OUT => sig_s_tens
         );
 
     -------------------------------------------------------
@@ -134,8 +135,15 @@ begin
     begin
         if RST = '1' then
             hour_reset <= '1';
+        -- TICK: If clock is at 23:59:59 and the minutes tick over
         elsif (sig_h_tens = "0010" and sig_h_units = "0011" and tc_mt = '1') then
             hour_reset <= '1';
+        -- LOAD PROTECTION: If current value is 24:XX or higher
+        -- This part works even if tc_mt is '0' (for the alarm)
+        elsif (sig_h_tens = "0010" and sig_h_units >= "0100") then
+            hour_reset <= '1'; 
+        elsif (sig_h_tens > "0010") then
+            hour_reset <= '1'; 
         else
             hour_reset <= '0';
         end if;

project_7/project_5.srcs/sources_1/new/counter.vhd

@@ -1,37 +1,9 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 09.03.2026 15:14:35
--- Design Name: 
--- Module Name: counter - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
+-- project_7/project_5.srcs/sources_1/new/counter.vhd
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
 entity counter is
     Generic ( MAX_LIMIT : STD_LOGIC_VECTOR(3 downto 0) := "1001" ); -- Default to 9
     Port ( CLK : in STD_LOGIC;
@@ -71,4 +43,4 @@ begin
 
     COUNT_OUT <= s_cnt;
 
-end Behavioral;
+end Behavioral;

project_7/project_5.srcs/sources_1/new/display_drive.vhd

@@ -4,14 +4,6 @@
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
 
 entity display_driver is
     Port ( 

project_7/project_5.srcs/sources_1/new/top_modul.vhd

@@ -8,10 +8,16 @@ entity top_modul is
            RST : in STD_LOGIC;
            START : in STD_LOGIC;
            SW_MODE  : in  STD_LOGIC; -- '0' = HH:MM, '1' = MM:SS
+           SW_ALARM_SET  : in  STD_LOGIC; -- '0' = Display Clock, '1' = Set Alarm
+           SW_STOP_SET  : in  STD_LOGIC; -- '0' = Display Clock, '1' = Set Stopky
            SW_DIN   : in STD_LOGIC_VECTOR (3 downto 0); -- Value to set
            BTN_LOAD : in STD_LOGIC_VECTOR (3 downto 0); -- Which digit to set
+           RST_B : in STD_LOGIC;
+           RST_C : in STD_LOGIC;
            SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
-           ANODS : out STD_LOGIC_VECTOR (3 downto 0));
+           ANODS : out STD_LOGIC_VECTOR (3 downto 0);
+           ALARM_LED : out STD_LOGIC -- LED lights up when alarm triggers
+        ); 
 end top_modul;
 
 architecture Behavioral of top_modul is
@@ -31,14 +37,36 @@ architecture Behavioral of top_modul is
     signal clk_400_Hz : std_logic;
     signal s_ce_units   : std_logic;
     
-    -- You MUST declare these signals so top_modul can carry data between the two submodules
+    -- Top_modul can carry data between the two submodules thanks to this
     signal sig_s_units, sig_s_tens : std_logic_vector(3 downto 0);
     signal sig_m_units, sig_m_tens : std_logic_vector(3 downto 0);
     signal sig_h_units, sig_h_tens : std_logic_vector(3 downto 0);
+
+    -- Alarm display clock
+    signal alrm_s_units, alrm_s_tens : std_logic_vector(3 downto 0);
+    signal alrm_m_units, alrm_m_tens : std_logic_vector(3 downto 0);
+    signal alrm_h_units, alrm_h_tens : std_logic_vector(3 downto 0);
+
+    -- stopky clock
+    signal stop_s_units, stop_s_tens : std_logic_vector(3 downto 0);
+    signal stop_m_units, stop_m_tens : std_logic_vector(3 downto 0);
+    signal stop_h_units, stop_h_tens : std_logic_vector(3 downto 0);
+    -- cap stopky clock
+    signal cap_s_units, cap_s_tens : std_logic_vector(3 downto 0);
+    signal cap_m_units, cap_m_tens : std_logic_vector(3 downto 0);
+    signal cap_h_units, cap_h_tens : std_logic_vector(3 downto 0);
     
     -- Signals to send to the display
     signal d0, d1, d2, d3 : std_logic_vector(3 downto 0);
 
+    signal load_clock : std_logic_vector(3 downto 0);
+    signal load_alarm : std_logic_vector(3 downto 0);
+    signal load_stopky : std_logic_vector(3 downto 0);
+
+    -- stopky ci behaju
+    signal stops_running : std_logic := '0';
+    signal stops_reset: std_logic := '0';
+    signal sw_stop_prev : std_logic := '0';
 begin
 
     U_DIV_1HZ : divider
@@ -56,7 +84,8 @@ begin
         );
 
     s_ce_units <= clk_1_Hz and START;
-
+    load_clock <= BTN_LOAD when SW_ALARM_SET = '0' else "0000";
+    load_alarm <= BTN_LOAD when SW_ALARM_SET = '1' else "0000";
     -- Clock Engine submodule
     U_CLOCK_CORE : entity work.clock_logic
         port map (
@@ -64,7 +93,7 @@ begin
             RST      => RST,
             CE_1HZ   => s_ce_units,
             SW_DIN   => SW_DIN,
-            BTN_LOAD => BTN_LOAD,
+            BTN_LOAD => load_clock,
             S_UNITS  => sig_s_units,
             S_TENS   => sig_s_tens,
             M_UNITS  => sig_m_units,
@@ -73,12 +102,124 @@ begin
             H_TENS   => sig_h_tens
         );
 
-    -- Mode Multiplexing
-    -- If SW_MODE = '1', show MM:SS. If '0', show HH:MM.
-    d0 <= sig_s_units when SW_MODE = '1' else sig_m_units;
-    d1 <= sig_s_tens  when SW_MODE = '1' else sig_m_tens;
-    d2 <= sig_m_units when SW_MODE = '1' else sig_h_units;
-    d3 <= sig_m_tens  when SW_MODE = '1' else sig_h_tens;
+    -- Clock Engine submodule for alarm
+    U_ALARM_CORE : entity work.clock_logic
+        port map (
+            CLK      => CLK,
+            RST      => RST,
+            CE_1HZ   => '0',
+            SW_DIN   => SW_DIN,
+            BTN_LOAD => load_alarm,
+            S_UNITS  => alrm_s_units,
+            S_TENS   => alrm_s_tens,
+            M_UNITS  => alrm_m_units,
+            M_TENS   => alrm_m_tens,
+            H_UNITS  => alrm_h_units,
+            H_TENS   => alrm_h_tens
+        );
+
+    stops_running  <= s_ce_units;
+    stops_reset <= RST or RST_C;
+    -- Clock Engine submodule for stopky
+    U_STOPKY_CORE : entity work.clock_logic
+        port map (
+            CLK      => CLK,
+            RST      => stops_reset,
+            CE_1HZ   => stops_running,
+            SW_DIN   => "0000",
+            BTN_LOAD => "0000",
+            S_UNITS  => stop_s_units,
+            S_TENS   => stop_s_tens,
+            M_UNITS  => stop_m_units,
+            M_TENS   => stop_m_tens,
+            H_UNITS  => stop_h_units,
+            H_TENS   => stop_h_tens
+        );
+
+    -- Comparator Logic for alarm LED to be ON or OFF
+    -- TODO BUG proste niekedy na zaciatku ledka svieti aj ked ma byt zhasnuta
+    process(CLK)
+    begin
+        if rising_edge(CLK) then
+            sw_stop_prev <= SW_STOP_SET;
+            -- alarm
+            if RST = '1' or RST_B = '1' then
+                ALARM_LED <= '0';
+            -- Match condition (HH:MM)
+            elsif (START = '1' and 
+                sig_h_tens = alrm_h_tens and sig_h_units = alrm_h_units and
+                sig_m_tens = alrm_m_tens and sig_m_units = alrm_m_units and
+                sig_s_tens = "0000" and sig_s_units = "0000") then
+                ALARM_LED <= '1';
+            end if;
+            if RST = '1' or RST_C = '1' then
+                cap_s_units <= "0000";
+                cap_s_tens  <= "0000";
+                cap_m_units <= "0000";
+                cap_m_tens  <= "0000";
+                cap_h_units <= "0000";
+                cap_h_tens  <= "0000";
+            elsif SW_STOP_SET = '1' and sw_stop_prev = '0' then 
+                cap_s_units <= stop_s_units;
+                cap_s_tens  <= stop_s_tens;
+                cap_m_units <= stop_m_units;
+                cap_m_tens  <= stop_m_tens;
+                cap_h_units <= stop_h_units;
+                cap_h_tens  <= stop_h_tens;
+            end if;
+        end if;
+    end process;
+
+    -- -- Mode Multiplexing
+    -- -- If SW_MODE = '1', show MM:SS. If '0', show HH:MM.
+    -- d0 <= sig_s_units when SW_MODE = '1' else sig_m_units;
+    -- d1 <= sig_s_tens  when SW_MODE = '1' else sig_m_tens;
+    -- d2 <= sig_m_units when SW_MODE = '1' else sig_h_units;
+    -- d3 <= sig_m_tens  when SW_MODE = '1' else sig_h_tens;
+
+    -- Mode Multiplexing (4 digit display)
+    process(SW_ALARM_SET, SW_MODE, 
+            sig_s_units, sig_s_tens, sig_m_units, sig_m_tens, sig_h_units, sig_h_tens,
+            alrm_m_units, alrm_m_tens, alrm_h_units, alrm_h_tens, stop_s_units, stop_s_tens,
+            stop_m_units, stop_m_tens, stop_h_units, stop_h_tens )
+    begin
+        if SW_ALARM_SET = '1' then
+            -- While setting alarm, always show Alarm HH:MM
+            d0 <= alrm_m_units;
+            d1 <= alrm_m_tens;
+            d2 <= alrm_h_units;
+            d3 <= alrm_h_tens;
+        elsif SW_STOP_SET = '1' then
+            if SW_MODE = '1' then
+                -- Stopky (MM:SS)
+                d0 <= cap_s_units;
+                d1 <= cap_s_tens;
+                d2 <= cap_m_units;
+                d3 <= cap_m_tens;
+            else
+                -- Stopky (HH:MM)
+                d0 <= cap_m_units;
+                d1 <= cap_m_tens;
+                d2 <= cap_h_units;
+                d3 <= cap_h_tens;
+            end if;
+        else
+            -- Normal Operation
+            if SW_MODE = '1' then
+                -- Show Seconds and Minutes (MM:SS)
+                d0 <= sig_s_units;
+                d1 <= sig_s_tens;
+                d2 <= sig_m_units;
+                d3 <= sig_m_tens;
+            else
+                -- Show Minutes and Hours (HH:MM)
+                d0 <= sig_m_units;
+                d1 <= sig_m_tens;
+                d2 <= sig_h_units;
+                d3 <= sig_h_tens;
+            end if;
+        end if;
+    end process;
     
     U_DISPLAY : entity work.display_driver
         port map (

project_7/project_5.xpr

@@ -177,6 +177,7 @@
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="top_modul"/>
         <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="dataflowViewerSettings" Val="min_width=16"/>
       </Config>
     </FileSet>
     <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">

vhdl_ls.toml

@@ -0,0 +1,7 @@
+[libraries]
+ieee.files = [
+]
+
+work.files = [
+    "project_*/**/*.vhd",
+]