aj obrazok

project_5/project_5.srcs/sources_1/new/top_modul.vhd

@@ -52,10 +52,35 @@ architecture Behavioral of top_modul is
                RST : in STD_LOGIC;
                CLK_400_Hz : out STD_LOGIC); -- This will be our enable pulse
     end component;
+    
+    component counter is
+        Port ( CLK : in STD_LOGIC;
+               RST : in STD_LOGIC;
+               CE : in STD_LOGIC;
+               TC : out STD_LOGIC;
+               COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
+    end component;
+    
+    component counter_2bit is
+        Port ( CLK : in STD_LOGIC;
+               RST : in STD_LOGIC;
+               COUNT_OUT : out STD_LOGIC_VECTOR (1 downto 0));
+    end component;
+
+    component decoder_an is
+        Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0);
+               ANODES : out STD_LOGIC_VECTOR (1 downto 0));
+    end component;
 
     signal clk_1_Hz   : std_logic;
     signal clk_400_Hz : std_logic;
     
+    signal s_tc_units   : std_logic; -- Wire connecting Top TC to Bottom CE
+    signal s_cnt_units  : std_logic_vector(3 downto 0); -- To MUX I0
+    signal s_cnt_tens   : std_logic_vector(3 downto 0); -- To MUX I1
+    
+    signal s_cnt_2bit   : std_logic_vector(1 downto 0);
+        
 begin
 
     U_DIV : divider
@@ -72,4 +97,39 @@ begin
             RST => RST,
             CLK_400_Hz => clk_400_Hz
         );
+ 
+    -- TOP COUNTER (Units)
+    U_CNT_TOP : counter
+        port map (
+            CLK       => CLK,
+            RST       => RST,
+            CE        => START, 
+            TC        => s_tc_units,             
+            COUNT_OUT => s_cnt_units             
+        );
+
+    -- BOTTOM COUNTER (Tens)
+    U_CNT_BOTTOM : counter
+        port map (
+            CLK       => CLK,
+            RST       => RST,
+            CE        => s_tc_units, -- Increments only when top counter hits 9
+            TC        => open,       -- Free TC
+            COUNT_OUT => s_cnt_tens  
+        );
+
+    U_CNT_2BIT : counter_2bit
+        port map (
+            CLK       => clk_400_Hz,
+            RST       => RST,
+            COUNT_OUT => s_cnt_2bit
+        );      
+        
+    U_DEC_ANODES : decoder_an
+        port map (
+            SEL    => s_cnt_2bit, -- 2-bitov<6F> sign<67>l 
+            ANODES => ANODS       -- V<>stupn<70> port top modulu
+        );
+        
+                
 end Behavioral;