diff --git a/project_5/project_5.srcs/sources_1/new/counter.vhd b/project_5/project_5.srcs/sources_1/new/counter.vhd index 37c930a..9a57fab 100644 --- a/project_5/project_5.srcs/sources_1/new/counter.vhd +++ b/project_5/project_5.srcs/sources_1/new/counter.vhd @@ -21,6 +21,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values @@ -40,8 +41,32 @@ entity counter is end counter; architecture Behavioral of counter is - + -- Internal signal to keep track of the current number + signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000"; begin + -- Main counting logic + process(CLK) + begin + if rising_edge(CLK) then + if RST = '1' then + s_cnt <= "0000"; + elsif CE = '1' then + if s_cnt = "1001" then -- If we are at 9 + s_cnt <= "0000"; -- Reset to 0 + else + s_cnt <= s_cnt + 1; -- Increment + end if; + end if; + end if; + end process; -end Behavioral; + -- Terminal Count logic (The red line connection) + -- TC is '1' ONLY when we are at 9 AND the enable pulse is active. + -- This ensures the next counter only moves once per rollover. + TC <= '1' when (s_cnt = "1001" and CE = '1') else '0'; + + -- Drive the output ports + COUNT_OUT <= s_cnt; + +end Behavioral; \ No newline at end of file diff --git a/project_5/project_5.srcs/sources_1/new/counter_2bit.vhd b/project_5/project_5.srcs/sources_1/new/counter_2bit.vhd new file mode 100644 index 0000000..ef0218f --- /dev/null +++ b/project_5/project_5.srcs/sources_1/new/counter_2bit.vhd @@ -0,0 +1,55 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09.03.2026 15:32:13 +-- Design Name: +-- Module Name: counter_2bit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity counter_2bit is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + COUNT_OUT : out STD_LOGIC_VECTOR (1 downto 0)); +end counter_2bit; + +architecture Behavioral of counter_2bit is + + signal s_cnt : STD_LOGIC_VECTOR(1 downto 0) := "00"; +begin + process(CLK, RST) + begin + if RST = '1' then + s_cnt <= "00"; + elsif rising_edge(CLK) then + s_cnt <= s_cnt + 1; + end if; + end process; + COUNT_OUT <= s_cnt; + +end Behavioral; diff --git a/project_5/project_5.srcs/sources_1/new/decoder_bottom.vhd b/project_5/project_5.srcs/sources_1/new/decoder_bottom.vhd new file mode 100644 index 0000000..9538c15 --- /dev/null +++ b/project_5/project_5.srcs/sources_1/new/decoder_bottom.vhd @@ -0,0 +1,50 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09.03.2026 15:39:11 +-- Design Name: +-- Module Name: decoder_bottom - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity decoder_an is + Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0); + ANODES : in STD_LOGIC_VECTOR (3 downto 0)); +end decoder_an; + +architecture Behavioral of decoder_an is + +begin + with SEL select + ANODES <= "1000" when "00", + "0100" when "01", + "0010" when "10", + "0001" when "11", + "0000" when others; + +end Behavioral; diff --git a/project_5/project_5.srcs/sources_1/new/top_modul.vhd b/project_5/project_5.srcs/sources_1/new/top_modul.vhd index d769908..4166aeb 100644 --- a/project_5/project_5.srcs/sources_1/new/top_modul.vhd +++ b/project_5/project_5.srcs/sources_1/new/top_modul.vhd @@ -52,10 +52,35 @@ architecture Behavioral of top_modul is RST : in STD_LOGIC; CLK_400_Hz : out STD_LOGIC); -- This will be our enable pulse end component; + + component counter is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + CE : in STD_LOGIC; + TC : out STD_LOGIC; + COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)); + end component; + + component counter_2bit is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + COUNT_OUT : out STD_LOGIC_VECTOR (1 downto 0)); + end component; + + component decoder_an is + Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0); + ANODES : out STD_LOGIC_VECTOR (1 downto 0)); + end component; signal clk_1_Hz : std_logic; signal clk_400_Hz : std_logic; + signal s_tc_units : std_logic; -- Wire connecting Top TC to Bottom CE + signal s_cnt_units : std_logic_vector(3 downto 0); -- To MUX I0 + signal s_cnt_tens : std_logic_vector(3 downto 0); -- To MUX I1 + + signal s_cnt_2bit : std_logic_vector(1 downto 0); + begin U_DIV : divider @@ -72,4 +97,39 @@ begin RST => RST, CLK_400_Hz => clk_400_Hz ); + + -- TOP COUNTER (Units) + U_CNT_TOP : counter + port map ( + CLK => CLK, + RST => RST, + CE => START, + TC => s_tc_units, + COUNT_OUT => s_cnt_units + ); + + -- BOTTOM COUNTER (Tens) + U_CNT_BOTTOM : counter + port map ( + CLK => CLK, + RST => RST, + CE => s_tc_units, -- Increments only when top counter hits 9 + TC => open, -- Free TC + COUNT_OUT => s_cnt_tens + ); + + U_CNT_2BIT : counter_2bit + port map ( + CLK => clk_400_Hz, + RST => RST, + COUNT_OUT => s_cnt_2bit + ); + + U_DEC_ANODES : decoder_an + port map ( + SEL => s_cnt_2bit, -- 2-bitový signál + ANODES => ANODS -- Výstupný port top modulu + ); + + end Behavioral; diff --git a/project_5/project_5.xpr b/project_5/project_5.xpr index 7ae0512..edc233d 100644 --- a/project_5/project_5.xpr +++ b/project_5/project_5.xpr @@ -92,6 +92,24 @@ + + + + + + + + + + + + + + + + + + @@ -110,13 +128,6 @@ - - - - - - -