136 lines
3.6 KiB
VHDL
136 lines
3.6 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 09.03.2026 14:40:14
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-- Design Name:
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-- Module Name: top_modul - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity top_modul is
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Port ( CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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START : in STD_LOGIC;
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SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
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ANODS : out STD_LOGIC_VECTOR (3 downto 0));
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end top_modul;
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architecture Behavioral of top_modul is
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component divider is
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Port ( CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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CLK_1_Hz : out STD_LOGIC); -- This will be our enable pulse
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end component;
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component divider_400Hz is
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Port ( CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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CLK_400_Hz : out STD_LOGIC); -- This will be our enable pulse
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end component;
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component counter is
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Port ( CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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CE : in STD_LOGIC;
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TC : out STD_LOGIC;
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COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
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end component;
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component counter_2bit is
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Port ( CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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COUNT_OUT : out STD_LOGIC_VECTOR (1 downto 0));
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end component;
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component decoder_an is
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Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0);
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ANODES : out STD_LOGIC_VECTOR (1 downto 0));
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end component;
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signal clk_1_Hz : std_logic;
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signal clk_400_Hz : std_logic;
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signal s_tc_units : std_logic; -- Wire connecting Top TC to Bottom CE
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signal s_cnt_units : std_logic_vector(3 downto 0); -- To MUX I0
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signal s_cnt_tens : std_logic_vector(3 downto 0); -- To MUX I1
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signal s_cnt_2bit : std_logic_vector(1 downto 0);
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begin
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U_DIV : divider
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port map (
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CLK => CLK,
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RST => RST,
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CLK_1_Hz => clk_1_Hz
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);
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U_DIV_400Hz : divider_400Hz
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port map (
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CLK => CLK,
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RST => RST,
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CLK_400_Hz => clk_400_Hz
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);
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-- TOP COUNTER (Units)
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U_CNT_TOP : counter
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port map (
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CLK => CLK,
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RST => RST,
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CE => START,
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TC => s_tc_units,
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COUNT_OUT => s_cnt_units
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);
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-- BOTTOM COUNTER (Tens)
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U_CNT_BOTTOM : counter
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port map (
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CLK => CLK,
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RST => RST,
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CE => s_tc_units, -- Increments only when top counter hits 9
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TC => open, -- Free TC
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COUNT_OUT => s_cnt_tens
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);
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U_CNT_2BIT : counter_2bit
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port map (
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CLK => clk_400_Hz,
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RST => RST,
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COUNT_OUT => s_cnt_2bit
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);
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U_DEC_ANODES : decoder_an
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port map (
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SEL => s_cnt_2bit, -- 2-bitov<6F> sign<67>l
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ANODES => ANODS -- V<>stupn<70> port top modulu
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);
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end Behavioral;
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