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project_4/project_4.srcs/sources_1/new/top_modul.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09.03.2026 13:07:50
+-- Design Name: 
+-- Module Name: top_modul - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top_modul is
+    Port ( CLK : in STD_LOGIC;
+           RST : in STD_LOGIC;
+           START_PAUSE : in STD_LOGIC;
+           LED_UNITS : out STD_LOGIC_VECTOR (3 downto 0);
+           LED_TENS : out STD_LOGIC_VECTOR (3 downto 0));
+end top_modul;
+
+
+architecture Behavioral of top_modul is
+
+    -- 1. Component Declarations
+    component divider is
+        Port ( CLK : in STD_LOGIC;
+               RST : in STD_LOGIC;
+               CLK_1_Hz : out STD_LOGIC); -- This will be our enable pulse
+    end component;
+
+    component counter is
+        Port ( CLK : in STD_LOGIC;
+               RST : in STD_LOGIC;
+               CE : in std_logic;
+               TC : out std_logic; -- Terminal Count for cascading
+               COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
+    end component;
+
+    -- 2. Internal "Wires"
+    signal s_1hz_tick : std_logic;
+    signal s_tc_units : std_logic;
+
+begin
+
+    -- 3. Block Instantiation & Wiring
+    U_DIV : divider
+        port map (
+            CLK => CLK,
+            RST => RST,
+            CLK_1_Hz => s_1hz_tick
+        );
+
+    -- Units Counter (First CNT in diagram)
+    U_CNT_UNITS : counter
+        port map (
+            CLK => CLK,
+            RST => RST,
+            CE => (s_1hz_tick and START_PAUSE), -- Input from DIV + Switch
+            TC => s_tc_units,                   -- Output to next counter
+            COUNT_OUT => LED_UNITS
+        );
+
+    -- Tens Counter (Second CNT in diagram)
+    U_CNT_TENS : counter
+        port map (
+            CLK => CLK,
+            RST => RST,
+            -- Increments ONLY when Units rolls over (TC) AND 1Hz pulse is there
+            CE => s_tc_units, 
+            TC => open, -- We don't need TC for the last digit
+            COUNT_OUT => LED_TENS
+        );
+
+end Behavioral;