From ab832ecd86292bc6c22636485d61805f9edca1d1 Mon Sep 17 00:00:00 2001 From: filipriec skolsky PC Date: Mon, 9 Mar 2026 14:04:49 +0100 Subject: [PATCH] hod4 a --- .../imports/Downloads/Basys-3-Master.xdc | 158 ++++++++++++++++++ .../project_4.srcs/sources_1/new/counter.vhd | 73 ++++++++ .../project_4.srcs/sources_1/new/divider.vhd | 62 +++++++ .../sources_1/new/top_modul.vhd | 95 +++++++++++ project_4/project_4.xpr | 43 ++++- 5 files changed, 429 insertions(+), 2 deletions(-) create mode 100644 project_4/project_4.srcs/constrs_1/imports/Downloads/Basys-3-Master.xdc create mode 100644 project_4/project_4.srcs/sources_1/new/counter.vhd create mode 100644 project_4/project_4.srcs/sources_1/new/divider.vhd create mode 100644 project_4/project_4.srcs/sources_1/new/top_modul.vhd diff --git a/project_4/project_4.srcs/constrs_1/imports/Downloads/Basys-3-Master.xdc b/project_4/project_4.srcs/constrs_1/imports/Downloads/Basys-3-Master.xdc new file mode 100644 index 0000000..386c166 --- /dev/null +++ b/project_4/project_4.srcs/constrs_1/imports/Downloads/Basys-3-Master.xdc @@ -0,0 +1,158 @@ +## This file is a general .xdc for the Basys3 rev B board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal +set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports CLK] +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK] + +## Switches +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {START_PAUSE}] +#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {sw[1]}] +#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {sw[2]}] +#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports {sw[3]}] +#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {sw[4]}] +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports {sw[5]}] +#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports {sw[6]}] +#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports {sw[7]}] +#set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports {sw[8]}] +#set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports {sw[9]}] +#set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports {sw[10]}] +#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {sw[11]}] +#set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports {sw[12]}] +#set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports {sw[13]}] +#set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {sw[14]}] +#set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {sw[15]}] + + +## LEDs +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports {LED_UNITS[0]}] +set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports {LED_UNITS[1]}] +set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports {LED_UNITS[2]}] +set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports {LED_UNITS[3]}] +set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports {LED_TENS[0]}] +set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports {LED_TENS[1]}] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports {LED_TENS[2]}] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports {LED_TENS[3]}] +#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports {led[8]}] +#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports {led[9]}] +#set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports {led[10]}] +#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports {led[11]}] +#set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports {led[12]}] +#set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports {led[13]}] +#set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports {led[14]}] +#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports {led[15]}] + + +##7 Segment Display +#set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports {seg[0]}] +#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports {seg[1]}] +#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports {seg[2]}] +#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports {seg[3]}] +#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports {seg[4]}] +#set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports {seg[5]}] +#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports {seg[6]}] + +#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports dp] + +#set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports {an[0]}] +#set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports {an[1]}] +#set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports {an[2]}] +#set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports {an[3]}] + + +##Buttons +set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports RST] +#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports btnU] +#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports btnL] +#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports btnR] +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports btnD] + + +##Pmod Header JA +#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports {JA[0]}];#Sch name = JA1 +#set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports {JA[1]}];#Sch name = JA2 +#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports {JA[2]}];#Sch name = JA3 +#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports {JA[3]}];#Sch name = JA4 +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports {JA[4]}];#Sch name = JA7 +#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports {JA[5]}];#Sch name = JA8 +#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports {JA[6]}];#Sch name = JA9 +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports {JA[7]}];#Sch name = JA10 + +##Pmod Header JB +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports {JB[0]}];#Sch name = JB1 +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports {JB[1]}];#Sch name = JB2 +#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports {JB[2]}];#Sch name = JB3 +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports {JB[3]}];#Sch name = JB4 +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports {JB[4]}];#Sch name = JB7 +#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports {JB[5]}];#Sch name = JB8 +#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports {JB[6]}];#Sch name = JB9 +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports {JB[7]}];#Sch name = JB10 + +##Pmod Header JC +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports {JC[0]}];#Sch name = JC1 +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports {JC[1]}];#Sch name = JC2 +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports {JC[2]}];#Sch name = JC3 +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports {JC[3]}];#Sch name = JC4 +#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports {JC[4]}];#Sch name = JC7 +#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports {JC[5]}];#Sch name = JC8 +#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports {JC[6]}];#Sch name = JC9 +#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports {JC[7]}];#Sch name = JC10 + +##Pmod Header JXADC +#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[0]}];#Sch name = XA1_P +#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[1]}];#Sch name = XA2_P +#set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[2]}];#Sch name = XA3_P +#set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[3]}];#Sch name = XA4_P +#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[4]}];#Sch name = XA1_N +#set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[5]}];#Sch name = XA2_N +#set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[6]}];#Sch name = XA3_N +#set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[7]}];#Sch name = XA4_N + + +##VGA Connector +#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[0]}] +#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[1]}] +#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[2]}] +#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[3]}] +#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[0]}] +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[1]}] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[2]}] +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[3]}] +#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[0]}] +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[1]}] +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[2]}] +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[3]}] +#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports Hsync] +#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports Vsync] + + +##USB-RS232 Interface +#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports RsRx] +#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports RsTx] + + +##USB HID (PS/2) +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Clk] +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Data] + + +##Quad SPI Flash +##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the +##STARTUPE2 primitive. +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[0]}] +#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[1]}] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[2]}] +#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[3]}] +#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports QspiCSn] + + +## Configuration options, can be used for all designs +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] + +## SPI configuration mode options for QSPI boot, can be used for all designs +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] diff --git a/project_4/project_4.srcs/sources_1/new/counter.vhd b/project_4/project_4.srcs/sources_1/new/counter.vhd new file mode 100644 index 0000000..9f93a01 --- /dev/null +++ b/project_4/project_4.srcs/sources_1/new/counter.vhd @@ -0,0 +1,73 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09.03.2026 13:12:16 +-- Design Name: +-- Module Name: counter - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity counter is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + CE : in STD_LOGIC; + TC : out STD_LOGIC; + COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)); +end counter; + + +architecture Behavioral of counter is + -- Internal signal to keep track of the current number + signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000"; +begin + + -- Main counting logic + process(CLK) + begin + if rising_edge(CLK) then + if RST = '1' then + s_cnt <= "0000"; + elsif CE = '1' then + if s_cnt = "1001" then -- If we are at 9 + s_cnt <= "0000"; -- Reset to 0 + else + s_cnt <= s_cnt + 1; -- Increment + end if; + end if; + end if; + end process; + + -- Terminal Count logic (The red line connection) + -- TC is '1' ONLY when we are at 9 AND the enable pulse is active. + -- This ensures the next counter only moves once per rollover. + TC <= '1' when (s_cnt = "1001" and CE = '1') else '0'; + + -- Drive the output ports + COUNT_OUT <= s_cnt; + +end Behavioral; \ No newline at end of file diff --git a/project_4/project_4.srcs/sources_1/new/divider.vhd b/project_4/project_4.srcs/sources_1/new/divider.vhd new file mode 100644 index 0000000..87160c4 --- /dev/null +++ b/project_4/project_4.srcs/sources_1/new/divider.vhd @@ -0,0 +1,62 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09.03.2026 13:19:27 +-- Design Name: +-- Module Name: divider - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity divider is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + CLK_1_Hz : out STD_LOGIC); +end divider; + +architecture Behavioral of divider is + -- We need a 27-bit signal to hold the number 100,000,000 + signal s_cnt : STD_LOGIC_VECTOR(26 downto 0) := (others => '0'); +begin + + process(CLK) + begin + if rising_edge(CLK) then + if RST = '1' then + s_cnt <= (others => '0'); + CLK_1_Hz <= '0'; + elsif s_cnt = 99_999_999 then -- One second has passed + s_cnt <= (others => '0'); + CLK_1_Hz <= '1'; -- Send one single 'high' pulse + else + s_cnt <= s_cnt + 1; + CLK_1_Hz <= '0'; -- Stay low otherwise + end if; + end if; + end process; + +end Behavioral; \ No newline at end of file diff --git a/project_4/project_4.srcs/sources_1/new/top_modul.vhd b/project_4/project_4.srcs/sources_1/new/top_modul.vhd new file mode 100644 index 0000000..67042cd --- /dev/null +++ b/project_4/project_4.srcs/sources_1/new/top_modul.vhd @@ -0,0 +1,95 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09.03.2026 13:07:50 +-- Design Name: +-- Module Name: top_modul - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity top_modul is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + START_PAUSE : in STD_LOGIC; + LED_UNITS : out STD_LOGIC_VECTOR (3 downto 0); + LED_TENS : out STD_LOGIC_VECTOR (3 downto 0)); +end top_modul; + + +architecture Behavioral of top_modul is + + -- 1. Component Declarations + component divider is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + CLK_1_Hz : out STD_LOGIC); -- This will be our enable pulse + end component; + + component counter is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + CE : in std_logic; + TC : out std_logic; -- Terminal Count for cascading + COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)); + end component; + + -- 2. Internal "Wires" + signal s_1hz_tick : std_logic; + signal s_tc_units : std_logic; + +begin + + -- 3. Block Instantiation & Wiring + U_DIV : divider + port map ( + CLK => CLK, + RST => RST, + CLK_1_Hz => s_1hz_tick + ); + + -- Units Counter (First CNT in diagram) + U_CNT_UNITS : counter + port map ( + CLK => CLK, + RST => RST, + CE => (s_1hz_tick and START_PAUSE), -- Input from DIV + Switch + TC => s_tc_units, -- Output to next counter + COUNT_OUT => LED_UNITS + ); + + -- Tens Counter (Second CNT in diagram) + U_CNT_TENS : counter + port map ( + CLK => CLK, + RST => RST, + -- Increments ONLY when Units rolls over (TC) AND 1Hz pulse is there + CE => s_tc_units, + TC => open, -- We don't need TC for the last digit + COUNT_OUT => LED_TENS + ); + +end Behavioral; \ No newline at end of file diff --git a/project_4/project_4.xpr b/project_4/project_4.xpr index c19914c..d2e4f19 100644 --- a/project_4/project_4.xpr +++ b/project_4/project_4.xpr @@ -92,13 +92,40 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -106,6 +133,8 @@ + + + + + + + + @@ -143,18 +180,19 @@ - + Vivado Synthesis Defaults + - + Default settings for Implementation. @@ -169,6 +207,7 @@ +