alarm
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@@ -32,7 +32,8 @@ end clock_logic;
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architecture Behavioral of clock_logic is
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component counter is
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-- TODO CHECK AGAINST COUNTER.VHD IF NEEDED
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component counter is
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Generic ( MAX_LIMIT : STD_LOGIC_VECTOR(3 downto 0) := "1001" ); -- Default to 9
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Port ( CLK : in STD_LOGIC;
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CE : in STD_LOGIC;
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@@ -43,8 +44,8 @@ architecture Behavioral of clock_logic is
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COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
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end component;
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-- Internal signals to connect the counters
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signal sig_s_units, sig_s_tens : std_logic_vector(3 downto 0);
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-- Internal signals to connect the counters
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signal sig_s_units, sig_s_tens : std_logic_vector(3 downto 0);
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signal sig_m_units, sig_m_tens : std_logic_vector(3 downto 0);
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signal sig_h_units, sig_h_tens : std_logic_vector(3 downto 0);
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-- Carry signals (TC)
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@@ -84,18 +85,26 @@ begin
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U_CNT_SEC_UNITS : counter
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generic map ( MAX_LIMIT => "1001" ) -- do 9
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port map (
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CLK => CLK, RST => RST, CE => CE_1HZ,
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PE => '0', DIN => "0000", -- Seconds usually don't need manual load
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TC => tc_su, COUNT_OUT => sig_s_units
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CLK => CLK,
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RST => RST,
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CE => CE_1HZ,
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PE => '0',
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DIN => "0000", -- Seconds usually don't need manual load
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TC => tc_su,
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COUNT_OUT => sig_s_units
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);
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-- SECONDS TENS (0-5) - Triggered when Sec Units reach 9
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U_CNT_SEC_TENS : counter
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generic map ( MAX_LIMIT => "0101" ) -- do 5
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port map (
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CLK => CLK, RST => RST, CE => tc_su,
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PE => '0', DIN => "0000",
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TC => tc_st, COUNT_OUT => sig_s_tens
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CLK => CLK,
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RST => RST,
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CE => tc_su,
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PE => '0',
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DIN => "0000",
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TC => tc_st,
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COUNT_OUT => sig_s_tens
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);
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-------------------------------------------------------
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@@ -134,8 +143,15 @@ begin
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begin
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if RST = '1' then
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hour_reset <= '1';
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-- TICK: If clock is at 23:59:59 and the minutes tick over
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elsif (sig_h_tens = "0010" and sig_h_units = "0011" and tc_mt = '1') then
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hour_reset <= '1';
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-- LOAD PROTECTION: If current value is 24:XX or higher
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-- This part works even if tc_mt is '0' (for the alarm)
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elsif (sig_h_tens = "0010" and sig_h_units >= "0100") then
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hour_reset <= '1';
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elsif (sig_h_tens > "0010") then
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hour_reset <= '1';
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else
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hour_reset <= '0';
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end if;
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