From 41f88a7072a1d97197f128f71ca5ecad936e68d6 Mon Sep 17 00:00:00 2001 From: Filipriec Date: Mon, 20 Apr 2026 17:17:13 +0200 Subject: [PATCH] alarm --- .../imports/Downloads/Basys-3-Master.xdc | 3 +- .../sources_1/new/clock_logic.vhd | 34 +++++-- .../sources_1/new/top_modul.vhd | 92 +++++++++++++++++-- 3 files changed, 110 insertions(+), 19 deletions(-) diff --git a/project_7/project_5.srcs/constrs_1/imports/Downloads/Basys-3-Master.xdc b/project_7/project_5.srcs/constrs_1/imports/Downloads/Basys-3-Master.xdc index 6e71daf..3f79a32 100644 --- a/project_7/project_5.srcs/constrs_1/imports/Downloads/Basys-3-Master.xdc +++ b/project_7/project_5.srcs/constrs_1/imports/Downloads/Basys-3-Master.xdc @@ -21,7 +21,8 @@ set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {SW_MODE #set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports {sw[8]}] #set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports {sw[9]}] #set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports {sw[10]}] -#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {sw[11]}] +# Budik +set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {SW_ALARM_SET}] set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[0]}] set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[1]}] set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[2]}] diff --git a/project_7/project_5.srcs/sources_1/new/clock_logic.vhd b/project_7/project_5.srcs/sources_1/new/clock_logic.vhd index 8c047e6..70e5f24 100644 --- a/project_7/project_5.srcs/sources_1/new/clock_logic.vhd +++ b/project_7/project_5.srcs/sources_1/new/clock_logic.vhd @@ -32,7 +32,8 @@ end clock_logic; architecture Behavioral of clock_logic is - component counter is + -- TODO CHECK AGAINST COUNTER.VHD IF NEEDED + component counter is Generic ( MAX_LIMIT : STD_LOGIC_VECTOR(3 downto 0) := "1001" ); -- Default to 9 Port ( CLK : in STD_LOGIC; CE : in STD_LOGIC; @@ -43,8 +44,8 @@ architecture Behavioral of clock_logic is COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)); end component; - -- Internal signals to connect the counters - signal sig_s_units, sig_s_tens : std_logic_vector(3 downto 0); + -- Internal signals to connect the counters + signal sig_s_units, sig_s_tens : std_logic_vector(3 downto 0); signal sig_m_units, sig_m_tens : std_logic_vector(3 downto 0); signal sig_h_units, sig_h_tens : std_logic_vector(3 downto 0); -- Carry signals (TC) @@ -84,18 +85,26 @@ begin U_CNT_SEC_UNITS : counter generic map ( MAX_LIMIT => "1001" ) -- do 9 port map ( - CLK => CLK, RST => RST, CE => CE_1HZ, - PE => '0', DIN => "0000", -- Seconds usually don't need manual load - TC => tc_su, COUNT_OUT => sig_s_units + CLK => CLK, + RST => RST, + CE => CE_1HZ, + PE => '0', + DIN => "0000", -- Seconds usually don't need manual load + TC => tc_su, + COUNT_OUT => sig_s_units ); -- SECONDS TENS (0-5) - Triggered when Sec Units reach 9 U_CNT_SEC_TENS : counter generic map ( MAX_LIMIT => "0101" ) -- do 5 port map ( - CLK => CLK, RST => RST, CE => tc_su, - PE => '0', DIN => "0000", - TC => tc_st, COUNT_OUT => sig_s_tens + CLK => CLK, + RST => RST, + CE => tc_su, + PE => '0', + DIN => "0000", + TC => tc_st, + COUNT_OUT => sig_s_tens ); ------------------------------------------------------- @@ -134,8 +143,15 @@ begin begin if RST = '1' then hour_reset <= '1'; + -- TICK: If clock is at 23:59:59 and the minutes tick over elsif (sig_h_tens = "0010" and sig_h_units = "0011" and tc_mt = '1') then hour_reset <= '1'; + -- LOAD PROTECTION: If current value is 24:XX or higher + -- This part works even if tc_mt is '0' (for the alarm) + elsif (sig_h_tens = "0010" and sig_h_units >= "0100") then + hour_reset <= '1'; + elsif (sig_h_tens > "0010") then + hour_reset <= '1'; else hour_reset <= '0'; end if; diff --git a/project_7/project_5.srcs/sources_1/new/top_modul.vhd b/project_7/project_5.srcs/sources_1/new/top_modul.vhd index 087b3f8..06c5e28 100644 --- a/project_7/project_5.srcs/sources_1/new/top_modul.vhd +++ b/project_7/project_5.srcs/sources_1/new/top_modul.vhd @@ -8,10 +8,13 @@ entity top_modul is RST : in STD_LOGIC; START : in STD_LOGIC; SW_MODE : in STD_LOGIC; -- '0' = HH:MM, '1' = MM:SS + SW_ALARM_SET : in STD_LOGIC; -- '0' = Display Clock, '1' = Set Alarm SW_DIN : in STD_LOGIC_VECTOR (3 downto 0); -- Value to set BTN_LOAD : in STD_LOGIC_VECTOR (3 downto 0); -- Which digit to set SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0); - ANODS : out STD_LOGIC_VECTOR (3 downto 0)); + ANODS : out STD_LOGIC_VECTOR (3 downto 0); + ALARM_LED : out STD_LOGIC -- LED lights up when alarm triggers + ); end top_modul; architecture Behavioral of top_modul is @@ -35,10 +38,17 @@ architecture Behavioral of top_modul is signal sig_s_units, sig_s_tens : std_logic_vector(3 downto 0); signal sig_m_units, sig_m_tens : std_logic_vector(3 downto 0); signal sig_h_units, sig_h_tens : std_logic_vector(3 downto 0); + + -- Alarm display clock + signal alrm_s_units, alrm_s_tens : std_logic_vector(3 downto 0); + signal alrm_m_units, alrm_m_tens : std_logic_vector(3 downto 0); + signal alrm_h_units, alrm_h_tens : std_logic_vector(3 downto 0); -- Signals to send to the display signal d0, d1, d2, d3 : std_logic_vector(3 downto 0); + signal load_clock : std_logic_vector(3 downto 0); + signal load_alarm : std_logic_vector(3 downto 0); begin U_DIV_1HZ : divider @@ -56,7 +66,8 @@ begin ); s_ce_units <= clk_1_Hz and START; - + load_clock <= BTN_LOAD when SW_ALARM_SET = '0' else "0000"; + load_alarm <= BTN_LOAD when SW_ALARM_SET = '1' else "0000"; -- Clock Engine submodule U_CLOCK_CORE : entity work.clock_logic port map ( @@ -64,7 +75,7 @@ begin RST => RST, CE_1HZ => s_ce_units, SW_DIN => SW_DIN, - BTN_LOAD => BTN_LOAD, + BTN_LOAD => load_clock, S_UNITS => sig_s_units, S_TENS => sig_s_tens, M_UNITS => sig_m_units, @@ -73,12 +84,75 @@ begin H_TENS => sig_h_tens ); - -- Mode Multiplexing - -- If SW_MODE = '1', show MM:SS. If '0', show HH:MM. - d0 <= sig_s_units when SW_MODE = '1' else sig_m_units; - d1 <= sig_s_tens when SW_MODE = '1' else sig_m_tens; - d2 <= sig_m_units when SW_MODE = '1' else sig_h_units; - d3 <= sig_m_tens when SW_MODE = '1' else sig_h_tens; + -- Clock Engine submodule for alarm + U_ALARM_CORE : entity work.clock_logic + port map ( + CLK => CLK, + RST => RST, + CE_1HZ => '0', + SW_DIN => SW_DIN, + BTN_LOAD => load_alarm, + S_UNITS => alrm_s_units, + S_TENS => alrm_s_tens, + M_UNITS => alrm_m_units, + M_TENS => alrm_m_tens, + H_UNITS => alrm_h_units, + H_TENS => alrm_h_tens + ); + + -- Comparator Logic for alarm LED to be ON or OFF + process(CLK) + begin + if rising_edge(CLK) then + -- Match condition (HH:MM) + if (sig_h_tens = alrm_h_tens and sig_h_units = alrm_h_units and + sig_m_tens = alrm_m_tens and sig_m_units = alrm_m_units and + sig_s_tens = "0000" and sig_s_units = "0000") then + ALARM_LED <= '1'; + end if; + + -- Reset turns the alarm LED off + if RST = '1' then + ALARM_LED <= '0'; + end if; + end if; + end process; + + -- -- Mode Multiplexing + -- -- If SW_MODE = '1', show MM:SS. If '0', show HH:MM. + -- d0 <= sig_s_units when SW_MODE = '1' else sig_m_units; + -- d1 <= sig_s_tens when SW_MODE = '1' else sig_m_tens; + -- d2 <= sig_m_units when SW_MODE = '1' else sig_h_units; + -- d3 <= sig_m_tens when SW_MODE = '1' else sig_h_tens; + + -- Mode Multiplexing (4 digit display) + process(SW_ALARM_SET, SW_MODE, + sig_s_units, sig_s_tens, sig_m_units, sig_m_tens, sig_h_units, sig_h_tens, + alrm_m_units, alrm_m_tens, alrm_h_units, alrm_h_tens) + begin + if SW_ALARM_SET = '1' then + -- While setting alarm, always show Alarm HH:MM + d0 <= alrm_m_units; + d1 <= alrm_m_tens; + d2 <= alrm_h_units; + d3 <= alrm_h_tens; + else + -- Normal Operation + if SW_MODE = '1' then + -- Show Seconds and Minutes (MM:SS) + d0 <= sig_s_units; + d1 <= sig_s_tens; + d2 <= sig_m_units; + d3 <= sig_m_tens; + else + -- Show Minutes and Hours (HH:MM) + d0 <= sig_m_units; + d1 <= sig_m_tens; + d2 <= sig_h_units; + d3 <= sig_h_tens; + end if; + end if; + end process; U_DISPLAY : entity work.display_driver port map (