time for big update from now on

dma Rx working
Rx is not using dma now
2025-10-31 22:37:23 +01:00 · 2025-10-31 17:28:34 +01:00 · 2025-10-31 14:31:25 +01:00 · 2025-10-31 13:19:54 +01:00 · 2025-10-31 13:00:21 +01:00 · 2025-10-31 11:46:21 +01:00
153 changed files with 17781 additions and 650 deletions
--- a/.gitignore
+++ b/.gitignore
@@ -0,0 +1 @@
+*.pdf
--- a/datasheet.txt
+++ b/datasheet.txt
@@ -0,0 +1 @@
+https://www.st.com/content/ccc/resource/technical/document/reference_manual/group0/f3/60/ca/d2/98/c8/47/88/DM00477635/files/DM00477635.pdf/jcr:content/translations/en.DM00477635.pdf
--- a/dma_gpio/.cargo/config.toml
+++ b/dma_gpio/.cargo/config.toml
@@ -0,0 +1,15 @@
+[build]
+target = "thumbv8m.main-none-eabihf"
+
+[target.thumbv8m.main-none-eabihf]
+runner = "probe-rs run --chip STM32U575ZITxQ"
+
+rustflags = [
+  "-C", "linker=rust-lld",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "link-arg=-Tdefmt.x",
+  "-C", "link-arg=--nmagic",
+]
+
+[package.metadata.cargo-flash]
+chip = "STM32U575ZIT"
--- a/dma_gpio/.gitignore
+++ b/dma_gpio/.gitignore
@@ -0,0 +1 @@
+/target
--- a/dma_gpio/Cargo.lock
+++ b/dma_gpio/Cargo.lock
--- a/dma_gpio/Cargo.toml
+++ b/dma_gpio/Cargo.toml
@@ -0,0 +1,27 @@
+[package]
+authors = ["Priec <filippriec@gmail.com>"]
+name = "dma_gpio"
+edition = "2024"
+version = "0.1.0"
+
+
+[dependencies]
+cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.5"
+panic-halt = "1.0.0"
+
+embassy-executor = { version = "0.9.1", features = ["arch-cortex-m", "executor-thread"] }
+embassy-futures = "0.1.2"
+embassy-stm32 = { version = "0.4.0", features = ["unstable-pac", "stm32u575zi", "time-driver-any", "memory-x", "defmt"] }
+embassy-sync = "0.7.2"
+embassy-time = { version = "0.5.0", features = ["tick-hz-32_768"] }
+embassy-usb = "0.5.1"
+
+embedded-hal = "1.0.0"
+embedded-graphics = "0.8.1"
+heapless = { version = "0.9.1", default-features = false }
+micromath = "2.1.0"
+tinybmp = "0.6.0"
+panic-probe = { version = "1.0.0", features = ["defmt"] }
+defmt-rtt = "1.1.0"
+defmt = "1.0.1"
--- a/stm32u5-blinky/LICENSE-APACHE
+++ b/stm32u5-blinky/LICENSE-APACHE
--- a/stm32u5-blinky/LICENSE-MIT
+++ b/stm32u5-blinky/LICENSE-MIT
--- a/dma_gpio/Makefile
+++ b/dma_gpio/Makefile
@@ -0,0 +1,23 @@
+TARGET = thumbv8m.main-none-eabihf
+CHIP = STM32U575ZI
+BIN = stm32u5-blinky
+MODE ?= release
+TARGET_DIR = target/$(TARGET)/$(MODE)
+ELF = $(TARGET_DIR)/$(BIN)
+PROBE = probe-rs
+
+.PHONY: all build flash clean empty
+
+all: build
+
+build:
+	cargo build --$(MODE)
+
+flash: build
+	$(PROBE) run --chip $(CHIP) $(ELF)
+
+empty:
+	$(PROBE) erase --chip $(CHIP)
+
+clean:
+	cargo clean
--- a/stm32u5-blinky/README.md
+++ b/stm32u5-blinky/README.md
--- a/dma_gpio/src/bin/main.rs
+++ b/dma_gpio/src/bin/main.rs
@@ -0,0 +1,155 @@
+// src/bin/main.rs
+
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use embassy_time::{Duration, Timer};
+use dma_gpio::dma_timer::init_tim6_for_uart;
+use dma_gpio::dma_timer::init_tim7_for_uart;
+use embassy_stm32::gpio::Input;
+use embassy_stm32::gpio::Pull;
+use dma_gpio::gpio_dma_uart_rx::GpioDmaRx;
+use {defmt_rtt as _, panic_probe as _};
+
+use embassy_stm32::{
+    gpio::{Level, Output, Speed},
+    peripherals::GPDMA1_CH0,
+    peripherals::GPDMA1_CH1,
+};
+use embassy_stm32::Peri;
+
+use dma_gpio::gpio_dma_uart_tx::{
+    write_uart_frames_to_pipe, GpioDmaBsrrTx, Parity, StopBits, UartConfig,
+};
+
+static PIPE_TX: Pipe<CriticalSectionRawMutex, 256> = Pipe::new();
+static PIPE_RX: Pipe<CriticalSectionRawMutex, 256> = Pipe::new();
+
+// Baud rate: one TIM6 update equals one UART bit-time
+const BAUD: u32 = 115_200;
+const TX_PIN_BIT: u8 = 2; // PA2
+const TX_OVERSAMPLE: u16 = 1;
+const RX_OVERSAMPLE: u16 = 16;
+
+const UART_CFG: UartConfig = UartConfig {
+    data_bits: 8,
+    parity: Parity::None,
+    stop_bits: StopBits::One,
+};
+static mut RX_DMA_BUF: [u32; 512] = [0; 512];
+
+fn dump_tim6_regs() {
+    // PAC path for STM32U5: module `tim6`, type `Tim6` with ptr()
+    use embassy_stm32::pac::timer::TimBasic;
+    let tim = unsafe { TimBasic::from_ptr(0x4000_1000usize as _) };
+    let sr = tim.sr().read();
+    let dier = tim.dier().read();
+    let cr1 = tim.cr1().read();
+    let arr = tim.arr().read().arr();
+    let psc = tim.psc().read();
+    info!(
+        "TIM6: CR1.CEN={} DIER.UDE={} SR.UIF={} PSC={} ARR={}",
+        cr1.cen(),
+        dier.ude(),
+        sr.uif(),
+        psc,
+        arr
+    );
+}
+
+fn dump_dma_ch0_regs() {
+    // PAC path for GPDMA1: module `gpdma1`, type `Gpdma1`
+    use embassy_stm32::pac::gpdma::Gpdma;
+    let dma = unsafe { Gpdma::from_ptr(0x4002_0000usize as _) };
+    let ch = dma.ch(0);
+    let cr = ch.cr().read();
+    let tr1 = ch.tr1().read();
+    let tr2 = ch.tr2().read();
+    let br1 = ch.br1().read();
+    info!(
+        "GPDMA1_CH0: EN={} PRIO={} SDW={} DDW={} SINC={} DINC={} REQSEL={} SWREQ={} DREQ={} BNDT={}",
+        cr.en(),
+        cr.prio(),
+        tr1.sdw(),
+        tr1.ddw(),
+        tr1.sinc(),
+        tr1.dinc(),
+        tr2.reqsel(),
+        tr2.swreq(),
+        tr2.dreq(),
+        br1.bndt()
+    );
+}
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    let p = embassy_stm32::init(Default::default());
+    info!("Hehe");
+
+    // PA3 as Rx "wire"
+    let pa3_rx = Input::new(p.PA3, Pull::Up);
+
+    // PA2 is the TX "wire"
+    let _pa2 = Output::new(p.PA2, Level::High, Speed::VeryHigh);
+    // drop(_pa2);
+    init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE); // TX
+    init_tim7_for_uart(p.TIM7, BAUD, RX_OVERSAMPLE); // RX
+    dump_tim6_regs();
+
+    // Start DMA consumer task
+    spawner.spawn(tx_dma_task(p.GPDMA1_CH0)).unwrap();
+    spawner.spawn(rx_dma_task(p.GPDMA1_CH1)).unwrap();
+
+    // Example: transmit a string as UART frames via the Pipe
+    loop {
+        write_uart_frames_to_pipe(
+            &PIPE_TX,
+            TX_PIN_BIT,
+            b"Hello marshmallow\r\n",
+            &UART_CFG,
+        ).await;
+        Timer::after(Duration::from_secs(2)).await;
+    }
+}
+
+#[embassy_executor::task]
+async fn rx_dma_task(ch: Peri<'static, GPDMA1_CH1>) {
+    let buf_ptr = core::ptr::addr_of_mut!(RX_DMA_BUF);
+    let buf = unsafe { &mut *buf_ptr };
+    let mut rx = GpioDmaRx::new(ch, 3 /*PA3 bit*/, buf, &PIPE_RX);
+    rx.run().await;
+}
+
+#[embassy_executor::task]
+async fn tx_dma_task(ch: Peri<'static, GPDMA1_CH0>) {
+    let mut tx = GpioDmaBsrrTx::new(ch);
+
+    info!("DMA task started, waiting for frames...");
+    loop {
+        // Read one 32-bit BSRR word (4 bytes) from the Pipe
+        let mut b = [0u8; 4];
+        let n = PIPE_TX.read(&mut b).await;
+        if n != 4 {
+            continue;
+        }
+        let w = u32::from_le_bytes(b);
+
+        info!("DMA write 0x{:08X} -> GPIOA.BSRR", w);
+        match embassy_time::with_timeout(
+            Duration::from_millis(20),
+            tx.write_word(w),
+        )
+        .await
+        {
+            Ok(()) => {}
+            Err(_) => {
+                warn!("DMA timeout: no TIM6 request");
+                dump_tim6_regs();
+                dump_dma_ch0_regs();
+            }
+        }
+    }
+}
--- a/dma_gpio/src/dma_timer.rs
+++ b/dma_gpio/src/dma_timer.rs
@@ -0,0 +1,58 @@
+// src/dma_timer.rs
+
+use embassy_stm32::{
+    peripherals::{TIM6, TIM7},
+    rcc,
+    timer::low_level::Timer,
+    Peri,
+};
+use core::mem;
+use embassy_stm32::timer::BasicInstance;
+use embassy_stm32::pac::timer::vals::Urs;
+
+/// Initializes TIM6 to tick at `baud * oversample` frequency.
+/// Each TIM6 update event triggers one DMA beat.
+pub fn init_tim6_for_uart<'d>(tim6: Peri<'d, TIM6>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM6>();
+    let ll = Timer::new(tim6);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+/// Initializes TIM7 to tick at `baud * oversample` frequency.
+/// Each TIM7 update event triggers one DMA beat.
+pub fn init_tim7_for_uart<'d>(tim7: Peri<'d, TIM7>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM7>();
+    let ll = Timer::new(tim7);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+// Shared internal helper — identical CR1/ARR setup
+fn configure_basic_timer<T: BasicInstance>(ll: &Timer<'_, T>, baud: u32, oversample: u16) {
+    let f_timer = rcc::frequency::<T>().0;
+    let target = baud.saturating_mul(oversample.max(1) as u32).max(1);
+
+    // Compute ARR (prescaler = 0)
+    let mut arr = (f_timer / target).saturating_sub(1) as u16;
+    if arr == 0 { arr = 1; }
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_cen(false);
+        w.set_opm(false);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+
+    ll.regs_basic().psc().write_value(0u16);
+    ll.regs_basic().arr().write(|w| w.set_arr(arr));
+    ll.regs_basic().dier().modify(|w| w.set_ude(true));
+    ll.regs_basic().egr().write(|w| w.set_ug(true));
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_opm(false);
+        w.set_cen(true);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+}
--- a/dma_gpio/src/gpio_dma_uart_rx.rs
+++ b/dma_gpio/src/gpio_dma_uart_rx.rs
@@ -0,0 +1,57 @@
+// src/gpio_dma_uart_rx.rs
+use embassy_stm32::{
+    dma::{Request, Transfer, TransferOptions},
+    peripherals::GPDMA1_CH1,
+    Peri,
+};
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+
+// RM0456 tabulka 137
+pub const TIM7_UP_REQ: Request = 5;
+
+pub struct GpioDmaRx<'d, const N: usize> {
+    ch: Peri<'d, GPDMA1_CH1>,
+    pin_bit: u8,
+    buf: &'d mut [u32; N],
+    opts: TransferOptions,
+    pipe_rx: &'d Pipe<CriticalSectionRawMutex, 256>,
+}
+
+impl<'d, const N: usize> GpioDmaRx<'d, N> {
+    pub fn new(
+        ch: Peri<'d, GPDMA1_CH1>,
+        pin_bit: u8,
+        buf: &'d mut [u32; N],
+        pipe_rx: &'d Pipe<CriticalSectionRawMutex, 256>,
+    ) -> Self {
+        Self {
+            ch,
+            pin_bit,
+            buf,
+            opts: TransferOptions::default(),
+            pipe_rx,
+        }
+    }
+
+    pub async fn run(&mut self) -> ! {
+        loop {
+            let gpioa_idr_addr = embassy_stm32::pac::GPIOA.as_ptr() as *mut u32;
+
+            unsafe {
+                Transfer::new_read(
+                    self.ch.reborrow(),
+                    TIM7_UP_REQ,
+                    gpioa_idr_addr,
+                    &mut self.buf[..],
+                    self.opts,
+                )
+            }
+            .await;
+
+            for &word in self.buf.iter() {
+                let bit_high = ((word >> self.pin_bit) & 1) as u8;
+                self.pipe_rx.write(&[bit_high]).await;
+            }
+        }
+    }
+}
--- a/dma_gpio/src/gpio_dma_uart_tx.rs
+++ b/dma_gpio/src/gpio_dma_uart_tx.rs
@@ -0,0 +1,168 @@
+// src/gpio_dma_uart.rs
+use embassy_stm32::{
+    dma::{Request, Transfer, TransferOptions},
+    peripherals::GPDMA1_CH0,
+    Peri,
+};
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+
+// kapitola 17.4.11 - 2 casovace pre 2 DMA
+pub const TIM6_UP_REQ: Request = 4; // Table 137: tim6_upd_dma, strana 687 STM32U5xx datasheet
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Parity {
+    None,
+    Even,
+    Odd,
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum StopBits {
+    One,
+    Two,
+}
+
+#[derive(Clone, Copy, Debug)]
+pub struct UartConfig {
+    pub data_bits: u8, // 5..=8 bitov strana 16 TI_uart
+    pub parity: Parity,
+    pub stop_bits: StopBits,
+}
+
+impl Default for UartConfig {
+    fn default() -> Self {
+        Self {
+            data_bits: 8,
+            parity: Parity::None,
+            stop_bits: StopBits::One,
+        }
+    }
+}
+
+pub struct GpioDmaBsrrTx<'d> {
+    ch: Peri<'d, GPDMA1_CH0>,
+    bsrr: *mut u32,
+    opts: TransferOptions,
+}
+
+impl<'d> GpioDmaBsrrTx<'d> {
+    // Constructor. Hides the raw register pointer internally.
+    pub fn new(ch: Peri<'d, GPDMA1_CH0>) -> Self {
+        let bsrr = embassy_stm32::pac::GPIOA.bsrr().as_ptr() as *mut u32;
+        Self {
+            ch,
+            bsrr,
+            opts: TransferOptions::default(),
+        }
+    }
+
+    // Safe API: perform one timer-paced DMA write of a single 32-bit BSRR word.
+    pub async fn write_word(&mut self, word: u32) {
+        let buf = [word];
+        // Safety: bsrr is a valid 32-bit aligned register, buf lives until DMA completes,
+        // request selects TIM6_UP, which paces one beat per update.
+        unsafe {
+            Transfer::new_write(
+                self.ch.reborrow(),
+                TIM6_UP_REQ,
+                &buf,
+                self.bsrr,
+                self.opts,
+            )
+        }
+        .await;
+    }
+}
+
+// Build up to 12 BSRR words for one UART frame on a given GPIO bit.
+// Format: 1 START (low), N data (LSB first), optional PARITY, STOP(1/2 -> here 1 or 2 ticks).
+// BSRR je safe atomic write only shortcut
+pub fn encode_uart_byte_cfg(
+    pin_bit: u8,
+    data: u8,
+    cfg: &UartConfig,
+    out: &mut [u32; 12],
+) -> usize {
+    // Dokumentacia strana 636 13.4.7
+    // set bit - HIGH, reset bit - LOW (BSRR)
+    let set_high = |bit: u8| -> u32 { 1u32 << bit };
+    let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) };
+
+    let mut idx = 0usize;
+
+    // START bit (LOW)
+    out[idx] = set_low(pin_bit);
+    idx += 1;
+
+    // Data bits, LSB first (5..=8)
+    let nbits = cfg.data_bits.clamp(5, 8);
+    for i in 0..nbits {
+        let one = ((data >> i) & 1) != 0;
+        out[idx] = if one { set_high(pin_bit) } else { set_low(pin_bit) };
+        idx += 1;
+    }
+
+    // Optional parity
+    match cfg.parity {
+        Parity::None => {}
+        Parity::Even | Parity::Odd => {
+            // Count ones
+            let mask: u8 = if nbits == 8 { 0xFF } else { (1u16 << nbits) as u8 - 1 };
+            let ones = (data & mask).count_ones() & 1; // 0=even, 1=odd
+            let par_bit_is_one = match cfg.parity {
+                Parity::Even => ones == 1, // make total ones even
+                Parity::Odd => ones == 0,  // make total ones odd
+                _ => false,
+            };
+            out[idx] = if par_bit_is_one {
+                set_high(pin_bit)
+            } else {
+                set_low(pin_bit)
+            };
+            idx += 1;
+        }
+    }
+
+    // STOP bits (HIGH)
+    //  - STB=0 => 1 stop bit
+    //  - STB=1 => 2 stop bits
+    let stop_ticks = match cfg.stop_bits {
+        StopBits::One => 1usize,
+        StopBits::Two => 2usize,
+    };
+    for _ in 0..stop_ticks {
+        out[idx] = set_high(pin_bit);
+        idx += 1;
+    }
+
+    idx
+}
+
+// Push UART frames for a whole byte slice into a Pipe.
+pub async fn write_uart_frames_to_pipe<const N: usize>(
+    pipe: &Pipe<CriticalSectionRawMutex, N>,
+    pin_bit: u8,
+    bytes: &[u8],
+    cfg: &UartConfig,
+) {
+    for &b in bytes {
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(pin_bit, b, cfg, &mut frame);
+        for w in &frame[..used] {
+            pipe.write(&w.to_le_bytes()).await;
+        }
+    }
+}
+
+// Optional: emit a BREAK (line LOW for 'bits' bit-times).
+pub async fn write_break_to_pipe<const N: usize>(
+    pipe: &Pipe<CriticalSectionRawMutex, N>,
+    pin_bit: u8,
+    bits: usize,
+) {
+    let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) };
+    let word = set_low(pin_bit);
+    for _ in 0..bits {
+        pipe.write(&word.to_le_bytes()).await;
+    }
+}
--- a/dma_gpio/src/lib.rs
+++ b/dma_gpio/src/lib.rs
@@ -0,0 +1,9 @@
+#![no_std]
+
+pub mod gpio_dma_uart_tx;
+pub mod gpio_dma_uart_rx;
+pub mod dma_timer;
+
+pub use gpio_dma_uart_tx::*;
+pub use gpio_dma_uart_rx::*;
+pub use dma_timer::*;
--- a/stm32u5-blinky/tests/integration.rs
+++ b/stm32u5-blinky/tests/integration.rs
--- a/flake.nix
+++ b/flake.nix
@@ -6,6 +6,10 @@
  outputs = { self, nixpkgs }: let
    system = "x86_64-linux";
    pkgs = import nixpkgs { inherit system; };
+    rust = pkgs.rust-bin.stable.latest.default.override {
+      targets = [ "thumbv8m.main-none-eabihf" ];
+      extensions = [ "rust-src" "rustfmt" "clippy" ];
+    };
  in {
    devShells.${system}.default = pkgs.mkShell {
      packages = with pkgs; [
@@ -34,32 +38,28 @@
      ];

      shellHook = ''
-        echo ">>> STM32U575ZI-Q Rust (HAL + PAC) DevShell"
-        echo "---------------------------------------------"
+        echo ">>> STM32 DevShell"

-        # Set up Rust target
-        rustup target add thumbv7em-none-eabihf 2>/dev/null || true
+	export PATH=${pkgs.rust-analyzer}/bin:$PATH
+	export PATH=$HOME/.cargo/bin:$PATH

-        # Ensure probe-rs binary is in PATH
-        if ! command -v probe-rs >/dev/null; then
-          echo "⚠️ probe-rs not found! (check nix installation)"
-        fi
+        rustup default stable
+        rustup component add rust-src rustfmt clippy 2>/dev/null || true
+        rustup target add thumbv8m.main-none-eabihf 2>/dev/null || true

-        export RUST_TARGET=thumbv7em-none-eabihf
+        export RUST_TARGET=thumbv8m.main-none-eabihf
        export CARGO_TARGET_DIR=target
+	export DEFMT_LOG=info
        export PATH=$PATH:${pkgs.gcc-arm-embedded}/bin
+        export RUST_SRC_PATH="$(rustc --print sysroot)/lib/rustlib/src/rust/library"

-        echo "🧩 Target: $RUST_TARGET"
-        echo "💡 Examples:"
-        echo "  1️⃣  cargo generate --git https://github.com/rust-embedded/cortex-m-quickstart --name stm32u5-blinky"
-        echo "  2️⃣  cd stm32u5-blinky && cargo build --release --target thumbv7em-none-eabihf"
-        echo "  3️⃣  probe-rs run --chip STM32U575ZITxQ target/thumbv7em-none-eabihf/release/stm32u5-blinky"
-        echo ""
-        echo "🧠 TIP: Add stm32u5xx-hal to Cargo.toml to access register-level HAL API."
-        echo "---------------------------------------------"
-
-        rustc --version
-        arm-none-eabi-gcc --version | head -n1
+	rustc --version
+	arm-none-eabi-gcc --version | head -n1
+        echo "cargo build --release --target thumbv8m.main-none-eabihf"
+        echo "cargo flash --release --chip STM32U575ZI"
+	echo "cargo run --bin main"
+	echo "probe-rs run --chip STM32U575ZITxQ target/thumbv8m.main-none-eabihf/release/main"
+	echo "target/**/build/embassy-stm32-*/out/_generated.rs"
      '';
    };
  };
--- a/hal_adc/.cargo/config.toml
+++ b/hal_adc/.cargo/config.toml
@@ -0,0 +1,15 @@
+[build]
+target = "thumbv8m.main-none-eabihf"
+
+[target.thumbv8m.main-none-eabihf]
+runner = "probe-rs run --chip STM32U575ZITxQ"
+
+rustflags = [
+  "-C", "linker=rust-lld",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "link-arg=-Tdefmt.x",
+  "-C", "link-arg=--nmagic",
+]
+
+[package.metadata.cargo-flash]
+chip = "STM32U575ZIT"
--- a/hal_adc/.gitignore
+++ b/hal_adc/.gitignore
@@ -0,0 +1 @@
+/target
--- a/hal_adc/Cargo.lock
+++ b/hal_adc/Cargo.lock
--- a/hal_adc/Cargo.toml
+++ b/hal_adc/Cargo.toml
@@ -0,0 +1,27 @@
+[package]
+authors = ["Priec <filippriec@gmail.com>"]
+name = "hal_adc"
+edition = "2024"
+version = "0.1.0"
+
+
+[dependencies]
+cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.5"
+panic-halt = "1.0.0"
+
+embassy-executor = { version = "0.9.1", features = ["arch-cortex-m", "executor-thread"] }
+embassy-futures = "0.1.2"
+embassy-stm32 = { version = "0.4.0", features = ["unstable-pac", "stm32u575zi", "time-driver-any", "memory-x"] }
+embassy-sync = "0.7.2"
+embassy-time = { version = "0.5.0", features = ["tick-hz-32_768"] }
+embassy-usb = "0.5.1"
+
+embedded-hal = "1.0.0"
+embedded-graphics = "0.8.1"
+heapless = { version = "0.9.1", default-features = false }
+micromath = "2.1.0"
+tinybmp = "0.6.0"
+panic-probe = { version = "1.0.0", features = ["defmt"] }
+defmt-rtt = "1.1.0"
+defmt = "1.0.1"
--- a/hal_adc/LICENSE-APACHE
+++ b/hal_adc/LICENSE-APACHE
--- a/hal_adc/LICENSE-MIT
+++ b/hal_adc/LICENSE-MIT
--- a/hal_adc/Makefile
+++ b/hal_adc/Makefile
@@ -0,0 +1,23 @@
+TARGET = thumbv8m.main-none-eabihf
+CHIP = STM32U575ZI
+BIN = stm32u5-blinky
+MODE ?= release
+TARGET_DIR = target/$(TARGET)/$(MODE)
+ELF = $(TARGET_DIR)/$(BIN)
+PROBE = probe-rs
+
+.PHONY: all build flash clean empty
+
+all: build
+
+build:
+	cargo build --$(MODE)
+
+flash: build
+	$(PROBE) run --chip $(CHIP) $(ELF)
+
+empty:
+	$(PROBE) erase --chip $(CHIP)
+
+clean:
+	cargo clean
--- a/hal_adc/README.md
+++ b/hal_adc/README.md
--- a/hal_adc/rust-toolchain.toml
+++ b/hal_adc/rust-toolchain.toml
@@ -0,0 +1,5 @@
+# rust-toolchain.toml
+[toolchain]
+channel = "stable"
+components = ["rust-src", "rustfmt", "clippy"]
+targets = ["thumbv8m.main-none-eabihf"]
--- a/hal_adc/src/bin/main.rs
+++ b/hal_adc/src/bin/main.rs
@@ -0,0 +1,111 @@
+// src/bin/main.rs
+
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_stm32::adc;
+use embassy_stm32::adc::{AdcChannel, adc4};
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: embassy_executor::Spawner) {
+    let config = embassy_stm32::Config::default();
+
+    let mut p = embassy_stm32::init(config);
+
+    // **** ADC1 init ****
+    let mut adc1 = adc::Adc::new(p.ADC1);
+    let mut adc1_pin1 = p.PA3; // A0 on nucleo u5a5
+    let mut adc1_pin2 = p.PA2; // A1
+    adc1.set_resolution(adc::Resolution::BITS14);
+    adc1.set_averaging(adc::Averaging::Samples1024);
+    adc1.set_sample_time(adc::SampleTime::CYCLES160_5);
+    let max1 = adc::resolution_to_max_count(adc::Resolution::BITS14);
+
+    // **** ADC2 init ****
+    let mut adc2 = adc::Adc::new(p.ADC2);
+    let mut adc2_pin1 = p.PC3; // A2
+    let mut adc2_pin2 = p.PB0; // A3
+    adc2.set_resolution(adc::Resolution::BITS14);
+    adc2.set_averaging(adc::Averaging::Samples1024);
+    adc2.set_sample_time(adc::SampleTime::CYCLES160_5);
+    let max2 = adc::resolution_to_max_count(adc::Resolution::BITS14);
+
+    // **** ADC4 init ****
+    let mut adc4 = adc4::Adc4::new(p.ADC4);
+    let mut adc4_pin1 = p.PC1; // A4
+    let mut adc4_pin2 = p.PC0; // A5
+    adc4.set_resolution(adc4::Resolution::BITS12);
+    adc4.set_averaging(adc4::Averaging::Samples256);
+    adc4.set_sample_time(adc4::SampleTime::CYCLES1_5);
+    let max4 = adc4::resolution_to_max_count(adc4::Resolution::BITS12);
+
+    // **** ADC1 blocking read ****
+    let raw: u16 = adc1.blocking_read(&mut adc1_pin1);
+    let volt: f32 = 3.3 * raw as f32 / max1 as f32;
+    info!("Read adc1 pin 1 {}", volt);
+
+    let raw: u16 = adc1.blocking_read(&mut adc1_pin2);
+    let volt: f32 = 3.3 * raw as f32 / max1 as f32;
+    info!("Read adc1 pin 2 {}", volt);
+
+    // **** ADC2 blocking read ****
+    let raw: u16 = adc2.blocking_read(&mut adc2_pin1);
+    let volt: f32 = 3.3 * raw as f32 / max2 as f32;
+    info!("Read adc2 pin 1 {}", volt);
+
+    let raw: u16 = adc2.blocking_read(&mut adc2_pin2);
+    let volt: f32 = 3.3 * raw as f32 / max2 as f32;
+    info!("Read adc2 pin 2 {}", volt);
+
+    // **** ADC4 blocking read ****
+    let raw: u16 = adc4.blocking_read(&mut adc4_pin1);
+    let volt: f32 = 3.3 * raw as f32 / max4 as f32;
+    info!("Read adc4 pin 1 {}", volt);
+
+    let raw: u16 = adc4.blocking_read(&mut adc4_pin2);
+    let volt: f32 = 3.3 * raw as f32 / max4 as f32;
+    info!("Read adc4 pin 2 {}", volt);
+
+    // **** ADC1 async read ****
+    let mut degraded11 = adc1_pin1.degrade_adc();
+    let mut degraded12 = adc1_pin2.degrade_adc();
+    let mut measurements = [0u16; 2];
+
+    adc1.read(
+        p.GPDMA1_CH0.reborrow(),
+        [
+            (&mut degraded11, adc::SampleTime::CYCLES160_5),
+            (&mut degraded12, adc::SampleTime::CYCLES160_5),
+        ]
+        .into_iter(),
+        &mut measurements,
+    )
+    .await;
+    let volt1: f32 = 3.3 * measurements[0] as f32 / max1 as f32;
+    let volt2: f32 = 3.3 * measurements[1] as f32 / max1 as f32;
+
+    info!("Async read 1 pin 1 {}", volt1);
+    info!("Async read 1 pin 2 {}", volt2);
+
+    // **** ADC2 does not support async read ****
+
+    // **** ADC4 async read ****
+    let mut degraded41 = adc4_pin1.degrade_adc();
+    let mut degraded42 = adc4_pin2.degrade_adc();
+    let mut measurements = [0u16; 2];
+
+    // The channels must be in ascending order and can't repeat for ADC4
+    adc4.read(
+        p.GPDMA1_CH1.reborrow(),
+        [&mut degraded42, &mut degraded41].into_iter(),
+        &mut measurements,
+    )
+    .await
+    .unwrap();
+    let volt2: f32 = 3.3 * measurements[0] as f32 / max4 as f32;
+    let volt1: f32 = 3.3 * measurements[1] as f32 / max4 as f32;
+    info!("Async read 4 pin 1 {}", volt1);
+    info!("Async read 4 pin 2 {}", volt2);
+}
--- a/hal_adc/src/lib.rs
+++ b/hal_adc/src/lib.rs
@@ -0,0 +1,18 @@
+#![no_std]
+
+use defmt_rtt as _; // global logger
+use panic_probe as _;
+
+// same panicking *behavior* as `panic-probe` but doesn't print a panic message
+// this prevents the panic message being printed *twice* when `defmt::panic` is invoked
+#[defmt::panic_handler]
+fn panic() -> ! {
+    cortex_m::asm::udf()
+}
+
+/// HardFault exit handler
+#[cortex_m_rt::exception]
+unsafe fn HardFault(_frame: &cortex_m_rt::ExceptionFrame) -> ! {
+    cortex_m::asm::bkpt(); // stay under debugger rather than exit semihosting
+    loop {}
+}
--- a/hal_adc/tests/integration.rs
+++ b/hal_adc/tests/integration.rs
--- a/hal_rng/.cargo/config.toml
+++ b/hal_rng/.cargo/config.toml
@@ -0,0 +1,15 @@
+[build]
+target = "thumbv8m.main-none-eabihf"
+
+[target.thumbv8m.main-none-eabihf]
+runner = "probe-rs run --chip STM32U575ZITxQ"
+
+rustflags = [
+  "-C", "linker=rust-lld",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "link-arg=-Tdefmt.x",
+  "-C", "link-arg=--nmagic",
+]
+
+[package.metadata.cargo-flash]
+chip = "STM32U575ZIT"
--- a/hal_rng/.gitignore
+++ b/hal_rng/.gitignore
@@ -0,0 +1 @@
+/target
--- a/hal_rng/Cargo.lock
+++ b/hal_rng/Cargo.lock
--- a/hal_rng/Cargo.toml
+++ b/hal_rng/Cargo.toml
@@ -0,0 +1,27 @@
+[package]
+authors = ["Priec <filippriec@gmail.com>"]
+name = "hal_rng"
+edition = "2024"
+version = "0.1.0"
+
+
+[dependencies]
+cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.5"
+panic-halt = "1.0.0"
+
+embassy-executor = { version = "0.9.1", features = ["arch-cortex-m", "executor-thread"] }
+embassy-futures = "0.1.2"
+embassy-stm32 = { version = "0.4.0", features = ["unstable-pac", "stm32u575zi", "time-driver-any", "memory-x", "defmt"] }
+embassy-sync = "0.7.2"
+embassy-time = { version = "0.5.0", features = ["tick-hz-32_768"] }
+embassy-usb = "0.5.1"
+
+embedded-hal = "1.0.0"
+embedded-graphics = "0.8.1"
+heapless = { version = "0.9.1", default-features = false }
+micromath = "2.1.0"
+tinybmp = "0.6.0"
+panic-probe = { version = "1.0.0", features = ["defmt"] }
+defmt-rtt = "1.1.0"
+defmt = "1.0.1"
--- a/hal_rng/LICENSE-APACHE
+++ b/hal_rng/LICENSE-APACHE
@@ -0,0 +1,201 @@
+                              Apache License
+                        Version 2.0, January 2004
+                     http://www.apache.org/licenses/
+
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--- a/hal_rng/LICENSE-MIT
+++ b/hal_rng/LICENSE-MIT
@@ -0,0 +1,23 @@
+Permission is hereby granted, free of charge, to any
+person obtaining a copy of this software and associated
+documentation files (the "Software"), to deal in the
+Software without restriction, including without
+limitation the rights to use, copy, modify, merge,
+publish, distribute, sublicense, and/or sell copies of
+the Software, and to permit persons to whom the Software
+is furnished to do so, subject to the following
+conditions:
+
+The above copyright notice and this permission notice
+shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
+ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
+IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.
--- a/hal_rng/Makefile
+++ b/hal_rng/Makefile
@@ -0,0 +1,23 @@
+TARGET = thumbv8m.main-none-eabihf
+CHIP = STM32U575ZI
+BIN = stm32u5-blinky
+MODE ?= release
+TARGET_DIR = target/$(TARGET)/$(MODE)
+ELF = $(TARGET_DIR)/$(BIN)
+PROBE = probe-rs
+
+.PHONY: all build flash clean empty
+
+all: build
+
+build:
+	cargo build --$(MODE)
+
+flash: build
+	$(PROBE) run --chip $(CHIP) $(ELF)
+
+empty:
+	$(PROBE) erase --chip $(CHIP)
+
+clean:
+	cargo clean
--- a/hal_rng/README.md
+++ b/hal_rng/README.md
@@ -0,0 +1,232 @@
+# `app-template`
+
+> Quickly set up a [`probe-rs`] + [`defmt`] + [`flip-link`] embedded project
+
+[`probe-rs`]: https://crates.io/crates/probe-rs
+[`defmt`]: https://github.com/knurling-rs/defmt
+[`flip-link`]: https://github.com/knurling-rs/flip-link
+
+## Dependencies
+
+### 1. `flip-link`:
+
+```bash
+cargo install flip-link
+```
+
+### 2. `probe-rs`:
+
+Install probe-rs by following the instructions at <https://probe.rs/docs/getting-started/installation/>.
+
+### 3. [`cargo-generate`]:
+
+```bash
+cargo install cargo-generate
+```
+
+[`cargo-generate`]: https://crates.io/crates/cargo-generate
+
+> *Note:* You can also just clone this repository instead of using `cargo-generate`, but this involves additional manual adjustments.
+
+## Setup
+
+### 1. Initialize the project template
+
+```bash
+cargo generate \
+    --git https://github.com/knurling-rs/app-template \
+    --branch main \
+    --name my-app
+```
+
+If you look into your new `my-app` folder, you'll find that there are a few `TODO`s in the files marking the properties you need to set.
+
+Let's walk through them together now.
+
+### 2. Set `probe-rs` chip
+
+Pick a chip from ` probe-rs chip list` and enter it into `.cargo/config.toml`.
+
+If, for example, you have a nRF52840 Development Kit as used in one of [our exercises], replace `{{chip}}` with `nRF52840_xxAA`.
+
+[our workshops]: https://rust-exercises.ferrous-systems.com
+
+```diff
+ # .cargo/config.toml
+-runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format=oneline"]
+runner = ["probe-rs", "run", "--chip", "nRF52840_xxAA", "--log-format=oneline"]
+```
+
+### 3. Adjust the compilation target
+
+In `.cargo/config.toml`, pick the right compilation target for your board.
+
+```diff
+ # .cargo/config.toml
+ [build]
+-target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
+-# target = "thumbv7m-none-eabi"    # Cortex-M3
+-# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
+-# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
+target = "thumbv7em-none-eabihf" # Cortex-M4F (with FPU)
+```
+
+Add the target with `rustup`.
+
+```bash
+rustup target add thumbv7em-none-eabihf
+```
+
+### 4. Add a HAL as a dependency
+
+In `Cargo.toml`, list the Hardware Abstraction Layer (HAL) for your board as a dependency.
+
+For the nRF52840 you'll want to use the [`nrf52840-hal`].
+
+[`nrf52840-hal`]: https://crates.io/crates/nrf52840-hal
+
+```diff
+ # Cargo.toml
+ [dependencies]
+-# some-hal = "1.2.3"
+nrf52840-hal = "0.14.0"
+```
+
+⚠️ Note for RP2040 users ⚠️
+
+You will need to not just specify the `rp-hal` HAL, but a BSP (board support crate) which includes a second stage bootloader. Please find a list of available BSPs [here](https://github.com/rp-rs/rp-hal-boards#packages).
+
+### 5. Import your HAL
+
+Now that you have selected a HAL, fix the HAL import in `src/lib.rs`
+
+```diff
+ // my-app/src/lib.rs
+-// use some_hal as _; // memory layout
+use nrf52840_hal as _; // memory layout
+```
+
+### (6. Get a linker script)
+
+Some HAL crates require that you manually copy over a file called `memory.x` from the HAL to the root of your project. For nrf52840-hal, this is done automatically so no action is needed. For other HAL crates, see their documentation on where to find an example file.
+
+The `memory.x` file should look something like:
+
+```text
+MEMORY
+{
+  FLASH : ORIGIN = 0x00000000, LENGTH = 1024K
+  RAM   : ORIGIN = 0x20000000, LENGTH = 256K
+}
+```
+
+The `memory.x` file is included in the `cortex-m-rt` linker script `link.x`, and so `link.x` is the one you should tell `rustc` to use (see the `.cargo/config.toml` file where we do that).
+
+### 7. Run!
+
+You are now all set to `cargo-run` your first `defmt`-powered application!
+There are some examples in the `src/bin` directory.
+
+Start by `cargo run`-ning `my-app/src/bin/hello.rs`:
+
+```console
+$ # `rb` is an alias for `run --bin`
+$ cargo rb hello
+    Finished `dev` profile [optimized + debuginfo] target(s) in 0.01s
+     Running `probe-rs run --chip nrf52840_xxaa --log-format=oneline target/thumbv6m-none-eabi/debug/hello`
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.79 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+Hello, world!
+
+$ echo $?
+0
+```
+
+If you're running out of memory (`flip-link` bails with an overflow error), you can decrease the size of the device memory buffer by setting the `DEFMT_RTT_BUFFER_SIZE` environment variable. The default value is 1024 bytes, and powers of two should be used for optimal performance:
+
+```console
+$ DEFMT_RTT_BUFFER_SIZE=64 cargo rb hello
+```
+
+### (8. Set `rust-analyzer.linkedProjects`)
+
+If you are using [rust-analyzer] with VS Code for IDE-like features you can add following configuration to your `.vscode/settings.json` to make it work transparently across workspaces. Find the details of this option in the [RA docs].
+
+```json
+{
+    "rust-analyzer.linkedProjects": [
+        "Cargo.toml",
+        "firmware/Cargo.toml",
+    ]
+}
+```
+
+[RA docs]: https://rust-analyzer.github.io/manual.html#configuration
+[rust-analyzer]: https://rust-analyzer.github.io/
+
+## Running tests
+
+The template comes configured for running unit tests and integration tests on the target.
+
+Unit tests reside in the library crate and can test private API; the initial set of unit tests are in `src/lib.rs`.
+`cargo test --lib` will run those unit tests.
+
+```console
+$ cargo test --lib
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.15s
+     Running unittests src/lib.rs (target/thumbv6m-none-eabi/debug/deps/example-2b0d0e25d141bf57)
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.99 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.33 KiB/s (took 1s)                                                                                                                        Finished in 1.10s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Integration tests reside in the `tests` directory; the initial set of integration tests are in `tests/integration.rs`.
+`cargo test --test integration` will run those integration tests.
+Note that the argument of the `--test` flag must match the name of the test file in the `tests` directory.
+
+```console
+$ cargo test --test integration
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.10s
+     Running tests/integration.rs (target/thumbv6m-none-eabi/debug/deps/integration-aaaff41151f6a722)
+      Erasing ✔ 100% [####################]   8.00 KiB @  16.03 KiB/s (took 0s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Note that to add a new test file to the `tests` directory you also need to add a new `[[test]]` section to `Cargo.toml`.
+
+To run all the tests via `cargo test` the tests need to be explicitly disabled for all the existing binary targets.
+See `Cargo.toml` for details on how to do this.
+
+## Support
+
+`app-template` is part of the [Knurling] project, [Ferrous Systems]' effort at
+improving tooling used to develop for embedded systems.
+
+If you think that our work is useful, consider sponsoring it via [GitHub
+Sponsors].
+
+## License
+
+Licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+  http://www.apache.org/licenses/LICENSE-2.0)
+
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+### Contribution
+
+Unless you explicitly state otherwise, any contribution intentionally submitted
+for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
+licensed as above, without any additional terms or conditions.
+
+[Knurling]: https://knurling.ferrous-systems.com
+[Ferrous Systems]: https://ferrous-systems.com/
+[GitHub Sponsors]: https://github.com/sponsors/knurling-rs
--- a/hal_rng/src/bin/main.rs
+++ b/hal_rng/src/bin/main.rs
@@ -0,0 +1,33 @@
+// src/bin/main.rs
+
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::rng::Rng;
+use embassy_stm32::{bind_interrupts, peripherals, rng};
+use embassy_time::{Duration, Timer};
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    RNG => rng::InterruptHandler<peripherals::RNG>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_stm32::init(Default::default());
+
+    info!("Hello World!");
+
+    let mut rng = Rng::new(p.RNG, Irqs);
+
+    let mut buf = [0u8; 16];
+
+    loop {
+        unwrap!(rng.async_fill_bytes(&mut buf).await);
+        info!("random bytes: {:02x}", buf);
+
+        Timer::after(Duration::from_secs(1)).await;
+    }
+}
--- a/hal_rng/src/lib.rs
+++ b/hal_rng/src/lib.rs
@@ -0,0 +1 @@
+#![no_std]
--- a/hal_rng/tests/integration.rs
+++ b/hal_rng/tests/integration.rs
@@ -0,0 +1,16 @@
+#![no_std]
+#![no_main]
+
+use stm32u5_blinky as _; // memory layout + panic handler
+
+// See https://crates.io/crates/defmt-test/0.3.0 for more documentation (e.g. about the 'state'
+// feature)
+#[defmt_test::tests]
+mod tests {
+    use defmt::assert;
+
+    #[test]
+    fn it_works() {
+        assert!(true)
+    }
+}
--- a/hal_test/.cargo/config.toml
+++ b/hal_test/.cargo/config.toml
@@ -1,22 +1,14 @@
-[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-runner = ["probe-rs", "run", "--chip", "STM32U575ZI", "--log-format=oneline"]
-
-rustflags = [
-  "-C", "linker=flip-link",
-  "-C", "link-arg=-Tlink.x",
-  "-C", "link-arg=-Tdefmt.x",
-  "-C", "link-arg=--nmagic",
-]
-
 [build]
 target = "thumbv8m.main-none-eabihf"

 [target.thumbv8m.main-none-eabihf]
-runner = "probe-rs run --chip STM32U575ZI"
+runner = "probe-rs run --chip STM32U575ZITxQ"

-[alias]
-rb = "run --bin"
-rrb = "run --release --bin"
+rustflags = [
+  "-C", "linker=rust-lld",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "link-arg=--nmagic",
+]

-[env]
-DEFMT_LOG = "info"
+[package.metadata.cargo-flash]
+chip = "STM32U575ZIT"
--- a/hal_test/.gitignore
+++ b/hal_test/.gitignore
@@ -1,2 +1 @@
 /target
-Cargo.lock
--- a/hal_test/Cargo.lock
+++ b/hal_test/Cargo.lock
@@ -0,0 +1,949 @@
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+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "de437e2a6208b014ab52972a27e59b33fa2920d3e00fe05026167a1c509d19cc"
+dependencies = [
+ "vcell",
+]
+
+[[package]]
+name = "zerocopy"
+version = "0.8.27"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0894878a5fa3edfd6da3f88c4805f4c8558e2b996227a3d864f47fe11e38282c"
+dependencies = [
+ "zerocopy-derive",
+]
+
+[[package]]
+name = "zerocopy-derive"
+version = "0.8.27"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "88d2b8d9c68ad2b9e4340d7832716a4d21a22a1154777ad56ea55c51a9cf3831"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn 2.0.107",
+]
--- a/hal_test/Cargo.toml
+++ b/hal_test/Cargo.toml
@@ -1,42 +1,24 @@
 [package]
-# TODO(1) fix `authors` and `name` if you didn't use `cargo-generate`
 authors = ["Priec <filippriec@gmail.com>"]
-name = "stm32u5-blinky"
+name = "hal_test"
 edition = "2024"
 version = "0.1.0"


 [dependencies]
-cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
-cortex-m-rt = "0.7"
-defmt = "1.0"
-defmt-rtt = "1.0"
-panic-probe = { version = "1.0", features = ["print-defmt"] }
-embassy-stm32 = { version = "0.4.0", features = ["stm32u575zi", "time-driver-tim1", "defmt", "low-power", "memory-x"] }
-embassy-time = "0.5.0"
-semihosting = "0.1.20"
+cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.5"
+panic-halt = "1.0.0"
+
+embassy-executor = { version = "0.9.1", features = ["arch-cortex-m", "executor-thread"] }
+embassy-futures = "0.1.2"
+embassy-stm32 = { version = "0.4.0", features = ["unstable-pac", "stm32u575zi", "time-driver-any", "memory-x"] }
+embassy-sync = "0.7.2"
+embassy-time = { version = "0.5.0", features = ["tick-hz-32_768"] }
+embassy-usb = "0.5.1"
+
 embedded-hal = "1.0.0"
-
-[dev-dependencies]
-defmt-test = "0.3"
-
-# cargo build/run
-[profile.dev]
-# default is opt-level = '0', but that makes very
-# verbose machine code
-opt-level = 's'
-# trade compile speed for slightly better optimisations
-codegen-units = 1
-
-# cargo build/run --release
-[profile.release]
-# default is opt-level = '3', but that makes quite
-# verbose machine code
-opt-level = 's'
-# trade compile speed for slightly better optimisations
-codegen-units = 1
-# Use Link Time Optimisations to further inline things across
-# crates
-lto = 'fat'
-# Leave the debug symbols in (default is no debug info)
-debug = 2
+embedded-graphics = "0.8.1"
+heapless = { version = "0.9.1", default-features = false }
+micromath = "2.1.0"
+tinybmp = "0.6.0"
--- a/hal_test/Makefile
+++ b/hal_test/Makefile
@@ -0,0 +1,20 @@
+TARGET = thumbv8m.main-none-eabihf
+CHIP = STM32U575ZI
+BIN = main
+MODE ?= release
+ELF = target/$(TARGET)/$(MODE)/$(BIN)
+PROBE = probe-rs
+
+.PHONY: all build flash empty
+
+all: build flash
+
+build:
+	cargo build --target $(TARGET) --$(MODE)
+
+flash: build
+	$(PROBE) run --chip $(CHIP) $(ELF)
+
+empty:
+	$(PROBE) erase --chip $(CHIP)
+
--- a/hal_test/memory.x
+++ b/hal_test/memory.x
@@ -1,13 +0,0 @@
-/* memory.x - STM32U575ZITxQ memory layout */
-
-/* Flash: 2 MB starting at 0x08000000 */
-/* SRAM1 + SRAM2 + SRAM3 total 786 KB starting at 0x20000000 */
-
-MEMORY
-{
-  FLASH (rx)  : ORIGIN = 0x08000000, LENGTH = 2048K
-  RAM   (xrw) : ORIGIN = 0x20000000, LENGTH = 786K
-}
-
-/* provide stack start symbol (end of RAM) */
-_stack_start = ORIGIN(RAM) + LENGTH(RAM);
--- a/hal_test/src/bin/main.rs
+++ b/hal_test/src/bin/main.rs
@@ -1,30 +1,24 @@
-// src/bin/main.rs
-
 #![no_std]
 #![no_main]

-use defmt_rtt as _;
+use embassy_executor::Spawner;
 use embassy_stm32::gpio::{Level, Output, Speed};
+use embassy_time::{Duration, Timer};
+use embassy_stm32::init;
 use embassy_stm32::Config;
-use embassy_time::Delay;
-use embedded_hal::delay::DelayNs;
-use panic_probe as _;
+use panic_halt as _;

-#[cortex_m_rt::entry]
-fn main() -> ! {
-    defmt::info!("Starting blinky on STM32U575ZI-Q...");
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = init(Config::default());

-    // Initialize peripherals with the default clock tree for STM32U5.
-    let p = embassy_stm32::init(Config::default());
-
-    // On‑board LED (PB7 on NUCLEO‑U575ZI‑Q)
-    let mut led = Output::new(p.PB7, Level::Low, Speed::Low);
-    let mut delay = Delay;
+    // The user LED on NUCLEO-U575ZI-Q is typically on port B, pin 0 (verify silkscreen)
+    let mut led = Output::new(p.PB0, Level::Low, Speed::Low);

    loop {
        led.set_high();
-        delay.delay_ms(500); // needs embedded_hal::delay::DelayNs in scope
+        Timer::after(Duration::from_millis(500)).await;
        led.set_low();
-        delay.delay_ms(500);
+        Timer::after(Duration::from_millis(500)).await;
    }
 }
--- a/hal_test/src/lib.rs
+++ b/hal_test/src/lib.rs
@@ -1,46 +1 @@
-#![no_main]
 #![no_std]
-
-use defmt_rtt as _; // global logger
-
-// TODO(5) adjust HAL import
-// use some_hal as _; // memory layout
-
-use panic_probe as _;
-
-// same panicking *behavior* as `panic-probe` but doesn't print a panic message
-// this prevents the panic message being printed *twice* when `defmt::panic` is invoked
-#[defmt::panic_handler]
-fn panic() -> ! {
-    cortex_m::asm::udf()
-}
-
-/// Terminates the application and makes a semihosting-capable debug tool exit
-/// with status code 0.
-pub fn exit() -> ! {
-    semihosting::process::exit(0);
-}
-
-/// Hardfault handler.
-///
-/// Terminates the application and makes a semihosting-capable debug tool exit
-/// with an error. This seems better than the default, which is to spin in a
-/// loop.
-#[cortex_m_rt::exception]
-unsafe fn HardFault(_frame: &cortex_m_rt::ExceptionFrame) -> ! {
-    semihosting::process::exit(1);
-}
-
-// defmt-test 0.3.0 has the limitation that this `#[tests]` attribute can only be used
-// once within a crate. the module can be in any file but there can only be at most
-// one `#[tests]` module in this library crate
-#[cfg(test)]
-#[defmt_test::tests]
-mod unit_tests {
-    use defmt::assert;
-
-    #[test]
-    fn it_works() {
-        assert!(true)
-    }
-}
--- a/pinout1.png
+++ b/pinout1.png
--- a/pinout2.png
+++ b/pinout2.png
--- a/semestralka_1/.cargo/config.toml
+++ b/semestralka_1/.cargo/config.toml
@@ -0,0 +1,15 @@
+[build]
+target = "thumbv8m.main-none-eabihf"
+
+[target.thumbv8m.main-none-eabihf]
+runner = "probe-rs run --chip STM32U575ZITxQ"
+
+rustflags = [
+  "-C", "linker=rust-lld",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "link-arg=-Tdefmt.x",
+  "-C", "link-arg=--nmagic",
+]
+
+[package.metadata.cargo-flash]
+chip = "STM32U575ZIT"
--- a/semestralka_1/.gitignore
+++ b/semestralka_1/.gitignore
@@ -0,0 +1 @@
+/target
--- a/semestralka_1/Cargo.lock
+++ b/semestralka_1/Cargo.lock
--- a/semestralka_1/Cargo.toml
+++ b/semestralka_1/Cargo.toml
@@ -0,0 +1,33 @@
+[package]
+authors = ["Priec <filippriec@gmail.com>"]
+name = "async_uart"
+edition = "2024"
+version = "0.1.0"
+
+
+[dependencies]
+cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.5"
+panic-halt = "1.0.0"
+
+embassy-executor = { version = "0.9.1", features = ["arch-cortex-m", "executor-thread"] }
+embassy-futures = "0.1.2"
+embassy-stm32 = { version = "0.4.0", features = ["unstable-pac", "stm32u575zi", "time-driver-any", "memory-x", "defmt"] }
+embassy-sync = "0.7.2"
+embassy-time = { version = "0.5.0", features = ["tick-hz-32_768"] }
+embassy-usb = "0.5.1"
+
+embedded-hal = "1.0.0"
+embedded-graphics = "0.8.1"
+heapless = { version = "0.9.1", default-features = false }
+micromath = "2.1.0"
+tinybmp = "0.6.0"
+panic-probe = { version = "1.0.0", features = ["defmt"] }
+defmt-rtt = "1.1.0"
+defmt = "1.0.1"
+static_cell = "2.1.1"
+embedded-io-async = "0.6.0"
+embedded-io = "0.6.1"
+
+[dev-dependencies]
+defmt-test = "0.4.0"
--- a/semestralka_1/LICENSE-APACHE
+++ b/semestralka_1/LICENSE-APACHE
@@ -0,0 +1,201 @@
+                              Apache License
+                        Version 2.0, January 2004
+                     http://www.apache.org/licenses/
+
+TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
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+
+APPENDIX: How to apply the Apache License to your work.
+
+   To apply the Apache License to your work, attach the following
+   boilerplate notice, with the fields enclosed by brackets "[]"
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+Copyright [yyyy] [name of copyright owner]
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+Licensed under the Apache License, Version 2.0 (the "License");
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+
+Unless required by applicable law or agreed to in writing, software
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+See the License for the specific language governing permissions and
+limitations under the License.
--- a/semestralka_1/LICENSE-MIT
+++ b/semestralka_1/LICENSE-MIT
@@ -0,0 +1,23 @@
+Permission is hereby granted, free of charge, to any
+person obtaining a copy of this software and associated
+documentation files (the "Software"), to deal in the
+Software without restriction, including without
+limitation the rights to use, copy, modify, merge,
+publish, distribute, sublicense, and/or sell copies of
+the Software, and to permit persons to whom the Software
+is furnished to do so, subject to the following
+conditions:
+
+The above copyright notice and this permission notice
+shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
+ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
+IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.
--- a/semestralka_1/Makefile
+++ b/semestralka_1/Makefile
@@ -0,0 +1,23 @@
+TARGET = thumbv8m.main-none-eabihf
+CHIP = STM32U575ZI
+BIN = stm32u5-blinky
+MODE ?= release
+TARGET_DIR = target/$(TARGET)/$(MODE)
+ELF = $(TARGET_DIR)/$(BIN)
+PROBE = probe-rs
+
+.PHONY: all build flash clean empty
+
+all: build
+
+build:
+	cargo build --$(MODE)
+
+flash: build
+	$(PROBE) run --chip $(CHIP) $(ELF)
+
+empty:
+	$(PROBE) erase --chip $(CHIP)
+
+clean:
+	cargo clean
--- a/semestralka_1/README.md
+++ b/semestralka_1/README.md
@@ -0,0 +1,232 @@
+# `app-template`
+
+> Quickly set up a [`probe-rs`] + [`defmt`] + [`flip-link`] embedded project
+
+[`probe-rs`]: https://crates.io/crates/probe-rs
+[`defmt`]: https://github.com/knurling-rs/defmt
+[`flip-link`]: https://github.com/knurling-rs/flip-link
+
+## Dependencies
+
+### 1. `flip-link`:
+
+```bash
+cargo install flip-link
+```
+
+### 2. `probe-rs`:
+
+Install probe-rs by following the instructions at <https://probe.rs/docs/getting-started/installation/>.
+
+### 3. [`cargo-generate`]:
+
+```bash
+cargo install cargo-generate
+```
+
+[`cargo-generate`]: https://crates.io/crates/cargo-generate
+
+> *Note:* You can also just clone this repository instead of using `cargo-generate`, but this involves additional manual adjustments.
+
+## Setup
+
+### 1. Initialize the project template
+
+```bash
+cargo generate \
+    --git https://github.com/knurling-rs/app-template \
+    --branch main \
+    --name my-app
+```
+
+If you look into your new `my-app` folder, you'll find that there are a few `TODO`s in the files marking the properties you need to set.
+
+Let's walk through them together now.
+
+### 2. Set `probe-rs` chip
+
+Pick a chip from ` probe-rs chip list` and enter it into `.cargo/config.toml`.
+
+If, for example, you have a nRF52840 Development Kit as used in one of [our exercises], replace `{{chip}}` with `nRF52840_xxAA`.
+
+[our workshops]: https://rust-exercises.ferrous-systems.com
+
+```diff
+ # .cargo/config.toml
+-runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format=oneline"]
+runner = ["probe-rs", "run", "--chip", "nRF52840_xxAA", "--log-format=oneline"]
+```
+
+### 3. Adjust the compilation target
+
+In `.cargo/config.toml`, pick the right compilation target for your board.
+
+```diff
+ # .cargo/config.toml
+ [build]
+-target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
+-# target = "thumbv7m-none-eabi"    # Cortex-M3
+-# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
+-# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
+target = "thumbv7em-none-eabihf" # Cortex-M4F (with FPU)
+```
+
+Add the target with `rustup`.
+
+```bash
+rustup target add thumbv7em-none-eabihf
+```
+
+### 4. Add a HAL as a dependency
+
+In `Cargo.toml`, list the Hardware Abstraction Layer (HAL) for your board as a dependency.
+
+For the nRF52840 you'll want to use the [`nrf52840-hal`].
+
+[`nrf52840-hal`]: https://crates.io/crates/nrf52840-hal
+
+```diff
+ # Cargo.toml
+ [dependencies]
+-# some-hal = "1.2.3"
+nrf52840-hal = "0.14.0"
+```
+
+⚠️ Note for RP2040 users ⚠️
+
+You will need to not just specify the `rp-hal` HAL, but a BSP (board support crate) which includes a second stage bootloader. Please find a list of available BSPs [here](https://github.com/rp-rs/rp-hal-boards#packages).
+
+### 5. Import your HAL
+
+Now that you have selected a HAL, fix the HAL import in `src/lib.rs`
+
+```diff
+ // my-app/src/lib.rs
+-// use some_hal as _; // memory layout
+use nrf52840_hal as _; // memory layout
+```
+
+### (6. Get a linker script)
+
+Some HAL crates require that you manually copy over a file called `memory.x` from the HAL to the root of your project. For nrf52840-hal, this is done automatically so no action is needed. For other HAL crates, see their documentation on where to find an example file.
+
+The `memory.x` file should look something like:
+
+```text
+MEMORY
+{
+  FLASH : ORIGIN = 0x00000000, LENGTH = 1024K
+  RAM   : ORIGIN = 0x20000000, LENGTH = 256K
+}
+```
+
+The `memory.x` file is included in the `cortex-m-rt` linker script `link.x`, and so `link.x` is the one you should tell `rustc` to use (see the `.cargo/config.toml` file where we do that).
+
+### 7. Run!
+
+You are now all set to `cargo-run` your first `defmt`-powered application!
+There are some examples in the `src/bin` directory.
+
+Start by `cargo run`-ning `my-app/src/bin/hello.rs`:
+
+```console
+$ # `rb` is an alias for `run --bin`
+$ cargo rb hello
+    Finished `dev` profile [optimized + debuginfo] target(s) in 0.01s
+     Running `probe-rs run --chip nrf52840_xxaa --log-format=oneline target/thumbv6m-none-eabi/debug/hello`
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.79 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+Hello, world!
+
+$ echo $?
+0
+```
+
+If you're running out of memory (`flip-link` bails with an overflow error), you can decrease the size of the device memory buffer by setting the `DEFMT_RTT_BUFFER_SIZE` environment variable. The default value is 1024 bytes, and powers of two should be used for optimal performance:
+
+```console
+$ DEFMT_RTT_BUFFER_SIZE=64 cargo rb hello
+```
+
+### (8. Set `rust-analyzer.linkedProjects`)
+
+If you are using [rust-analyzer] with VS Code for IDE-like features you can add following configuration to your `.vscode/settings.json` to make it work transparently across workspaces. Find the details of this option in the [RA docs].
+
+```json
+{
+    "rust-analyzer.linkedProjects": [
+        "Cargo.toml",
+        "firmware/Cargo.toml",
+    ]
+}
+```
+
+[RA docs]: https://rust-analyzer.github.io/manual.html#configuration
+[rust-analyzer]: https://rust-analyzer.github.io/
+
+## Running tests
+
+The template comes configured for running unit tests and integration tests on the target.
+
+Unit tests reside in the library crate and can test private API; the initial set of unit tests are in `src/lib.rs`.
+`cargo test --lib` will run those unit tests.
+
+```console
+$ cargo test --lib
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.15s
+     Running unittests src/lib.rs (target/thumbv6m-none-eabi/debug/deps/example-2b0d0e25d141bf57)
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.99 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.33 KiB/s (took 1s)                                                                                                                        Finished in 1.10s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Integration tests reside in the `tests` directory; the initial set of integration tests are in `tests/integration.rs`.
+`cargo test --test integration` will run those integration tests.
+Note that the argument of the `--test` flag must match the name of the test file in the `tests` directory.
+
+```console
+$ cargo test --test integration
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.10s
+     Running tests/integration.rs (target/thumbv6m-none-eabi/debug/deps/integration-aaaff41151f6a722)
+      Erasing ✔ 100% [####################]   8.00 KiB @  16.03 KiB/s (took 0s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Note that to add a new test file to the `tests` directory you also need to add a new `[[test]]` section to `Cargo.toml`.
+
+To run all the tests via `cargo test` the tests need to be explicitly disabled for all the existing binary targets.
+See `Cargo.toml` for details on how to do this.
+
+## Support
+
+`app-template` is part of the [Knurling] project, [Ferrous Systems]' effort at
+improving tooling used to develop for embedded systems.
+
+If you think that our work is useful, consider sponsoring it via [GitHub
+Sponsors].
+
+## License
+
+Licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+  http://www.apache.org/licenses/LICENSE-2.0)
+
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+### Contribution
+
+Unless you explicitly state otherwise, any contribution intentionally submitted
+for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
+licensed as above, without any additional terms or conditions.
+
+[Knurling]: https://knurling.ferrous-systems.com
+[Ferrous Systems]: https://ferrous-systems.com/
+[GitHub Sponsors]: https://github.com/sponsors/knurling-rs
--- a/semestralka_1/datasheet.txt
+++ b/semestralka_1/datasheet.txt
@@ -0,0 +1 @@
+https://www.ti.com/lit/ug/sprugp1/sprugp1.pdf?ts=1761641486453
--- a/semestralka_1/src/bin/main.rs
+++ b/semestralka_1/src/bin/main.rs
@@ -0,0 +1,157 @@
+// src/bin/main.rs
+
+#![no_std]
+#![no_main]
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::bind_interrupts;
+use embassy_stm32::peripherals;
+use embassy_stm32::peripherals::{PA2, PA3};
+use embassy_stm32::gpio::{Input, Output, Pull, Speed, Level};
+use embassy_stm32::Peripherals;
+use embassy_stm32::usart::{BufferedInterruptHandler, BufferedUart, Config};
+use embassy_stm32::timer::low_level::Timer as HardwareTimer;
+use embassy_stm32::interrupt::{self, typelevel::TIM2 as TIM2_IRQ, Priority};
+use embassy_stm32::peripherals::TIM2;
+use embedded_io_async::{Read, Write};
+use embassy_stm32::time::Hertz;
+use embassy_time::{Timer, Duration, Instant};
+use embassy_futures::yield_now;
+use embassy_futures::select::{select, Either};
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+use embassy_sync::signal::Signal;
+use static_cell::StaticCell;
+use {defmt_rtt as _, panic_probe as _};
+use async_uart::safety::{preflight_and_suggest_yield_period, RX_PIPE_CAP, TX_PIPE_CAP};
+
+static UART_TX: Pipe<CriticalSectionRawMutex, TX_PIPE_CAP> = Pipe::new();
+static UART_RX: Pipe<CriticalSectionRawMutex, RX_PIPE_CAP> = Pipe::new();
+static TIM2_TICK: Signal<CriticalSectionRawMutex, ()> = Signal::new();
+
+bind_interrupts!(
+    struct Irqs {
+        USART1 => BufferedInterruptHandler<peripherals::USART1>;
+    }
+);
+
+#[embassy_executor::task]
+async fn uart_task(mut uart: BufferedUart<'static>) {
+    let mut rx_byte = [0u8; 1];
+    let mut tx_buf = [0u8; 64];
+    loop {
+        // Wait for either RX or TX events.
+        let rx_fut = uart.read(&mut rx_byte);
+        let tx_fut = async {
+            // Until there's outgoing data in TX pipe
+            let n = UART_TX.read(&mut tx_buf).await;
+            n
+        };
+        match select(rx_fut, tx_fut).await {
+            // Incoming data from UART hardware
+            Either::First(res) => {
+                if let Ok(_) = res {
+                    // Forward to RX pipe
+                    let _ = UART_RX.write(&rx_byte).await;
+                    let _ = UART_TX.try_write(&rx_byte);
+                }
+            }
+            // Outgoing data waiting in TX pipe
+            Either::Second(n) => {
+                unwrap!(uart.write(&tx_buf[..n]).await);
+            }
+        }
+    }
+}
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    info!("tititititi");
+    let p = embassy_stm32::init(Default::default());
+    static TX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
+    static RX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
+    let tx_buf = TX_BUF.init([0; 256]);
+    let rx_buf = RX_BUF.init([0; 256]);
+    let mut cfg = Config::default();
+    cfg.baudrate = 230_400;
+
+    // Call preflight and get the computed yield period
+    let yield_period = preflight_and_suggest_yield_period(cfg.baudrate);
+
+    let usart = BufferedUart::new(
+        p.USART1,
+        p.PA10, // RX
+        p.PA9,  // TX
+        tx_buf,
+        rx_buf,
+        Irqs,
+        cfg,
+    ).unwrap();
+    info!("starting uart task");
+    spawner.spawn(uart_task(usart)).unwrap();
+
+    let mut transfer: u32 = 16;
+    let mut rx_buf = [0u8; 64];
+    let mut last_yield = Instant::now();
+
+    // Software UART bits init
+    let mut tx = Output::new(p.PA2, Level::Low, Speed::Low);
+    let _rx = Input::new(p.PA3, Pull::Up);
+
+    let tim = HardwareTimer::new(p.TIM2);
+
+    // Configure for 230_400 Hz
+    tim.set_frequency(Hertz(cfg.baudrate*transfer));
+    tim.enable_update_interrupt(true);
+    tim.start();
+
+    tx.set_high();
+    loop {
+
+        TIM2_TICK.wait().await;
+        tx.set_low();
+        TIM2_TICK.wait().await;
+
+        Timer::after(Duration::from_millis(1000)).await;
+        // Poll RX pipe for new data (non-blocking)
+        if let Ok(n) = UART_RX.try_read(&mut rx_buf) {
+            if n > 0 {
+                if let Ok(s) = core::str::from_utf8(&rx_buf[..n]) {
+                    info!("RX got: {}", s);
+                } else {
+                    info!("RX got (non‑utf8): {:?}", &rx_buf[..n]);
+                }
+            }
+        }
+
+        // Guaranteed to yield before ISR RX buffer can overflow
+        if Instant::now().duration_since(last_yield) >= yield_period {
+            yield_now().await;
+            last_yield = Instant::now();
+            // info!("Yield mf {}", counter);
+        }
+        // Timer::after(Duration::from_micros(1)).await;
+        // Timer::after(Duration::from_secs(5)).await;
+    }
+}
+
+#[embassy_stm32::interrupt]
+fn TIM2() {
+    use embassy_stm32::timer::CoreInstance;
+
+    // Access TIM2 core registers directly.
+    let regs = unsafe {
+        embassy_stm32::pac::timer::TimCore::from_ptr(
+            <peripherals::TIM2 as CoreInstance>::regs(),
+        )
+    };
+
+    // Clear update flag to avoid retriggering.
+    let sr = regs.sr().read();
+    if sr.uif() {
+        regs.sr().modify(|r| r.set_uif(false));
+
+        // Signal the waiting task that a tick occurred.
+        TIM2_TICK.signal(());
+    }
+}
--- a/semestralka_1/src/lib.rs
+++ b/semestralka_1/src/lib.rs
@@ -0,0 +1,3 @@
+#![no_std]
+pub mod safety;
+// pub mod software_uart;
--- a/semestralka_1/src/safety.rs
+++ b/semestralka_1/src/safety.rs
@@ -0,0 +1,57 @@
+// src/safety.rs
+use defmt::info;
+use embassy_time::Duration;
+
+// ISR RX ring capacity = RX_BUF len
+const ISR_RX_BUF_CAP: usize = 256;
+// Yield 1/2 the time it takes to fill ISR RX ring.
+const YIELD_MARGIN_NUM: u32 = 1;
+const YIELD_MARGIN_DEN: u32 = 2;
+// Ensure RX_PIPE_CAP can hold this.
+const WORST_MAIN_LATENCY_MS: u32 = 20;
+
+pub const TX_PIPE_CAP: usize = 1024;
+pub const RX_PIPE_CAP: usize = 1024;
+
+
+
+/// Perform safety checks and compute yield timing to avoid buffer overflow.
+///
+/// # Panics
+/// Panics if pipe capacities are too small for the configured baud.
+pub fn preflight_and_suggest_yield_period(baud: u32) -> Duration {
+    // Approx bytes per second for 8N1 (10 bits per byte on the wire)
+    let bytes_per_sec = (baud / 10).max(1);
+
+    // Time until ISR RX ring fills, in microseconds.
+    let t_fill_us = (ISR_RX_BUF_CAP as u64) * 1_000_000u64 / (bytes_per_sec as u64);
+
+    // Choose a yield period as a fraction of t_fill.
+    let yield_us = (t_fill_us as u64)
+        .saturating_mul(YIELD_MARGIN_NUM as u64)
+        / (YIELD_MARGIN_DEN as u64);
+
+    // Verify RX pipe can absorb a worst-case app latency so uart_task
+    // can always forward without dropping when it runs.
+    let required_rx_pipe = (bytes_per_sec as u64) * (WORST_MAIN_LATENCY_MS as u64) / 1000;
+
+    if (RX_PIPE_CAP as u64) < required_rx_pipe {
+        core::panic!(
+            "RX pipe too small: have {}B, need >= {}B for {}ms at {} bps",
+            RX_PIPE_CAP, required_rx_pipe, WORST_MAIN_LATENCY_MS, baud
+        );
+    }
+
+    info!(
+        "Preflight: baud={}, rx_isr={}B, rx_pipe={}B, bytes/s={}, t_fill_us={}, yield_us={}",
+        baud,
+        ISR_RX_BUF_CAP,
+        RX_PIPE_CAP,
+        bytes_per_sec,
+        t_fill_us,
+        yield_us
+    );
+
+    // Never choose zero.
+    Duration::from_micros(yield_us.max(1) as u64)
+}
--- a/semestralka_1/src/software_uart/mod.rs
+++ b/semestralka_1/src/software_uart/mod.rs
@@ -0,0 +1,4 @@
+// src/software_uart/mod.rs
+
+pub mod suart;
+pub use suart::*;
--- a/semestralka_1/src/software_uart/suart.rs
+++ b/semestralka_1/src/software_uart/suart.rs
@@ -0,0 +1,19 @@
+// src/software_uart/suart.rs
+
+use embassy_stm32::peripherals::{PA2, PA3};
+use embassy_stm32::gpio::{Input, Output, Pull, Speed, Level};
+use embassy_stm32::Peripherals;
+use embassy_time::Timer;
+
+pub async fn suart_test(mut tx_pin: PA2, rx_pin: PA3) {
+    let mut tx = Output::new(tx_pin.into(), Level::Low, Speed::Low);
+    let _rx = Input::new(rx_pin.into(), Pull::Up);
+
+    loop {
+        tx.set_high();
+        Timer::after_millis(500).await;
+
+        tx.set_low();
+        Timer::after_millis(500).await;
+    }
+}
--- a/semestralka_1/tests/integration.rs
+++ b/semestralka_1/tests/integration.rs
@@ -0,0 +1,14 @@
+#![no_std]
+#![no_main]
+
+// See https://crates.io/crates/defmt-test/0.3.0 for more documentation (e.g. about the 'state'
+// feature)
+#[defmt_test::tests]
+mod tests {
+    use defmt::assert;
+
+    #[test]
+    fn it_works() {
+        assert!(true)
+    }
+}
--- a/stm32u5-blinky/.cargo/config.toml
+++ b/stm32u5-blinky/.cargo/config.toml
@@ -1,27 +0,0 @@
-[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# TODO(2) replace `$CHIP` with your chip's name (see `probe-rs chip list` output)
-runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format=oneline"]
-# If you have an nRF52, you might also want to add "--allow-erase-all" to the list
-
-rustflags = [
-  "-C", "linker=flip-link",
-  "-C", "link-arg=-Tlink.x",
-  "-C", "link-arg=-Tdefmt.x",
-  # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x
-  # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95
-  "-C", "link-arg=--nmagic",
-]
-
-[build]
-# TODO(3) Adjust the compilation target.
-# Select the correct target for your processor:
-# target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
-# target = "thumbv7m-none-eabi"    # Cortex-M3
-# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
-target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
-
-[alias]
-# `cargo rb foo` will expand to `cargo run --bin foo`
-rb = "run --bin"
-# `cargo rrb foo` will expand to `cargo run --release --bin foo`
-rrb = "run --release --bin"
--- a/stm32u5-blinky/.gitignore
+++ b/stm32u5-blinky/.gitignore
@@ -1,2 +0,0 @@
-/target
-Cargo.lock
--- a/stm32u5-blinky/.vscode/settings.json
+++ b/stm32u5-blinky/.vscode/settings.json
@@ -1,9 +0,0 @@
-{
-    // override the default setting (`cargo check --all-targets`) which produces the following error
-    // "can't find crate for `test`" when the default compilation target is a no_std target
-    // with these changes RA will call `cargo check --bins` on save
-    "rust-analyzer.check.allTargets": false,
-    "rust-analyzer.check.extraArgs": [
-        "--bins"
-    ]
-}
--- a/stm32u5-blinky/Cargo.toml
+++ b/stm32u5-blinky/Cargo.toml
@@ -1,85 +0,0 @@
-[package]
-# TODO(1) fix `authors` and `name` if you didn't use `cargo-generate`
-authors = ["Priec <filippriec@gmail.com>"]
-name = "stm32u5-blinky"
-edition = "2024"
-version = "0.1.0"
-
-
-# To run all the tests via `cargo test` the tests need to be explicitly disabled for the binary targets
-# If you use a standard main.rs file the following is sufficient:
-# [[bin]]
-# name = "stm32u5-blinky"
-# test = false
-
-[[bin]]
-name = "bitfield"
-path = "src/bin/bitfield.rs"
-test = false
-
-[[bin]]
-name = "format"
-path = "src/bin/format.rs"
-test = false
-
-[[bin]]
-name = "hello"
-path = "src/bin/hello.rs"
-test = false
-
-[[bin]]
-name = "levels"
-path = "src/bin/levels.rs"
-test = false
-
-[[bin]]
-name = "overflow"
-path = "src/bin/overflow.rs"
-test = false
-
-[[bin]]
-name = "panic"
-path = "src/bin/panic.rs"
-test = false
-
-[lib]
-harness = false
-
-# needed for each integration test
-[[test]]
-name = "integration"
-harness = false
-
-[dependencies]
-cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
-cortex-m-rt = "0.7"
-defmt = "1.0"
-defmt-rtt = "1.0"
-panic-probe = { version = "1.0", features = ["print-defmt"] }
-semihosting = "0.1.20"
-# TODO(4) enter your HAL here
-# some-hal = "1.2.3"
-
-[dev-dependencies]
-defmt-test = "0.3"
-
-# cargo build/run
-[profile.dev]
-# default is opt-level = '0', but that makes very
-# verbose machine code
-opt-level = 's'
-# trade compile speed for slightly better optimisations
-codegen-units = 1
-
-# cargo build/run --release
-[profile.release]
-# default is opt-level = '3', but that makes quite
-# verbose machine code
-opt-level = 's'
-# trade compile speed for slightly better optimisations
-codegen-units = 1
-# Use Link Time Optimisations to further inline things across
-# crates
-lto = 'fat'
-# Leave the debug symbols in (default is no debug info)
-debug = 2
--- a/stm32u5-blinky/memory.x
+++ b/stm32u5-blinky/memory.x
@@ -1,13 +0,0 @@
-/* memory.x - STM32U575ZITxQ memory layout */
-
-/* Flash: 2 MB starting at 0x08000000 */
-/* SRAM1 + SRAM2 + SRAM3 total 786 KB starting at 0x20000000 */
-
-MEMORY
-{
-  FLASH (rx)  : ORIGIN = 0x08000000, LENGTH = 2048K
-  RAM   (xrw) : ORIGIN = 0x20000000, LENGTH = 786K
-}
-
-/* provide stack start symbol (end of RAM) */
-_stack_start = ORIGIN(RAM) + LENGTH(RAM);
--- a/stm32u5-blinky/src/bin/bitfield.rs
+++ b/stm32u5-blinky/src/bin/bitfield.rs
@@ -1,13 +0,0 @@
-#![no_main]
-#![no_std]
-
-use stm32u5_blinky as _; // global logger + panicking-behavior + memory layout
-
-#[cortex_m_rt::entry]
-fn main() -> ! {
-    // value of the FREQUENCY register (nRF52840 device; RADIO peripheral)
-    let frequency: u32 = 276;
-    defmt::println!("FREQUENCY: {0=0..7}, MAP: {0=8..9}", frequency);
-
-    stm32u5_blinky::exit()
-}
--- a/stm32u5-blinky/src/bin/format.rs
+++ b/stm32u5-blinky/src/bin/format.rs
@@ -1,29 +0,0 @@
-#![no_main]
-#![no_std]
-
-use stm32u5_blinky as _; // global logger + panicking-behavior + memory layout
-use defmt::Format; // <- derive attribute
-
-#[derive(Format)]
-struct S1<T> {
-    x: u8,
-    y: T,
-}
-
-#[derive(Format)]
-struct S2 {
-    z: u8,
-}
-
-#[cortex_m_rt::entry]
-fn main() -> ! {
-    let s = S1 {
-        x: 42,
-        y: S2 { z: 43 },
-    };
-    defmt::println!("s={:?}", s);
-    let x = 42;
-    defmt::println!("x={=u8}", x);
-
-    stm32u5_blinky::exit()
-}
--- a/stm32u5-blinky/src/bin/hello.rs
+++ b/stm32u5-blinky/src/bin/hello.rs
@@ -1,11 +0,0 @@
-#![no_main]
-#![no_std]
-
-use stm32u5_blinky as _; // global logger + panicking-behavior + memory layout
-
-#[cortex_m_rt::entry]
-fn main() -> ! {
-    defmt::println!("Hello, world!");
-
-    stm32u5_blinky::exit()
-}
--- a/stm32u5-blinky/src/bin/levels.rs
+++ b/stm32u5-blinky/src/bin/levels.rs
@@ -1,17 +0,0 @@
-#![no_main]
-#![no_std]
-
-use stm32u5_blinky as _; // global logger + panicking-behavior + memory layout
-
-#[cortex_m_rt::entry]
-fn main() -> ! {
-    // try setting the DEFMT_LOG environment variable
-    // e.g. `export DEFMT_LOG=info` or `DEFMT_LOG=trace cargo rb levels`
-    defmt::info!("info");
-    defmt::trace!("trace");
-    defmt::warn!("warn");
-    defmt::debug!("debug");
-    defmt::error!("error");
-
-    stm32u5_blinky::exit()
-}
--- a/stm32u5-blinky/src/bin/overflow.rs
+++ b/stm32u5-blinky/src/bin/overflow.rs
@@ -1,28 +0,0 @@
-#![no_main]
-#![no_std]
-
-use stm32u5_blinky as _; // global logger + panicking-behavior + memory layout
-
-#[cortex_m_rt::entry]
-fn main() -> ! {
-    ack(10, 10);
-    stm32u5_blinky::exit()
-}
-
-fn ack(m: u32, n: u32) -> u32 {
-    // waste stack space to trigger a stack overflow
-    let mut buffer = [0u8; 16 * 1024];
-    // estimate of the Stack Pointer register
-    let sp = buffer.as_mut_ptr();
-    defmt::println!("ack(m={=u32}, n={=u32}, SP={:x})", m, n, sp);
-
-    if m == 0 {
-        n + 1
-    } else {
-        if n == 0 {
-            ack(m - 1, 1)
-        } else {
-            ack(m - 1, ack(m, n - 1))
-        }
-    }
-}
--- a/stm32u5-blinky/src/bin/panic.rs
+++ b/stm32u5-blinky/src/bin/panic.rs
@@ -1,11 +0,0 @@
-#![no_main]
-#![no_std]
-
-use stm32u5_blinky as _; // global logger + panicking-behavior + memory layout
-
-#[cortex_m_rt::entry]
-fn main() -> ! {
-    defmt::println!("main");
-
-    defmt::panic!()
-}
--- a/stm32u5-blinky/src/lib.rs
+++ b/stm32u5-blinky/src/lib.rs
@@ -1,46 +0,0 @@
-#![no_main]
-#![no_std]
-
-use defmt_rtt as _; // global logger
-
-// TODO(5) adjust HAL import
-// use some_hal as _; // memory layout
-
-use panic_probe as _;
-
-// same panicking *behavior* as `panic-probe` but doesn't print a panic message
-// this prevents the panic message being printed *twice* when `defmt::panic` is invoked
-#[defmt::panic_handler]
-fn panic() -> ! {
-    cortex_m::asm::udf()
-}
-
-/// Terminates the application and makes a semihosting-capable debug tool exit
-/// with status code 0.
-pub fn exit() -> ! {
-    semihosting::process::exit(0);
-}
-
-/// Hardfault handler.
-///
-/// Terminates the application and makes a semihosting-capable debug tool exit
-/// with an error. This seems better than the default, which is to spin in a
-/// loop.
-#[cortex_m_rt::exception]
-unsafe fn HardFault(_frame: &cortex_m_rt::ExceptionFrame) -> ! {
-    semihosting::process::exit(1);
-}
-
-// defmt-test 0.3.0 has the limitation that this `#[tests]` attribute can only be used
-// once within a crate. the module can be in any file but there can only be at most
-// one `#[tests]` module in this library crate
-#[cfg(test)]
-#[defmt_test::tests]
-mod unit_tests {
-    use defmt::assert;
-
-    #[test]
-    fn it_works() {
-        assert!(true)
-    }
-}
--- a/tim2/.cargo/config.toml
+++ b/tim2/.cargo/config.toml
@@ -1,27 +0,0 @@
-[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# TODO(2) replace `$CHIP` with your chip's name (see `probe-rs chip list` output)
-runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format=oneline"]
-# If you have an nRF52, you might also want to add "--allow-erase-all" to the list
-
-rustflags = [
-  "-C", "linker=flip-link",
-  "-C", "link-arg=-Tlink.x",
-  "-C", "link-arg=-Tdefmt.x",
-  # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x
-  # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95
-  "-C", "link-arg=--nmagic",
-]
-
-[build]
-# TODO(3) Adjust the compilation target.
-# Select the correct target for your processor:
-# target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
-# target = "thumbv7m-none-eabi"    # Cortex-M3
-# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
-target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
-
-[alias]
-# `cargo rb foo` will expand to `cargo run --bin foo`
-rb = "run --bin"
-# `cargo rrb foo` will expand to `cargo run --release --bin foo`
-rrb = "run --release --bin"
--- a/tim2/.gitignore
+++ b/tim2/.gitignore
@@ -1,2 +0,0 @@
-/target
-Cargo.lock
--- a/tim2/Cargo.toml
+++ b/tim2/Cargo.toml
@@ -1,55 +0,0 @@
-[package]
-# TODO(1) fix `authors` and `name` if you didn't use `cargo-generate`
-authors = ["Priec <filippriec@gmail.com>"]
-name = "stm32u5-tim2"
-edition = "2024"
-version = "0.1.0"
-
-[[bin]]
-name = "main"
-path = "src/bin/main.rs"
-test = false
-
-[lib]
-harness = false
-
-# needed for each integration test
-[[test]]
-name = "integration"
-harness = false
-
-[dependencies]
-cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
-cortex-m-rt = "0.7"
-defmt = "1.0"
-defmt-rtt = "1.0"
-panic-halt = "1.0.0"
-panic-probe = { version = "1.0", features = ["print-defmt"] }
-semihosting = "0.1.20"
-stm32u5 = { version = "0.16.0", features = ["rt", "stm32u575"] }
-# TODO(4) enter your HAL here
-# some-hal = "1.2.3"
-
-[dev-dependencies]
-defmt-test = "0.3"
-
-# cargo build/run
-[profile.dev]
-# default is opt-level = '0', but that makes very
-# verbose machine code
-opt-level = 's'
-# trade compile speed for slightly better optimisations
-codegen-units = 1
-
-# cargo build/run --release
-[profile.release]
-# default is opt-level = '3', but that makes quite
-# verbose machine code
-opt-level = 's'
-# trade compile speed for slightly better optimisations
-codegen-units = 1
-# Use Link Time Optimisations to further inline things across
-# crates
-lto = 'fat'
-# Leave the debug symbols in (default is no debug info)
-debug = 2
--- a/tim2/memory.x
+++ b/tim2/memory.x
@@ -1,13 +0,0 @@
-/* memory.x - STM32U575ZITxQ memory layout */
-
-/* Flash: 2 MB starting at 0x08000000 */
-/* SRAM1 + SRAM2 + SRAM3 total 786 KB starting at 0x20000000 */
-
-MEMORY
-{
-  FLASH (rx)  : ORIGIN = 0x08000000, LENGTH = 2048K
-  RAM   (xrw) : ORIGIN = 0x20000000, LENGTH = 786K
-}
-
-/* provide stack start symbol (end of RAM) */
-_stack_start = ORIGIN(RAM) + LENGTH(RAM);
--- a/tim2/src/bin/main.rs
+++ b/tim2/src/bin/main.rs
@@ -1,70 +0,0 @@
-#![no_std]
-#![no_main]
-
-use cortex_m_rt::entry;
-use panic_halt as _;
-use stm32u5::stm32u575 as pac;
-use pac::interrupt; // Import the interrupt enum
-
-// Timer frequency constants
-const PRESCALER: u16 = 0;
-const PULSE1_VALUE: u32 = 50000; // For 800 Hz toggle
-
-#[entry]
-fn main() -> ! {
-    let dp = pac::Peripherals::take().unwrap();
-    dp.RCC.apb1enr1().modify(|_, w| w.tim2en().set_bit());
-    
-    // Enable GPIOA clock for TIM2_CH4 (PA3)
-    dp.RCC.ahb2enr1().modify(|_, w| w.gpioaen().set_bit());
-    
-    // Configure PA3 as AF1 (TIM2_CH4)
-    dp.GPIOA.moder().modify(|_, w| w.mode3().alternate());
-    dp.GPIOA.afrl().modify(|_, w| w.afrel3().af1());
-    
-    // Configure TIM2
-    dp.TIM2.psc().write(|w| unsafe { w.bits(PRESCALER as u32) });
-    dp.TIM2.arr().write(|w| unsafe { w.bits(0xFFFF_FFFF) }); // Max for 32-bit timer
-    
-    // Configure CH4 for output compare toggle mode
-    dp.TIM2.ccmr2_output().modify(|_, w| unsafe {
-        w.cc4s().bits(0b00)    // CH4 as output
-         .oc4m().bits(0b011)    // Toggle mode
-    });
-    
-    // Set initial compare value
-    dp.TIM2.ccr4().write(|w| unsafe { w.bits(PULSE1_VALUE) });
-    
-    // Enable CH4 output
-    dp.TIM2.ccer().modify(|_, w| w.cc4e().set_bit());
-    
-    // Enable CH4 interrupt
-    dp.TIM2.dier().modify(|_, w| w.cc4ie().set_bit());
-    
-    // Enable TIM2 interrupt in NVIC
-    unsafe {
-        cortex_m::peripheral::NVIC::unmask(pac::Interrupt::TIM2);
-    }
-    
-    // Start timer
-    dp.TIM2.cr1().modify(|_, w| w.cen().set_bit());
-    
-    loop {
-        cortex_m::asm::wfi(); // Wait for interrupt
-    }
-}
-
-#[interrupt]
-fn TIM2() {
-    unsafe {
-        let tim2 = &(*pac::TIM2::ptr());
-        if tim2.sr().read().cc4if().bit_is_set() {
-            tim2.sr().modify(|_, w| w.cc4if().clear_bit());
-
-            // Use wrapping arithmetic
-            let current = tim2.ccr4().read().bits();
-            let next = current.wrapping_add(PULSE1_VALUE);
-            tim2.ccr4().write(|w| w.bits(next));
-        }
-    }
-}
--- a/tim2/src/lib.rs
+++ b/tim2/src/lib.rs
@@ -1,46 +0,0 @@
-#![no_main]
-#![no_std]
-
-use defmt_rtt as _; // global logger
-
-// TODO(5) adjust HAL import
-// use some_hal as _; // memory layout
-
-use panic_probe as _;
-
-// same panicking *behavior* as `panic-probe` but doesn't print a panic message
-// this prevents the panic message being printed *twice* when `defmt::panic` is invoked
-#[defmt::panic_handler]
-fn panic() -> ! {
-    cortex_m::asm::udf()
-}
-
-/// Terminates the application and makes a semihosting-capable debug tool exit
-/// with status code 0.
-pub fn exit() -> ! {
-    semihosting::process::exit(0);
-}
-
-/// Hardfault handler.
-///
-/// Terminates the application and makes a semihosting-capable debug tool exit
-/// with an error. This seems better than the default, which is to spin in a
-/// loop.
-#[cortex_m_rt::exception]
-unsafe fn HardFault(_frame: &cortex_m_rt::ExceptionFrame) -> ! {
-    semihosting::process::exit(1);
-}
-
-// defmt-test 0.3.0 has the limitation that this `#[tests]` attribute can only be used
-// once within a crate. the module can be in any file but there can only be at most
-// one `#[tests]` module in this library crate
-#[cfg(test)]
-#[defmt_test::tests]
-mod unit_tests {
-    use defmt::assert;
-
-    #[test]
-    fn it_works() {
-        assert!(true)
-    }
-}
--- a/time_meas/.cargo/config.toml
+++ b/time_meas/.cargo/config.toml
@@ -0,0 +1,15 @@
+[build]
+target = "thumbv8m.main-none-eabihf"
+
+[target.thumbv8m.main-none-eabihf]
+runner = "probe-rs run --chip STM32U575ZITxQ"
+
+rustflags = [
+  "-C", "linker=rust-lld",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "link-arg=-Tdefmt.x",
+  "-C", "link-arg=--nmagic",
+]
+
+[package.metadata.cargo-flash]
+chip = "STM32U575ZIT"
--- a/time_meas/.gitignore
+++ b/time_meas/.gitignore
@@ -0,0 +1 @@
+/target
--- a/time_meas/Cargo.lock
+++ b/time_meas/Cargo.lock
--- a/time_meas/Cargo.toml
+++ b/time_meas/Cargo.toml
@@ -0,0 +1,30 @@
+[package]
+authors = ["Priec <filippriec@gmail.com>"]
+name = "hal_rng"
+edition = "2024"
+version = "0.1.0"
+
+
+[dependencies]
+cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.5"
+panic-halt = "1.0.0"
+
+embassy-executor = { version = "0.9.1", features = ["arch-cortex-m", "executor-thread"] }
+embassy-futures = "0.1.2"
+embassy-stm32 = { version = "0.4.0", features = ["unstable-pac", "stm32u575zi", "time-driver-any", "memory-x", "defmt"] }
+embassy-sync = "0.7.2"
+embassy-time = { version = "0.5.0", features = ["tick-hz-32_768"] }
+embassy-usb = "0.5.1"
+
+embedded-hal = "1.0.0"
+embedded-graphics = "0.8.1"
+heapless = { version = "0.9.1", default-features = false }
+micromath = "2.1.0"
+tinybmp = "0.6.0"
+panic-probe = { version = "1.0.0", features = ["defmt"] }
+defmt-rtt = "1.1.0"
+defmt = "1.0.1"
+static_cell = "2.1.1"
+embedded-io-async = "0.6.0"
+embedded-io = "0.6.1"
--- a/time_meas/LICENSE-APACHE
+++ b/time_meas/LICENSE-APACHE
@@ -0,0 +1,201 @@
+                              Apache License
+                        Version 2.0, January 2004
+                     http://www.apache.org/licenses/
+
+TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
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+8. Limitation of Liability. In no event and under no legal theory,
+   whether in tort (including negligence), contract, or otherwise,
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+   negligent acts) or agreed to in writing, shall any Contributor be
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--- a/time_meas/LICENSE-MIT
+++ b/time_meas/LICENSE-MIT
@@ -0,0 +1,23 @@
+Permission is hereby granted, free of charge, to any
+person obtaining a copy of this software and associated
+documentation files (the "Software"), to deal in the
+Software without restriction, including without
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+The above copyright notice and this permission notice
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+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
+ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
+IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.
--- a/time_meas/Makefile
+++ b/time_meas/Makefile
@@ -0,0 +1,23 @@
+TARGET = thumbv8m.main-none-eabihf
+CHIP = STM32U575ZI
+BIN = stm32u5-blinky
+MODE ?= release
+TARGET_DIR = target/$(TARGET)/$(MODE)
+ELF = $(TARGET_DIR)/$(BIN)
+PROBE = probe-rs
+
+.PHONY: all build flash clean empty
+
+all: build
+
+build:
+	cargo build --$(MODE)
+
+flash: build
+	$(PROBE) run --chip $(CHIP) $(ELF)
+
+empty:
+	$(PROBE) erase --chip $(CHIP)
+
+clean:
+	cargo clean
--- a/time_meas/README.md
+++ b/time_meas/README.md
@@ -0,0 +1,232 @@
+# `app-template`
+
+> Quickly set up a [`probe-rs`] + [`defmt`] + [`flip-link`] embedded project
+
+[`probe-rs`]: https://crates.io/crates/probe-rs
+[`defmt`]: https://github.com/knurling-rs/defmt
+[`flip-link`]: https://github.com/knurling-rs/flip-link
+
+## Dependencies
+
+### 1. `flip-link`:
+
+```bash
+cargo install flip-link
+```
+
+### 2. `probe-rs`:
+
+Install probe-rs by following the instructions at <https://probe.rs/docs/getting-started/installation/>.
+
+### 3. [`cargo-generate`]:
+
+```bash
+cargo install cargo-generate
+```
+
+[`cargo-generate`]: https://crates.io/crates/cargo-generate
+
+> *Note:* You can also just clone this repository instead of using `cargo-generate`, but this involves additional manual adjustments.
+
+## Setup
+
+### 1. Initialize the project template
+
+```bash
+cargo generate \
+    --git https://github.com/knurling-rs/app-template \
+    --branch main \
+    --name my-app
+```
+
+If you look into your new `my-app` folder, you'll find that there are a few `TODO`s in the files marking the properties you need to set.
+
+Let's walk through them together now.
+
+### 2. Set `probe-rs` chip
+
+Pick a chip from ` probe-rs chip list` and enter it into `.cargo/config.toml`.
+
+If, for example, you have a nRF52840 Development Kit as used in one of [our exercises], replace `{{chip}}` with `nRF52840_xxAA`.
+
+[our workshops]: https://rust-exercises.ferrous-systems.com
+
+```diff
+ # .cargo/config.toml
+-runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format=oneline"]
+runner = ["probe-rs", "run", "--chip", "nRF52840_xxAA", "--log-format=oneline"]
+```
+
+### 3. Adjust the compilation target
+
+In `.cargo/config.toml`, pick the right compilation target for your board.
+
+```diff
+ # .cargo/config.toml
+ [build]
+-target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
+-# target = "thumbv7m-none-eabi"    # Cortex-M3
+-# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
+-# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
+target = "thumbv7em-none-eabihf" # Cortex-M4F (with FPU)
+```
+
+Add the target with `rustup`.
+
+```bash
+rustup target add thumbv7em-none-eabihf
+```
+
+### 4. Add a HAL as a dependency
+
+In `Cargo.toml`, list the Hardware Abstraction Layer (HAL) for your board as a dependency.
+
+For the nRF52840 you'll want to use the [`nrf52840-hal`].
+
+[`nrf52840-hal`]: https://crates.io/crates/nrf52840-hal
+
+```diff
+ # Cargo.toml
+ [dependencies]
+-# some-hal = "1.2.3"
+nrf52840-hal = "0.14.0"
+```
+
+⚠️ Note for RP2040 users ⚠️
+
+You will need to not just specify the `rp-hal` HAL, but a BSP (board support crate) which includes a second stage bootloader. Please find a list of available BSPs [here](https://github.com/rp-rs/rp-hal-boards#packages).
+
+### 5. Import your HAL
+
+Now that you have selected a HAL, fix the HAL import in `src/lib.rs`
+
+```diff
+ // my-app/src/lib.rs
+-// use some_hal as _; // memory layout
+use nrf52840_hal as _; // memory layout
+```
+
+### (6. Get a linker script)
+
+Some HAL crates require that you manually copy over a file called `memory.x` from the HAL to the root of your project. For nrf52840-hal, this is done automatically so no action is needed. For other HAL crates, see their documentation on where to find an example file.
+
+The `memory.x` file should look something like:
+
+```text
+MEMORY
+{
+  FLASH : ORIGIN = 0x00000000, LENGTH = 1024K
+  RAM   : ORIGIN = 0x20000000, LENGTH = 256K
+}
+```
+
+The `memory.x` file is included in the `cortex-m-rt` linker script `link.x`, and so `link.x` is the one you should tell `rustc` to use (see the `.cargo/config.toml` file where we do that).
+
+### 7. Run!
+
+You are now all set to `cargo-run` your first `defmt`-powered application!
+There are some examples in the `src/bin` directory.
+
+Start by `cargo run`-ning `my-app/src/bin/hello.rs`:
+
+```console
+$ # `rb` is an alias for `run --bin`
+$ cargo rb hello
+    Finished `dev` profile [optimized + debuginfo] target(s) in 0.01s
+     Running `probe-rs run --chip nrf52840_xxaa --log-format=oneline target/thumbv6m-none-eabi/debug/hello`
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.79 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+Hello, world!
+
+$ echo $?
+0
+```
+
+If you're running out of memory (`flip-link` bails with an overflow error), you can decrease the size of the device memory buffer by setting the `DEFMT_RTT_BUFFER_SIZE` environment variable. The default value is 1024 bytes, and powers of two should be used for optimal performance:
+
+```console
+$ DEFMT_RTT_BUFFER_SIZE=64 cargo rb hello
+```
+
+### (8. Set `rust-analyzer.linkedProjects`)
+
+If you are using [rust-analyzer] with VS Code for IDE-like features you can add following configuration to your `.vscode/settings.json` to make it work transparently across workspaces. Find the details of this option in the [RA docs].
+
+```json
+{
+    "rust-analyzer.linkedProjects": [
+        "Cargo.toml",
+        "firmware/Cargo.toml",
+    ]
+}
+```
+
+[RA docs]: https://rust-analyzer.github.io/manual.html#configuration
+[rust-analyzer]: https://rust-analyzer.github.io/
+
+## Running tests
+
+The template comes configured for running unit tests and integration tests on the target.
+
+Unit tests reside in the library crate and can test private API; the initial set of unit tests are in `src/lib.rs`.
+`cargo test --lib` will run those unit tests.
+
+```console
+$ cargo test --lib
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.15s
+     Running unittests src/lib.rs (target/thumbv6m-none-eabi/debug/deps/example-2b0d0e25d141bf57)
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.99 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.33 KiB/s (took 1s)                                                                                                                        Finished in 1.10s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Integration tests reside in the `tests` directory; the initial set of integration tests are in `tests/integration.rs`.
+`cargo test --test integration` will run those integration tests.
+Note that the argument of the `--test` flag must match the name of the test file in the `tests` directory.
+
+```console
+$ cargo test --test integration
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.10s
+     Running tests/integration.rs (target/thumbv6m-none-eabi/debug/deps/integration-aaaff41151f6a722)
+      Erasing ✔ 100% [####################]   8.00 KiB @  16.03 KiB/s (took 0s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Note that to add a new test file to the `tests` directory you also need to add a new `[[test]]` section to `Cargo.toml`.
+
+To run all the tests via `cargo test` the tests need to be explicitly disabled for all the existing binary targets.
+See `Cargo.toml` for details on how to do this.
+
+## Support
+
+`app-template` is part of the [Knurling] project, [Ferrous Systems]' effort at
+improving tooling used to develop for embedded systems.
+
+If you think that our work is useful, consider sponsoring it via [GitHub
+Sponsors].
+
+## License
+
+Licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+  http://www.apache.org/licenses/LICENSE-2.0)
+
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+### Contribution
+
+Unless you explicitly state otherwise, any contribution intentionally submitted
+for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
+licensed as above, without any additional terms or conditions.
+
+[Knurling]: https://knurling.ferrous-systems.com
+[Ferrous Systems]: https://ferrous-systems.com/
+[GitHub Sponsors]: https://github.com/sponsors/knurling-rs
--- a/time_meas/src/bin/main.rs
+++ b/time_meas/src/bin/main.rs
@@ -0,0 +1,84 @@
+// src/bin/main.rs
+#![no_std]
+#![no_main]
+
+use core::sync::atomic::{AtomicUsize, Ordering};
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::pac;
+use embassy_stm32::interrupt::InterruptExt;
+use embassy_stm32::timer::low_level::{CountingMode, Timer as LLTimer};
+use embassy_stm32::time::khz;
+use embassy_stm32::interrupt;
+use {defmt_rtt as _, panic_probe as _};
+
+// Pointer to the local `counter` so the ISR can read it with zero per-iteration overhead.
+static COUNTER_PTR: AtomicUsize = AtomicUsize::new(0);
+
+// NVIC handler for TIM2
+#[interrupt]
+fn TIM2() {
+    // Clear UIF, stop the timer
+    pac::TIM2.sr().modify(|r| r.set_uif(false));
+    pac::TIM2.cr1().modify(|r| r.set_cen(false));
+
+    // Snapshot the counter that the loop has been incrementing
+    let ptr = COUNTER_PTR.load(Ordering::Relaxed) as *const u32;
+    let count = unsafe { core::ptr::read_volatile(ptr) };
+
+    info!("10 seconds elapsed, counter = {}", count);
+
+    // Halt
+    loop {
+        cortex_m::asm::bkpt();
+    }
+}
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    info!("Start");
+    let p = embassy_stm32::init(Default::default());
+
+    // Configure TIM2
+    let mut tim2 = LLTimer::new(p.TIM2);
+    tim2.stop();
+    tim2.set_counting_mode(CountingMode::EdgeAlignedUp);
+
+    // Make the timer tick at 10 kHz. Driver derives PSC from RCC, so timing is exact.
+    tim2.set_tick_freq(khz(10));
+
+    // 10 seconds => 10_000 ticks/s * 10 s = 100_000 ticks. ARR is inclusive: set to 100_000 - 1.
+    tim2.set_max_compare_value(100_000 - 1);
+
+    // One-pulse mode (auto-stop after the first update event)
+    tim2.regs_core().cr1().modify(|r| r.set_opm(true));
+
+    // Ensure no pending UIF from the UG we generated during PSC/ARR programming.
+    // Important: do this BEFORE enabling UIE/NVIC to avoid an immediate ISR.
+    let _ = tim2.clear_update_interrupt();
+
+    // Enable update interrupt, reset counter to 0. Do not start yet.
+    tim2.enable_update_interrupt(true);
+    tim2.reset();
+
+    // Expose the address of the loop counter BEFORE enabling the NVIC so the ISR
+    // never runs before COUNTER_PTR is valid.
+    let mut counter: u32 = 0;
+    COUNTER_PTR.store(&counter as *const u32 as usize, Ordering::Relaxed);
+
+    // Unpend and enable NVIC for TIM2, then start the timer.
+    unsafe {
+        embassy_stm32::interrupt::TIM2.unpend();
+        embassy_stm32::interrupt::TIM2.enable();
+    }
+    tim2.start();
+
+    // Tight CPU loop for benchmarking
+    loop {
+        counter = counter.wrapping_add(1);
+
+        if counter % 10000 == 0 {
+            info!("CPU doing other work: {}", counter);
+        }
+    }
+}
--- a/time_meas/src/lib.rs
+++ b/time_meas/src/lib.rs
@@ -0,0 +1 @@
+#![no_std]
--- a/time_meas/tests/integration.rs
+++ b/time_meas/tests/integration.rs
@@ -0,0 +1,16 @@
+#![no_std]
+#![no_main]
+
+use stm32u5_blinky as _; // memory layout + panic handler
+
+// See https://crates.io/crates/defmt-test/0.3.0 for more documentation (e.g. about the 'state'
+// feature)
+#[defmt_test::tests]
+mod tests {
+    use defmt::assert;
+
+    #[test]
+    fn it_works() {
+        assert!(true)
+    }
+}
--- a/usart_async_buffered/.cargo/config.toml
+++ b/usart_async_buffered/.cargo/config.toml
@@ -0,0 +1,15 @@
+[build]
+target = "thumbv8m.main-none-eabihf"
+
+[target.thumbv8m.main-none-eabihf]
+runner = "probe-rs run --chip STM32U575ZITxQ"
+
+rustflags = [
+  "-C", "linker=rust-lld",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "link-arg=-Tdefmt.x",
+  "-C", "link-arg=--nmagic",
+]
+
+[package.metadata.cargo-flash]
+chip = "STM32U575ZIT"
--- a/usart_async_buffered/.gitignore
+++ b/usart_async_buffered/.gitignore
@@ -0,0 +1 @@
+/target
--- a/usart_async_buffered/Cargo.lock
+++ b/usart_async_buffered/Cargo.lock
--- a/usart_async_buffered/Cargo.toml
+++ b/usart_async_buffered/Cargo.toml
@@ -0,0 +1,30 @@
+[package]
+authors = ["Priec <filippriec@gmail.com>"]
+name = "hal_rng"
+edition = "2024"
+version = "0.1.0"
+
+
+[dependencies]
+cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.5"
+panic-halt = "1.0.0"
+
+embassy-executor = { version = "0.9.1", features = ["arch-cortex-m", "executor-thread"] }
+embassy-futures = "0.1.2"
+embassy-stm32 = { version = "0.4.0", features = ["unstable-pac", "stm32u575zi", "time-driver-any", "memory-x", "defmt"] }
+embassy-sync = "0.7.2"
+embassy-time = { version = "0.5.0", features = ["tick-hz-32_768"] }
+embassy-usb = "0.5.1"
+
+embedded-hal = "1.0.0"
+embedded-graphics = "0.8.1"
+heapless = { version = "0.9.1", default-features = false }
+micromath = "2.1.0"
+tinybmp = "0.6.0"
+panic-probe = { version = "1.0.0", features = ["defmt"] }
+defmt-rtt = "1.1.0"
+defmt = "1.0.1"
+static_cell = "2.1.1"
+embedded-io-async = "0.6.0"
+embedded-io = "0.6.1"
--- a/usart_async_buffered/LICENSE-APACHE
+++ b/usart_async_buffered/LICENSE-APACHE
@@ -0,0 +1,201 @@
+                              Apache License
+                        Version 2.0, January 2004
+                     http://www.apache.org/licenses/
+
+TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
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--- a/usart_async_buffered/LICENSE-MIT
+++ b/usart_async_buffered/LICENSE-MIT
@@ -0,0 +1,23 @@
+Permission is hereby granted, free of charge, to any
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+DEALINGS IN THE SOFTWARE.
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Priec	1a4c071417	time for big update from now on	2025-10-31 22:37:23 +01:00
Priec	8ce9ee9f6c	dma Rx working	2025-10-31 17:28:34 +01:00
Priec	28b468902a	Rx is not using dma now	2025-10-31 14:31:25 +01:00
Priec	0ecf821e40	moved properly	2025-10-31 13:19:54 +01:00
Priec	8de34e13d9	solution detached from main for async buffered generalized2	2025-10-31 13:00:21 +01:00
Priec	457d783d3b	FINAL FIX WORKING OH MY GOSH YES, We have to leak the timer to keep it toggled on after going out of scope to not call destructor	2025-10-31 11:46:21 +01:00
Priec	172dd899f9	debugging	2025-10-31 10:26:33 +01:00
Priec	f56fe0561b	timer is now separated	2025-10-31 00:05:19 +01:00
Priec	f2b6590473	the Tx is finished	2025-10-30 23:37:53 +01:00
Priec	e09231635f	working	2025-10-30 12:22:47 +01:00
Priec	8072ea15f0	DMA working	2025-10-29 23:23:20 +01:00
Priec	1c15d4d669	ready for dma implemenatation	2025-10-29 22:48:36 +01:00
Priec	c78af52849	dma transfering from buffer to the gpio	2025-10-29 21:37:08 +01:00
Filipriec	62303e7cf1	interrupt is wrong	2025-10-28 17:39:27 +01:00
Filipriec	5a7e5c6497	working but probably wrong. timer + bit turn on for semestralka1	2025-10-28 17:27:19 +01:00
Filipriec	90f8a1769f	starting sofware emulation of uart	2025-10-28 15:07:16 +01:00
Filipriec	847b6258a5	copy only	2025-10-28 15:02:53 +01:00
Priec	73c45bff85	timer working	2025-10-23 12:08:59 +02:00
Priec	7da55196e7	looking amazing, time for timer testing to improve performance to the maximum	2025-10-22 23:31:10 +02:00
Priec	9ac4f81975	still not there yet	2025-10-22 22:26:02 +02:00
Priec	706867818e	100% cpu workage showing safe results	2025-10-22 21:11:37 +02:00
Priec	7149bfab61	buffered generalized working	2025-10-22 08:12:34 +02:00
Priec	311de67247	uart getting better	2025-10-21 22:55:02 +02:00
Priec	26791906ac	working async buffered uart	2025-10-21 22:52:34 +02:00
Priec	f610a84ed0	working async uart properly well	2025-10-21 19:49:39 +02:00
Filipriec	98ee0b2617	working properly well	2025-10-21 19:26:58 +02:00
Filipriec	c000fd85f4	working blocking uart	2025-10-21 17:22:27 +02:00
Priec	a3344efcde	fixed properly	2025-10-21 11:28:07 +02:00
Priec	4f486eaead	printing in a loop	2025-10-21 09:08:53 +02:00
Priec	43af240f51	info! printing to the terminal	2025-10-21 09:07:44 +02:00
Priec	bf44bcc5d0	fixed	2025-10-21 08:18:36 +02:00
Priec	c6709f6aac	cleaned flake	2025-10-20 22:52:43 +02:00
Priec	deee05afb5	working hal_test	2025-10-20 22:37:21 +02:00
Priec	da01c4593e	fixed gitignores	2025-10-20 20:30:16 +02:00
Filipriec	621de5f37c	examples builded	2025-10-20 18:06:32 +02:00
Filipriec	bab60914b0	cleared rust repo for stm32	2025-10-20 17:45:49 +02:00
				`@@ -0,0 +1 @@`
				`https://www.st.com/content/ccc/resource/technical/document/reference_manual/group0/f3/60/ca/d2/98/c8/47/88/DM00477635/files/DM00477635.pdf/jcr:content/translations/en.DM00477635.pdf`
				`@@ -0,0 +1 @@`
				`https://www.ti.com/lit/ug/sprugp1/sprugp1.pdf?ts=1761641486453`