Priec
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fef7de2045
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working, but data are in pipe, but we read ringbuffer, critical bug, fix now
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2025-11-02 22:39:01 +01:00 |
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Priec
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15b3b96b68
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compiled and working
v0.1.1b
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2025-11-01 23:47:15 +01:00 |
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Priec
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4365c72688
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complete movement, some parts are destroyed and not moved yet
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2025-11-01 23:35:27 +01:00 |
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Priec
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63c353faac
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adjusted comments
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2025-11-01 14:08:27 +01:00 |
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Priec
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f24bd73c6b
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compiled from main branch working with LLI DMA
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2025-10-31 23:04:48 +01:00 |
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Priec
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1a4c071417
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time for big update from now on
v0.1.1
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2025-10-31 22:37:23 +01:00 |
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Priec
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8ce9ee9f6c
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dma Rx working
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2025-10-31 17:28:34 +01:00 |
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Priec
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28b468902a
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Rx is not using dma now
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2025-10-31 14:31:25 +01:00 |
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Priec
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0ecf821e40
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moved properly
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2025-10-31 13:19:54 +01:00 |
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Priec
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8de34e13d9
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solution detached from main for async buffered generalized2
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2025-10-31 13:00:21 +01:00 |
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Priec
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457d783d3b
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FINAL FIX WORKING OH MY GOSH YES, We have to leak the timer to keep it toggled on after going out of scope to not call destructor
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2025-10-31 11:46:21 +01:00 |
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Priec
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172dd899f9
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debugging
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2025-10-31 10:26:33 +01:00 |
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Priec
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f56fe0561b
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timer is now separated
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2025-10-31 00:05:19 +01:00 |
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Priec
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f2b6590473
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the Tx is finished
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2025-10-30 23:37:53 +01:00 |
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Priec
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e09231635f
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working
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2025-10-30 12:22:47 +01:00 |
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Priec
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8072ea15f0
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DMA working
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2025-10-29 23:23:20 +01:00 |
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Priec
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1c15d4d669
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ready for dma implemenatation
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2025-10-29 22:48:36 +01:00 |
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Priec
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c78af52849
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dma transfering from buffer to the gpio
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2025-10-29 21:37:08 +01:00 |
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Filipriec
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62303e7cf1
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interrupt is wrong
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2025-10-28 17:39:27 +01:00 |
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Filipriec
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5a7e5c6497
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working but probably wrong. timer + bit turn on for semestralka1
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2025-10-28 17:27:19 +01:00 |
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Filipriec
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90f8a1769f
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starting sofware emulation of uart
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2025-10-28 15:07:16 +01:00 |
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Filipriec
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847b6258a5
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copy only
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2025-10-28 15:02:53 +01:00 |
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Priec
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73c45bff85
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timer working
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2025-10-23 12:08:59 +02:00 |
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Priec
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7da55196e7
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looking amazing, time for timer testing to improve performance to the maximum
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2025-10-22 23:31:10 +02:00 |
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Priec
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9ac4f81975
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still not there yet
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2025-10-22 22:26:02 +02:00 |
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Priec
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706867818e
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100% cpu workage showing safe results
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2025-10-22 21:11:37 +02:00 |
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Priec
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7149bfab61
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buffered generalized working
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2025-10-22 08:12:34 +02:00 |
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Priec
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311de67247
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uart getting better
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2025-10-21 22:55:02 +02:00 |
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Priec
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26791906ac
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working async buffered uart
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2025-10-21 22:52:34 +02:00 |
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Priec
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f610a84ed0
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working async uart properly well
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2025-10-21 19:49:39 +02:00 |
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Filipriec
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98ee0b2617
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working properly well
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2025-10-21 19:26:58 +02:00 |
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Filipriec
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c000fd85f4
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working blocking uart
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2025-10-21 17:22:27 +02:00 |
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Priec
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a3344efcde
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fixed properly
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2025-10-21 11:28:07 +02:00 |
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Priec
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4f486eaead
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printing in a loop
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2025-10-21 09:08:53 +02:00 |
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Priec
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43af240f51
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info! printing to the terminal
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2025-10-21 09:07:44 +02:00 |
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Priec
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bf44bcc5d0
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fixed
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2025-10-21 08:18:36 +02:00 |
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Priec
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c6709f6aac
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cleaned flake
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2025-10-20 22:52:43 +02:00 |
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Priec
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deee05afb5
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working hal_test
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2025-10-20 22:37:21 +02:00 |
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Priec
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da01c4593e
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fixed gitignores
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2025-10-20 20:30:16 +02:00 |
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Filipriec
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621de5f37c
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examples builded
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2025-10-20 18:06:32 +02:00 |
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Filipriec
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bab60914b0
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cleared rust repo for stm32
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2025-10-20 17:45:49 +02:00 |
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Priec
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8fbe8e05eb
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embassy hal
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2025-10-19 23:26:33 +02:00 |
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Priec
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cc94aab412
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tim2 compiled
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2025-10-12 18:07:37 +02:00 |
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Priec
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325f47debc
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compiled with memory file
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2025-10-07 11:29:44 +02:00 |
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Priec
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52e8a9385e
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correct target
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2025-10-07 11:25:16 +02:00 |
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Priec
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0836af0f4f
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stm32 should now work
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2025-10-07 11:19:43 +02:00 |
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