Priec
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da2f011682
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1d needs to be builded again from scratch
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2025-11-19 12:51:45 +01:00 |
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Priec
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9c26a0ca81
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not working interrupt via tim7 to read data
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2025-11-19 11:57:28 +01:00 |
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Priec
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7a8a308620
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now im reading proper buffer
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2025-11-18 23:23:33 +01:00 |
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Priec
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516309aed2
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proper printing of the pipe_int tx_pipe
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2025-11-18 22:56:28 +01:00 |
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Filipriec
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45df1e87e4
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testing, not owrking 1d yet
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2025-11-18 19:39:51 +01:00 |
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Filipriec
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0a0ff0f38a
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debugging more
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2025-11-18 16:55:42 +01:00 |
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Filipriec
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1909497403
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hopefuly working CPU transfer to bsrr
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2025-11-18 13:36:07 +01:00 |
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Priec
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c0bc36bec2
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rx bez dma ready for testing
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2025-11-18 10:12:02 +01:00 |
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