Filipriec
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19536dde78
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compiled hw and sw uart in semestralka
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2025-11-11 21:39:46 +01:00 |
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Filipriec
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17c205f23b
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adding hardware uart
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2025-11-11 17:16:18 +01:00 |
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Filipriec
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c738fabac7
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software rx and tx are now using data, transmitting on the Tx and receiving on the Rx side
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2025-11-11 16:15:59 +01:00 |
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Filipriec
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bc68e30ead
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its a separate task now
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2025-11-11 16:03:46 +01:00 |
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Filipriec
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541173bfcb
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semestralka joinig all worlds together
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2025-11-11 15:51:37 +01:00 |
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Filipriec
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62303e7cf1
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interrupt is wrong
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2025-10-28 17:39:27 +01:00 |
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Filipriec
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5a7e5c6497
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working but probably wrong. timer + bit turn on for semestralka1
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2025-10-28 17:27:19 +01:00 |
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Filipriec
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90f8a1769f
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starting sofware emulation of uart
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2025-10-28 15:07:16 +01:00 |
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Filipriec
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847b6258a5
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copy only
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2025-10-28 15:02:53 +01:00 |
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