filipriec/stm32_rust
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its a separate task now

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Filipriec
2025-11-11 16:03:46 +01:00
parent 541173bfcb
commit bc68e30ead
3 changed files with 20 additions and 46 deletions
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38
semestralka_1/src/bin/main.rs
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@@ -7,15 +7,14 @@ use embassy_executor::Spawner;
use embassy_stm32::dma::Request;
use embassy_stm32::gpio::{Input, Output, Level, Pull, Speed};
use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
use embassy_stm32::dma::{TransferOptions, WritableRingBuffer};
use dma_gpio::software_uart::{
dma_timer::{init_tim6_for_uart, init_tim7_for_uart},
gpio_dma_uart_tx::encode_uart_frames,
gpio_dma_uart_rx::rx_dma_task,
debug::dump_tim6_regs,
};
use dma_gpio::config::{BAUD, TX_PIN_BIT, RX_OVERSAMPLE, TX_OVERSAMPLE};
use dma_gpio::config::{BAUD, RX_OVERSAMPLE, TX_OVERSAMPLE};
use dma_gpio::config::{TX_RING_BYTES, RX_RING_BYTES, PIPE_RX_SIZE};
use dma_gpio::software_uart::gpio_dma_uart_tx::tx_dma_task;
use static_cell::StaticCell;
use embassy_futures::yield_now;
use {defmt_rtt as _, panic_probe as _};
@@ -49,44 +48,13 @@ async fn main(spawner: Spawner) {
// Create and start the TX DMA ring in main.
// let bsrr_ptr = embassy_stm32::pac::GPIOA.bsrr().as_ptr() as *mut u32;
let odr_ptr = embassy_stm32::pac::GPIOA.odr().as_ptr() as *mut u32;
let mut tx_opts = TransferOptions::default();
tx_opts.half_transfer_ir = true;
tx_opts.complete_transfer_ir = true;
// SAFETY: tx_ring_mem is exclusive
let mut tx_ring = unsafe {
WritableRingBuffer::new(
p.GPDMA1_CH0,
TIM6_UP_REQ,
odr_ptr,
tx_ring_mem,
tx_opts,
)
};
// Start DMA
tx_ring.start();
info!("TX DMA ring started");
let mut frame_buf = [0u32; 4096];
spawner.spawn(tx_dma_task(p.GPDMA1_CH0, odr_ptr, tx_ring_mem).unwrap());
loop {
info!("tick start");
// Timer::after(Duration::from_millis(100)).await;
// info!("tick end");
let used = encode_uart_frames(
TX_PIN_BIT,
b"Hello marshmallow\r\n",
&mut frame_buf,
)
.await;
if used == 0 {
info!("encode_uart_frames() produced 0 words, skipping write");
yield_now().await;
continue;
}
let _ = tx_ring.write_exact(&frame_buf[..used]).await;
info!("text");
yield_now().await;
}
}

BIN
semestralka_1/src/software_uart/.gpio_dma_uart_tx.rs.swp
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28
semestralka_1/src/software_uart/gpio_dma_uart_tx.rs
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@@ -5,13 +5,10 @@ use embassy_stm32::{
peripherals::GPDMA1_CH0,
Peri,
};
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::pipe::Pipe;
use embassy_futures::yield_now;
use defmt::info;
use crate::config::{TX_OVERSAMPLE, TX_PIN_BIT, UART_CFG};
use crate::software_uart::dma_timer::init_tim6_for_uart;
use crate::config::{TX_PIN_BIT, UART_CFG};
use crate::software_uart::uart_emulation::encode_uart_byte_cfg;
pub const TIM6_UP_REQ: Request = 4;
@@ -44,15 +41,24 @@ pub async fn encode_uart_frames<'a>(
pub async fn tx_dma_task(
ch: Peri<'static, GPDMA1_CH0>,
odr_ptr: *mut u32,
tx_ring: &'static mut [u32],
tx_ring_mem: &'static mut [u32],
) {
let mut opts = TransferOptions::default();
opts.half_transfer_ir = true;
opts.complete_transfer_ir = true;
let mut tx_opts = TransferOptions::default();
tx_opts.half_transfer_ir = true;
tx_opts.complete_transfer_ir = true;
// SAFETY: tx_ring is exclusive to this task
let mut tx = unsafe { WritableRingBuffer::new(ch, TIM6_UP_REQ, odr_ptr, tx_ring, opts) };
tx.start();
let mut tx_ring = unsafe {
WritableRingBuffer::new(
ch,
TIM6_UP_REQ,
odr_ptr,
tx_ring_mem,
tx_opts,
)
};
tx_ring.start();
info!("TX DMA ring started");
let mut frame_buf = [0u32; 4096];
@@ -68,7 +74,7 @@ pub async fn tx_dma_task(
continue;
}
let _ = tx.write_exact(&frame_buf[..used]).await;
let _ = tx_ring.write_exact(&frame_buf[..used]).await;
yield_now().await;
}