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FPGA---VHDL
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v1.0.0
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filipriec skolsky PC
23eb5ae24c
its now working perfectly well with HH:MM and MM:SS to switch between them via button
2026-04-13 17:29:48 +02:00
project_1
working z predoslych hodin
2026-03-09 14:04:31 +01:00
project_2
working z predoslych hodin
2026-03-09 14:04:31 +01:00
project_3_nzio
working z predoslych hodin
2026-03-09 14:04:31 +01:00
project_4
nakreslene zadanie
2026-03-09 14:05:17 +01:00
project_5
hotovy priklad 5 funguje uplne bez problemov
2026-03-09 17:03:42 +01:00
project_6
workinghod 6 a hod7
2026-04-13 12:33:42 +02:00
project_7
its now working perfectly well with HH:MM and MM:SS to switch between them via button
2026-04-13 17:29:48 +02:00
project_7_hodiny
/project_6.srcs
clock
2026-03-23 14:04:42 +01:00
.gitignore
working z predoslych hodin
2026-03-09 14:04:31 +01:00
Description
To co sme robili v skole
2.8
MiB
Languages
VHDL
52.4%
Tcl
42.4%
Mermaid
5.2%
