75 lines
1.6 KiB
VHDL
75 lines
1.6 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 16.02.2026 15:27:16
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-- Design Name:
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-- Module Name: top_modul - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity top_modul is
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Port ( S : in STD_LOGIC;
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I0 : in STD_LOGIC;
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I1 : in STD_LOGIC;
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Y0 : out STD_LOGIC;
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Y1 : out STD_LOGIC;
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Y2 : out STD_LOGIC;
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Y3 : out STD_LOGIC);
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end top_modul;
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architecture Behavioral of top_modul is
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begin
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Y0 <= I0 when (S = '0') -- konkurentny prikaz multiplexor 1
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else I1;
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with S select -- konkurentny multiplexor 2
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Y1 <= I0 when '0',
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I1 when others;
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--Y2 <= I1 when S = '1' else I0; -- gpd konkurencny multiplexor 3
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mux_proc : process (S) -- sensitivity list
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begin
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case S is
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when '0' => Y2 <= I0;
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when others => Y2 <= I1;
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end case;
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end process;
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MUX3: process (S)
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begin
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if (S = '0') then
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Y3 <= I0;
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else
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Y3 <= I1;
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end if;
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end process;
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end Behavioral;
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