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-- Company: 
-- Engineer: 
-- 
-- Create Date: 16.02.2026 15:27:16
-- Design Name: 
-- Module Name: top_modul - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top_modul is
    Port ( S : in STD_LOGIC;
           I0 : in STD_LOGIC;
           I1 : in STD_LOGIC;
           Y0 : out STD_LOGIC;
           Y1 : out STD_LOGIC;
           Y2 : out STD_LOGIC;
           Y3 : out STD_LOGIC);
end top_modul;

architecture Behavioral of top_modul is

begin

Y0 <= I0 when  (S = '0') -- konkurentny prikaz multiplexor 1
        else I1;
        
with S select -- konkurentny multiplexor 2
        Y1 <= I0 when '0',
             I1 when others;
             
--Y2 <= I1 when S = '1' else I0; -- gpd konkurencny multiplexor 3
    
mux_proc : process (S)      -- sensitivity list
    begin
        case S is
            when '0' => Y2 <= I0;
            when others => Y2 <= I1;
        end case;
    end process;
    
MUX3: process (S)
begin
    if (S = '0') then
        Y3 <= I0;
    else
        Y3 <= I1;
    end if;
end process;

end Behavioral;