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a87a3896cc
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## This file is a general .xdc for the Basys3 rev B board
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## To use it in a project:
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## - uncomment the lines corresponding to used pins
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||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
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||||
## Clock signal
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||||
set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports CLK]
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create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
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||||
|
||||
|
||||
## Switches
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set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {RST}]
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set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {START}]
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||||
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {sw[2]}]
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#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports {sw[3]}]
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||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {sw[4]}]
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||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports {sw[5]}]
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||||
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports {sw[6]}]
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||||
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports {sw[7]}]
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||||
#set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports {sw[8]}]
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||||
#set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports {sw[9]}]
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||||
#set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports {sw[10]}]
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||||
#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {sw[11]}]
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||||
#set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports {sw[12]}]
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||||
#set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports {sw[13]}]
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||||
#set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {sw[14]}]
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||||
#set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {sw[15]}]
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||||
|
||||
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||||
## LEDs
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#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports {led[0]}]
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#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports {led[1]}]
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#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports {led[2]}]
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#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports {led[3]}]
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#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports {led[4]}]
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#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports {led[5]}]
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#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports {led[6]}]
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#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports {led[7]}]
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#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports {led[8]}]
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#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports {led[9]}]
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#set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports {led[10]}]
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#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports {led[11]}]
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#set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports {led[12]}]
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#set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports {led[13]}]
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#set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports {led[14]}]
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#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports {led[15]}]
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##7 Segment Display
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set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[0]}]
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set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[1]}]
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set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[2]}]
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set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[3]}]
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set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[4]}]
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set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[5]}]
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set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[6]}]
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set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[7]}]
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||||
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set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports {ANODS[0]}]
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set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports {ANODS[1]}]
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set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports {ANODS[2]}]
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set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports {ANODS[3]}]
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##Buttons
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#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports btnC]
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#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports btnU]
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#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports btnL]
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#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports btnR]
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#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports btnD]
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##Pmod Header JA
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#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports {JA[0]}];#Sch name = JA1
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#set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports {JA[1]}];#Sch name = JA2
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#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports {JA[2]}];#Sch name = JA3
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#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports {JA[3]}];#Sch name = JA4
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#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports {JA[4]}];#Sch name = JA7
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#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports {JA[5]}];#Sch name = JA8
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#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports {JA[6]}];#Sch name = JA9
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#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports {JA[7]}];#Sch name = JA10
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##Pmod Header JB
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#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports {JB[0]}];#Sch name = JB1
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#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports {JB[1]}];#Sch name = JB2
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#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports {JB[2]}];#Sch name = JB3
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||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports {JB[3]}];#Sch name = JB4
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||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports {JB[4]}];#Sch name = JB7
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||||
#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports {JB[5]}];#Sch name = JB8
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||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports {JB[6]}];#Sch name = JB9
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||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports {JB[7]}];#Sch name = JB10
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||||
|
||||
##Pmod Header JC
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||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports {JC[0]}];#Sch name = JC1
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||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports {JC[1]}];#Sch name = JC2
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||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports {JC[2]}];#Sch name = JC3
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||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports {JC[3]}];#Sch name = JC4
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||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports {JC[4]}];#Sch name = JC7
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||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports {JC[5]}];#Sch name = JC8
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||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports {JC[6]}];#Sch name = JC9
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||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports {JC[7]}];#Sch name = JC10
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||||
|
||||
##Pmod Header JXADC
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||||
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[0]}];#Sch name = XA1_P
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||||
#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[1]}];#Sch name = XA2_P
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||||
#set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[2]}];#Sch name = XA3_P
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||||
#set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[3]}];#Sch name = XA4_P
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||||
#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[4]}];#Sch name = XA1_N
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||||
#set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[5]}];#Sch name = XA2_N
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||||
#set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[6]}];#Sch name = XA3_N
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||||
#set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[7]}];#Sch name = XA4_N
|
||||
|
||||
|
||||
##VGA Connector
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[0]}]
|
||||
#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[1]}]
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[2]}]
|
||||
#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[3]}]
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[0]}]
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[1]}]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[2]}]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[3]}]
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[0]}]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[1]}]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[2]}]
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[3]}]
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports Hsync]
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports Vsync]
|
||||
|
||||
|
||||
##USB-RS232 Interface
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports RsRx]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports RsTx]
|
||||
|
||||
|
||||
##USB HID (PS/2)
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Clk]
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Data]
|
||||
|
||||
|
||||
##Quad SPI Flash
|
||||
##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
|
||||
##STARTUPE2 primitive.
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[0]}]
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[1]}]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[2]}]
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[3]}]
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports QspiCSn]
|
||||
|
||||
|
||||
## Configuration options, can be used for all designs
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
|
||||
## SPI configuration mode options for QSPI boot, can be used for all designs
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
72
project_5/project_5.srcs/sources_1/new/counter.vhd
Normal file
72
project_5/project_5.srcs/sources_1/new/counter.vhd
Normal file
@@ -0,0 +1,72 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 09.03.2026 15:14:35
|
||||
-- Design Name:
|
||||
-- Module Name: counter - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity counter is
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RST : in STD_LOGIC;
|
||||
CE : in STD_LOGIC;
|
||||
TC : out STD_LOGIC;
|
||||
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
|
||||
end counter;
|
||||
|
||||
architecture Behavioral of counter is
|
||||
-- Internal signal to keep track of the current number
|
||||
signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
||||
begin
|
||||
|
||||
-- Main counting logic
|
||||
process(CLK)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if RST = '1' then
|
||||
s_cnt <= "0000";
|
||||
elsif CE = '1' then
|
||||
if s_cnt = "1001" then -- If we are at 9
|
||||
s_cnt <= "0000"; -- Reset to 0
|
||||
else
|
||||
s_cnt <= s_cnt + 1; -- Increment
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Terminal Count logic (The red line connection)
|
||||
-- TC is '1' ONLY when we are at 9 AND the enable pulse is active.
|
||||
-- This ensures the next counter only moves once per rollover.
|
||||
TC <= '1' when (s_cnt = "1001" and CE = '1') else '0';
|
||||
|
||||
-- Drive the output ports
|
||||
COUNT_OUT <= s_cnt;
|
||||
|
||||
end Behavioral;
|
||||
55
project_5/project_5.srcs/sources_1/new/counter_2bit.vhd
Normal file
55
project_5/project_5.srcs/sources_1/new/counter_2bit.vhd
Normal file
@@ -0,0 +1,55 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 09.03.2026 15:32:13
|
||||
-- Design Name:
|
||||
-- Module Name: counter_2bit - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity counter_2bit is
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RST : in STD_LOGIC;
|
||||
COUNT_OUT : out STD_LOGIC_VECTOR (1 downto 0));
|
||||
end counter_2bit;
|
||||
|
||||
architecture Behavioral of counter_2bit is
|
||||
|
||||
signal s_cnt : STD_LOGIC_VECTOR(1 downto 0) := "00";
|
||||
begin
|
||||
process(CLK, RST)
|
||||
begin
|
||||
if RST = '1' then
|
||||
s_cnt <= "00";
|
||||
elsif rising_edge(CLK) then
|
||||
s_cnt <= s_cnt + 1;
|
||||
end if;
|
||||
end process;
|
||||
COUNT_OUT <= s_cnt;
|
||||
|
||||
end Behavioral;
|
||||
58
project_5/project_5.srcs/sources_1/new/dec2.vhd
Normal file
58
project_5/project_5.srcs/sources_1/new/dec2.vhd
Normal file
@@ -0,0 +1,58 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 09.03.2026 15:54:24
|
||||
-- Design Name:
|
||||
-- Module Name: dec_seg - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity dec_seg is
|
||||
Port ( BCD : in STD_LOGIC_VECTOR (3 downto 0);
|
||||
SEG : out STD_LOGIC_VECTOR (7 downto 0));
|
||||
end dec_seg;
|
||||
|
||||
architecture Behavioral of dec_seg is
|
||||
|
||||
begin
|
||||
-- Konverzia BCD na 7-segment (ABCDEFG + DP)
|
||||
-- Form<72>t: "ABCDEFG DP"
|
||||
|
||||
with bcd select
|
||||
seg <= "11000000" when "0000", -- 0
|
||||
"11111001" when "0001", -- 1
|
||||
"10100100" when "0010", -- 2
|
||||
"10110000" when "0011", -- 3
|
||||
"10011001" when "0100", -- 4
|
||||
"10010010" when "0101", -- 5
|
||||
"10000010" when "0110", -- 6
|
||||
"11111000" when "0111", -- 7
|
||||
"10000000" when "1000", -- 8
|
||||
"10010000" when "1001", -- 9
|
||||
"11111111" when others; -- off
|
||||
|
||||
end Behavioral;
|
||||
50
project_5/project_5.srcs/sources_1/new/decoder_bottom.vhd
Normal file
50
project_5/project_5.srcs/sources_1/new/decoder_bottom.vhd
Normal file
@@ -0,0 +1,50 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 09.03.2026 15:39:11
|
||||
-- Design Name:
|
||||
-- Module Name: decoder_bottom - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity decoder_an is
|
||||
Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0);
|
||||
ANODES : out STD_LOGIC_VECTOR (3 downto 0));
|
||||
end decoder_an;
|
||||
|
||||
architecture Behavioral of decoder_an is
|
||||
|
||||
begin
|
||||
with SEL select
|
||||
ANODES <= "1110" when "00",
|
||||
"1101" when "01",
|
||||
"1011" when "10",
|
||||
"0111" when "11",
|
||||
"1111" when others;
|
||||
|
||||
end Behavioral;
|
||||
60
project_5/project_5.srcs/sources_1/new/divider.vhd
Normal file
60
project_5/project_5.srcs/sources_1/new/divider.vhd
Normal file
@@ -0,0 +1,60 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 09.03.2026 14:43:21
|
||||
-- Design Name:
|
||||
-- Module Name: divider - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity divider is
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RST : in STD_LOGIC;
|
||||
CLK_1_Hz : out STD_LOGIC);
|
||||
end divider;
|
||||
|
||||
architecture Behavioral of divider is
|
||||
-- 27 bits is enough for 100 million
|
||||
signal s_cnt : STD_LOGIC_VECTOR(26 downto 0) := (others => '0');
|
||||
begin
|
||||
process(CLK)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if RST = '1' then
|
||||
s_cnt <= (others => '0');
|
||||
CLK_1_Hz <= '0';
|
||||
elsif s_cnt = 99_999_999 then
|
||||
s_cnt <= (others => '0');
|
||||
CLK_1_Hz <= '1'; -- The pulse
|
||||
else
|
||||
s_cnt <= s_cnt + 1;
|
||||
CLK_1_Hz <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end Behavioral;
|
||||
60
project_5/project_5.srcs/sources_1/new/divider_400Hz.vhd
Normal file
60
project_5/project_5.srcs/sources_1/new/divider_400Hz.vhd
Normal file
@@ -0,0 +1,60 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 09.03.2026 14:49:47
|
||||
-- Design Name:
|
||||
-- Module Name: divider_400Hz - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity divider_400Hz is
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RST : in STD_LOGIC;
|
||||
CLK_400_Hz : out STD_LOGIC);
|
||||
end divider_400Hz;
|
||||
|
||||
architecture Behavioral of divider_400Hz is
|
||||
-- 18 bits is enough for 250,000
|
||||
signal s_cnt : STD_LOGIC_VECTOR(17 downto 0) := (others => '0');
|
||||
begin
|
||||
process(CLK)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if RST = '1' then
|
||||
s_cnt <= (others => '0');
|
||||
CLK_400_Hz <= '0';
|
||||
elsif s_cnt = 249_999 then
|
||||
s_cnt <= (others => '0');
|
||||
CLK_400_Hz <= '1';
|
||||
else
|
||||
s_cnt <= s_cnt + 1;
|
||||
CLK_400_Hz <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end Behavioral;
|
||||
53
project_5/project_5.srcs/sources_1/new/mux.vhd
Normal file
53
project_5/project_5.srcs/sources_1/new/mux.vhd
Normal file
@@ -0,0 +1,53 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 09.03.2026 15:47:51
|
||||
-- Design Name:
|
||||
-- Module Name: mux - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity mux is
|
||||
Port ( I0 : in STD_LOGIC_VECTOR (3 downto 0);
|
||||
I1 : in STD_LOGIC_VECTOR (3 downto 0);
|
||||
I2 : in STD_LOGIC_VECTOR (3 downto 0);
|
||||
I3 : in STD_LOGIC_VECTOR (3 downto 0);
|
||||
S : in STD_LOGIC_VECTOR (1 downto 0);
|
||||
Y : out STD_LOGIC_VECTOR (3 downto 0));
|
||||
end mux;
|
||||
|
||||
architecture Behavioral of mux is
|
||||
|
||||
begin
|
||||
with S select
|
||||
Y <= I0 when "00",
|
||||
I1 when "01",
|
||||
I2 when "10",
|
||||
I3 when "11",
|
||||
"0000" when others;
|
||||
|
||||
end Behavioral;
|
||||
169
project_5/project_5.srcs/sources_1/new/top_modul.vhd
Normal file
169
project_5/project_5.srcs/sources_1/new/top_modul.vhd
Normal file
@@ -0,0 +1,169 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 09.03.2026 14:40:14
|
||||
-- Design Name:
|
||||
-- Module Name: top_modul - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity top_modul is
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RST : in STD_LOGIC;
|
||||
START : in STD_LOGIC;
|
||||
SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
ANODS : out STD_LOGIC_VECTOR (3 downto 0));
|
||||
end top_modul;
|
||||
|
||||
architecture Behavioral of top_modul is
|
||||
|
||||
component divider is
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RST : in STD_LOGIC;
|
||||
CLK_1_Hz : out STD_LOGIC); -- This will be our enable pulse
|
||||
end component;
|
||||
|
||||
component divider_400Hz is
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RST : in STD_LOGIC;
|
||||
CLK_400_Hz : out STD_LOGIC); -- This will be our enable pulse
|
||||
end component;
|
||||
|
||||
component counter is
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RST : in STD_LOGIC;
|
||||
CE : in STD_LOGIC;
|
||||
TC : out STD_LOGIC;
|
||||
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
|
||||
end component;
|
||||
|
||||
component counter_2bit is
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RST : in STD_LOGIC;
|
||||
COUNT_OUT : out STD_LOGIC_VECTOR (1 downto 0));
|
||||
end component;
|
||||
|
||||
component decoder_an is
|
||||
Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0);
|
||||
ANODES : out STD_LOGIC_VECTOR (3 downto 0));
|
||||
end component;
|
||||
|
||||
component mux is
|
||||
Port ( I0 : in STD_LOGIC_VECTOR (3 downto 0);
|
||||
I1 : in STD_LOGIC_VECTOR (3 downto 0);
|
||||
I2 : in STD_LOGIC_VECTOR (3 downto 0);
|
||||
I3 : in STD_LOGIC_VECTOR (3 downto 0);
|
||||
S : in STD_LOGIC_VECTOR (1 downto 0);
|
||||
Y : out STD_LOGIC_VECTOR (3 downto 0));
|
||||
end component;
|
||||
|
||||
component dec_seg is
|
||||
Port ( bcd : in STD_LOGIC_VECTOR (3 downto 0);
|
||||
seg : out STD_LOGIC_VECTOR (7 downto 0));
|
||||
end component;
|
||||
|
||||
signal clk_1_Hz : std_logic;
|
||||
signal clk_400_Hz : std_logic;
|
||||
|
||||
signal s_tc_units : std_logic; -- Wire connecting Top TC to Bottom CE
|
||||
signal s_cnt_units : std_logic_vector(3 downto 0); -- To MUX I0
|
||||
signal s_cnt_tens : std_logic_vector(3 downto 0); -- To MUX I1
|
||||
|
||||
signal s_cnt_2bit : std_logic_vector(1 downto 0);
|
||||
|
||||
signal s_mux_out : std_logic_vector(3 downto 0);
|
||||
|
||||
signal s_ce_units : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
U_DIV : divider
|
||||
port map (
|
||||
CLK => CLK,
|
||||
RST => RST,
|
||||
CLK_1_Hz => clk_1_Hz
|
||||
);
|
||||
|
||||
|
||||
U_DIV_400Hz : divider_400Hz
|
||||
port map (
|
||||
CLK => CLK,
|
||||
RST => RST,
|
||||
CLK_400_Hz => clk_400_Hz
|
||||
);
|
||||
|
||||
s_ce_units <= clk_1_Hz and START;
|
||||
-- TOP COUNTER (Units)
|
||||
U_CNT_TOP : counter
|
||||
port map (
|
||||
CLK => CLK,
|
||||
RST => RST,
|
||||
CE => s_ce_units,
|
||||
TC => s_tc_units,
|
||||
COUNT_OUT => s_cnt_units
|
||||
);
|
||||
|
||||
-- BOTTOM COUNTER (Tens)
|
||||
U_CNT_BOTTOM : counter
|
||||
port map (
|
||||
CLK => CLK,
|
||||
RST => RST,
|
||||
CE => s_tc_units, -- Increments only when top counter hits 9
|
||||
TC => open, -- Free TC
|
||||
COUNT_OUT => s_cnt_tens
|
||||
);
|
||||
|
||||
U_CNT_2BIT : counter_2bit
|
||||
port map (
|
||||
CLK => clk_400_Hz,
|
||||
RST => RST,
|
||||
COUNT_OUT => s_cnt_2bit
|
||||
);
|
||||
|
||||
U_DEC_ANODES : decoder_an
|
||||
port map (
|
||||
SEL => s_cnt_2bit, -- 2-bitov<6F> sign<67>l
|
||||
ANODES => ANODS -- V<>stupn<70> port top modulu
|
||||
);
|
||||
|
||||
U_MUX : mux
|
||||
port map (
|
||||
I0 => s_cnt_units, -- V<>stup z prv<72>ho <20><>ta<74>a
|
||||
I1 => s_cnt_tens, -- V<>stup z druh<75>ho <20><>ta<74>a
|
||||
I2 => "0000", -- Zatia<69> nevyu<79>it<69> (nula)
|
||||
I3 => "0000", -- Zatia<69> nevyu<79>it<69> (nula)
|
||||
S => s_cnt_2bit, -- Sign<67>l zo zelen<65>ho <20><>ta<74>a (v<>ber an<61>dy)
|
||||
Y => s_mux_out -- Vybran<61> <20><>slica pre segmenty
|
||||
);
|
||||
|
||||
U_DEC_SEG : dec_seg
|
||||
port map (
|
||||
BCD => s_mux_out, -- <20><>slica vybran<61> multiplexerom
|
||||
SEG => SEGMENTS -- V<>stupn<70> port top modulu (8 bitov)
|
||||
);
|
||||
|
||||
end Behavioral;
|
||||
284
project_5/project_5.xpr
Normal file
284
project_5/project_5.xpr
Normal file
@@ -0,0 +1,284 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2022.2 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="61" Path="C:/Users/student/Documents/priecinok/project_5/project_5.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="e38d1a4c4a2f4256841e587df17ee164"/>
|
||||
<Option Name="Part" Val="xc7a35tcpg236-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2022.2"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2022.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2022.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="21.09.009"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="S-2021.09"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2022.04"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="13.0"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="TargetLanguage" Val="VHDL"/>
|
||||
<Option Name="SimulatorLanguage" Val="VHDL"/>
|
||||
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
|
||||
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../AppData/Roaming/Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSABoardId" Val="basys3"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/counter.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/counter_2bit.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/dec2.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/decoder_bottom.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/divider.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/divider_400Hz.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/mux.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/top_modul.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="top_modul"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PSRCDIR/constrs_1/new/projekt_5.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/constrs_1/imports/Downloads/Basys-3-Master.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../../../Downloads/Basys-3-Master.xdc"/>
|
||||
<Attr Name="ImportTime" Val="1771253458"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="top_modul"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<File Path="$PSRCDIR/utils_1/imports/synth_1/top_modul.dcp">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedInSteps" Val="synth_1"/>
|
||||
<Attr Name="AutoDcp" Val="1"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="19">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top_modul.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board>
|
||||
<Jumpers/>
|
||||
</Board>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
BIN
project_5/zadanie.jpg
Normal file
BIN
project_5/zadanie.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 1.2 MiB |
Reference in New Issue
Block a user