61 lines
1.5 KiB
VHDL
61 lines
1.5 KiB
VHDL
----------------------------------------------------------------------------------
|
|
-- Company:
|
|
-- Engineer:
|
|
--
|
|
-- Create Date: 09.03.2026 14:49:47
|
|
-- Design Name:
|
|
-- Module Name: divider_400Hz - Behavioral
|
|
-- Project Name:
|
|
-- Target Devices:
|
|
-- Tool Versions:
|
|
-- Description:
|
|
--
|
|
-- Dependencies:
|
|
--
|
|
-- Revision:
|
|
-- Revision 0.01 - File Created
|
|
-- Additional Comments:
|
|
--
|
|
----------------------------------------------------------------------------------
|
|
|
|
|
|
library IEEE;
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
|
|
|
-- Uncomment the following library declaration if using
|
|
-- arithmetic functions with Signed or Unsigned values
|
|
--use IEEE.NUMERIC_STD.ALL;
|
|
|
|
-- Uncomment the following library declaration if instantiating
|
|
-- any Xilinx leaf cells in this code.
|
|
--library UNISIM;
|
|
--use UNISIM.VComponents.all;
|
|
|
|
entity divider_400Hz is
|
|
Port ( CLK : in STD_LOGIC;
|
|
RST : in STD_LOGIC;
|
|
CLK_400_Hz : out STD_LOGIC);
|
|
end divider_400Hz;
|
|
|
|
architecture Behavioral of divider_400Hz is
|
|
-- 18 bits is enough for 250,000
|
|
signal s_cnt : STD_LOGIC_VECTOR(17 downto 0) := (others => '0');
|
|
begin
|
|
process(CLK)
|
|
begin
|
|
if rising_edge(CLK) then
|
|
if RST = '1' then
|
|
s_cnt <= (others => '0');
|
|
CLK_400_Hz <= '0';
|
|
elsif s_cnt = 249_999 then
|
|
s_cnt <= (others => '0');
|
|
CLK_400_Hz <= '1';
|
|
else
|
|
s_cnt <= s_cnt + 1;
|
|
CLK_400_Hz <= '0';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
end Behavioral;
|