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23eb5ae24c ... sk_pc

Author SHA1 Message Date
filipriec skolsky PC
3e2b49671e working buttons and DIN to control display 2026-03-23 17:22:08 +01:00
filipriec skolsky PC
07f021abe6 workinghod 6 a hod7 2026-03-23 16:43:42 +01:00
30 changed files with 176 additions and 2066 deletions
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flowchart TD
%% ── External ports ──────────────────────────────────────────
CLK([CLK])
RST([RST])
START([START])
SEGMENTS([SEGMENTS\nout])
ANODS([ANODS\nout])
%% ════════════════════════════════════════════════════════════
%% FILE: divider.vhd
%% ════════════════════════════════════════════════════════════
subgraph FILE_DIV["📄 divider.vhd — entity: divider"]
direction TB
DIV["U_DIV\ndivider\n─────────────\nIN: CLK, RST\nOUT: CLK_1_Hz"]
end
%% ════════════════════════════════════════════════════════════
%% FILE: divider_400Hz.vhd
%% ════════════════════════════════════════════════════════════
subgraph FILE_DIV400["📄 divider_400Hz.vhd — entity: divider_400Hz"]
direction TB
DIV400["U_DIV_400Hz\ndivider_400Hz\n─────────────\nIN: CLK, RST\nOUT: CLK_400_Hz"]
end
%% ════════════════════════════════════════════════════════════
%% FILE: counter.vhd
%% ════════════════════════════════════════════════════════════
subgraph FILE_CNT["📄 counter.vhd — entity: counter (reused 4x)"]
direction TB
CNT_U["U_CNT_TOP\ncounter - Units\n─────────────\nIN: CLK, RST, CE\nOUT: COUNT_OUT, TC"]
CNT_T["U_CNT_BOTTOM\ncounter - Tens\n─────────────\nIN: CLK, RST, CE\nOUT: COUNT_OUT, TC"]
CNT_H["U_CNT_3\ncounter - Hundreds\n─────────────\nIN: CLK, RST, CE\nOUT: COUNT_OUT, TC"]
CNT_K["U_CNT_4\ncounter - Thousands\n─────────────\nIN: CLK, RST, CE\nOUT: COUNT_OUT, TC=open"]
end
%% ════════════════════════════════════════════════════════════
%% FILE: counter_2bit.vhd
%% ════════════════════════════════════════════════════════════
subgraph FILE_CNT2["📄 counter_2bit.vhd — entity: counter_2bit"]
direction TB
CNT2["U_CNT_2BIT\ncounter_2bit\n─────────────\nIN: CLK=clk_400Hz, RST\nOUT: COUNT_OUT 2-bit"]
end
%% ════════════════════════════════════════════════════════════
%% FILE: decoder_bottom.vhd
%% ════════════════════════════════════════════════════════════
subgraph FILE_DEC_AN["📄 decoder_bottom.vhd — entity: decoder_an"]
direction TB
DEC_AN["U_DEC_ANODES\ndecoder_an\n─────────────\nIN: SEL 2-bit\nOUT: ANODES 4-bit"]
end
%% ════════════════════════════════════════════════════════════
%% FILE: mux.vhd
%% ════════════════════════════════════════════════════════════
subgraph FILE_MUX["📄 mux.vhd — entity: mux"]
direction TB
MUX["U_MUX\nmux 4x4-bit\n─────────────\nIN: I0,I1,I2,I3, S 2-bit\nOUT: Y 4-bit"]
end
%% ════════════════════════════════════════════════════════════
%% FILE: dec2.vhd
%% ════════════════════════════════════════════════════════════
subgraph FILE_DEC_SEG["📄 dec2.vhd — entity: dec_seg"]
direction TB
DEC_SEG["U_DEC_SEG\ndec_seg\n─────────────\nIN: BCD 4-bit\nOUT: SEG 8-bit"]
end
%% ════════════════════════════════════════════════════════════
%% top_modul.vhd — glue logic defined directly in this file
%% ════════════════════════════════════════════════════════════
subgraph FILE_TOP["📄 top_modul.vhd — glue signals defined here"]
direction TB
AND_START{"s_ce_units\nclk_1_Hz AND START"}
AND2{"CE for Hundreds\ns_tc_units AND s_tc_tens"}
AND3{"CE for Thousands\ns_tc_units AND s_tc_tens\nAND s_tc_hundreds"}
end
%% ── Clock / Reset wiring ─────────────────────────────────────
CLK --> DIV
RST --> DIV
CLK --> DIV400
RST --> DIV400
CLK --> CNT_U & CNT_T & CNT_H & CNT_K
RST --> CNT_U & CNT_T & CNT_H & CNT_K & CNT2
%% ── 1 Hz chain ───────────────────────────────────────────────
DIV -->|"clk_1_Hz"| AND_START
START --> AND_START
AND_START -->|"s_ce_units (CE)"| CNT_U
%% ── BCD carry chain ──────────────────────────────────────────
CNT_U -->|"s_tc_units (TC->CE)"| CNT_T
CNT_U -->|"s_tc_units"| AND2
CNT_T -->|"s_tc_tens"| AND2
AND2 -->|"CE"| CNT_H
CNT_U -->|"s_tc_units"| AND3
CNT_T -->|"s_tc_tens"| AND3
CNT_H -->|"s_tc_hundreds"| AND3
AND3 -->|"CE"| CNT_K
%% ── 400 Hz display scan ──────────────────────────────────────
DIV400 -->|"clk_400_Hz"| CNT2
CNT2 -->|"s_cnt_2bit (SEL)"| DEC_AN
CNT2 -->|"s_cnt_2bit (S)"| MUX
DEC_AN -->|"ANODES"| ANODS
%% ── MUX inputs from counters ─────────────────────────────────
CNT_U -->|"s_cnt_units (I0)"| MUX
CNT_T -->|"s_cnt_tens (I1)"| MUX
CNT_H -->|"s_cnt_hundreds (I2)"| MUX
CNT_K -->|"s_cnt_thousands (I3)"| MUX
%% ── Segment decode ───────────────────────────────────────────
MUX -->|"s_mux_out (BCD)"| DEC_SEG
DEC_SEG -->|"SEG"| SEGMENTS

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flowchart LR
%% ── Inputs ───────────────────────────────────────────────────
CLK([CLK])
RST([RST])
START([START])
%% ── Outputs ──────────────────────────────────────────────────
SEGMENTS([SEGMENTS])
ANODS([ANODS])
%% ── Clock dividers ───────────────────────────────────────────
subgraph FILE_DIV["📄 divider.vhd"]
DIV["divider\n──────────\n100MHz → 1Hz pulse"]
end
subgraph FILE_DIV400["📄 divider_400Hz.vhd"]
DIV400["divider_400Hz\n──────────\n100MHz → 400Hz pulse"]
end
%% ── Glue in top_modul ────────────────────────────────────────
AND_CE(["⚡ top_modul.vhd\ns_ce_units =\nclk_1_Hz AND START"])
%% ── BCD counter chain ────────────────────────────────────────
subgraph FILE_CNT["📄 counter.vhd (entity reused 4×)"]
direction LR
CNT_U["U_CNT_TOP\n── Units ──\nCE=s_ce_units\nTC→s_tc_units"]
CNT_T["U_CNT_BOTTOM\n── Tens ──\nCE=s_tc_units\nTC→s_tc_tens"]
CNT_H["U_CNT_3\n── Hundreds ──\nCE=tc_u AND tc_t\nTC→s_tc_hundreds"]
CNT_K["U_CNT_4\n── Thousands ──\nCE=tc_u AND tc_t\n AND tc_h\nTC=open"]
CNT_U -->|"s_tc_units"| CNT_T
CNT_T -->|"s_tc_tens"| CNT_H
CNT_H -->|"s_tc_hundreds"| CNT_K
end
%% ── Display scan chain ───────────────────────────────────────
subgraph FILE_CNT2["📄 counter_2bit.vhd"]
CNT2["counter_2bit\n──────────\nIN: clk_400Hz\nOUT: s_cnt_2bit"]
end
subgraph FILE_DEC_AN["📄 decoder_bottom.vhd"]
DEC_AN["decoder_an\n──────────\nIN: SEL 2-bit\nOUT: ANODES 4-bit"]
end
%% ── Mux + segment decode ─────────────────────────────────────
subgraph FILE_MUX["📄 mux.vhd"]
MUX["mux 4×4-bit\n──────────\nI0–I3: digit values\nS: s_cnt_2bit\nY: s_mux_out"]
end
subgraph FILE_DEC_SEG["📄 dec2.vhd"]
DEC_SEG["dec_seg\n──────────\nBCD 4-bit\n→ SEG 8-bit"]
end
%% ═══════════════════════════════════════════════════════
%% WIRING
%% ═══════════════════════════════════════════════════════
%% Clock sources
CLK -->|"100 MHz"| DIV
CLK -->|"100 MHz"| DIV400
%% 1 Hz counting path
DIV -->|"clk_1_Hz"| AND_CE
START --> AND_CE
AND_CE -->|"s_ce_units"| CNT_U
%% 400 Hz display scan path
DIV400 -->|"clk_400_Hz"| CNT2
CNT2 -->|"s_cnt_2bit"| DEC_AN
CNT2 -->|"s_cnt_2bit (S)"| MUX
DEC_AN -->|"ANODES"| ANODS
%% Counter digits into mux
CNT_U -->|"s_cnt_units (I0)"| MUX
CNT_T -->|"s_cnt_tens (I1)"| MUX
CNT_H -->|"s_cnt_hundreds (I2)"| MUX
CNT_K -->|"s_cnt_thousands (I3)"| MUX
%% Segment output
MUX -->|"s_mux_out"| DEC_SEG
DEC_SEG -->|"SEG"| SEGMENTS

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## This file is a general .xdc for the Basys3 rev B board
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
## Clock signal
set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports CLK]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
## Switches
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {RST}]
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {START}]
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {sw[2]}]
#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports {sw[3]}]
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {sw[4]}]
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports {sw[5]}]
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports {sw[6]}]
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports {sw[7]}]
#set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports {sw[8]}]
#set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports {sw[9]}]
#set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports {sw[10]}]
#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {sw[11]}]
#set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports {sw[12]}]
#set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports {sw[13]}]
#set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {sw[14]}]
#set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {sw[15]}]
## LEDs
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports {led[0]}]
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports {led[1]}]
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports {led[2]}]
#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports {led[3]}]
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports {led[4]}]
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports {led[5]}]
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports {led[6]}]
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports {led[7]}]
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports {led[8]}]
#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports {led[9]}]
#set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports {led[10]}]
#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports {led[11]}]
#set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports {led[12]}]
#set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports {led[13]}]
#set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports {led[14]}]
#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports {led[15]}]
##7 Segment Display
set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[0]}]
set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[1]}]
set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[2]}]
set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[3]}]
set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[4]}]
set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[5]}]
set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[6]}]
set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[7]}]
set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports {ANODS[0]}]
set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports {ANODS[1]}]
set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports {ANODS[2]}]
set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports {ANODS[3]}]
##Buttons
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports btnC]
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports btnU]
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports btnL]
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports btnR]
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports btnD]
##Pmod Header JA
#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports {JA[0]}];#Sch name = JA1
#set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports {JA[1]}];#Sch name = JA2
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports {JA[2]}];#Sch name = JA3
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports {JA[3]}];#Sch name = JA4
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports {JA[4]}];#Sch name = JA7
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports {JA[5]}];#Sch name = JA8
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports {JA[6]}];#Sch name = JA9
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports {JA[7]}];#Sch name = JA10
##Pmod Header JB
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports {JB[0]}];#Sch name = JB1
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports {JB[1]}];#Sch name = JB2
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports {JB[2]}];#Sch name = JB3
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports {JB[3]}];#Sch name = JB4
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports {JB[4]}];#Sch name = JB7
#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports {JB[5]}];#Sch name = JB8
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports {JB[6]}];#Sch name = JB9
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports {JB[7]}];#Sch name = JB10
##Pmod Header JC
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports {JC[0]}];#Sch name = JC1
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports {JC[1]}];#Sch name = JC2
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports {JC[2]}];#Sch name = JC3
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports {JC[3]}];#Sch name = JC4
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports {JC[4]}];#Sch name = JC7
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports {JC[5]}];#Sch name = JC8
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports {JC[6]}];#Sch name = JC9
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports {JC[7]}];#Sch name = JC10
##Pmod Header JXADC
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[0]}];#Sch name = XA1_P
#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[1]}];#Sch name = XA2_P
#set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[2]}];#Sch name = XA3_P
#set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[3]}];#Sch name = XA4_P
#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[4]}];#Sch name = XA1_N
#set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[5]}];#Sch name = XA2_N
#set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[6]}];#Sch name = XA3_N
#set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[7]}];#Sch name = XA4_N
##VGA Connector
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[0]}]
#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[1]}]
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[2]}]
#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[3]}]
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[0]}]
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[1]}]
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[2]}]
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[3]}]
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[0]}]
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[1]}]
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[2]}]
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[3]}]
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports Hsync]
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports Vsync]
##USB-RS232 Interface
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports RsRx]
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports RsTx]
##USB HID (PS/2)
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Clk]
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Data]
##Quad SPI Flash
##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
##STARTUPE2 primitive.
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[0]}]
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[1]}]
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[2]}]
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[3]}]
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports QspiCSn]
## Configuration options, can be used for all designs
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
## SPI configuration mode options for QSPI boot, can be used for all designs
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]

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project_6/project_6.srcs/sources_1/new/counter.vhd
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 15:14:35
-- Design Name:
-- Module Name: counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CE : in STD_LOGIC;
TC : out STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture Behavioral of counter is
-- Internal signal to keep track of the current number
signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin
-- Main counting logic
process(CLK)
begin
if rising_edge(CLK) then
if RST = '1' then
s_cnt <= "0000";
elsif CE = '1' then
if s_cnt = "1001" then -- If we are at 9
s_cnt <= "0000"; -- Reset to 0
else
s_cnt <= s_cnt + 1; -- Increment
end if;
end if;
end if;
end process;
-- Terminal Count logic (The red line connection)
-- TC is '1' ONLY when we are at 9 AND the enable pulse is active.
-- This ensures the next counter only moves once per rollover.
-- TC <= '1' when (s_cnt = "1001" and CE = '1') else '0'; / TODO
-- Drive the output ports
COUNT_OUT <= s_cnt;
end Behavioral;

55
project_6/project_6.srcs/sources_1/new/counter_2bit.vhd
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@@ -1,55 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 15:32:13
-- Design Name:
-- Module Name: counter_2bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter_2bit is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (1 downto 0));
end counter_2bit;
architecture Behavioral of counter_2bit is
signal s_cnt : STD_LOGIC_VECTOR(1 downto 0) := "00";
begin
process(CLK, RST)
begin
if RST = '1' then
s_cnt <= "00";
elsif rising_edge(CLK) then
s_cnt <= s_cnt + 1;
end if;
end process;
COUNT_OUT <= s_cnt;
end Behavioral;

58
project_6/project_6.srcs/sources_1/new/dec2.vhd
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@@ -1,58 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 15:54:24
-- Design Name:
-- Module Name: dec_seg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dec_seg is
Port ( BCD : in STD_LOGIC_VECTOR (3 downto 0);
SEG : out STD_LOGIC_VECTOR (7 downto 0));
end dec_seg;
architecture Behavioral of dec_seg is
begin
-- Konverzia BCD na 7-segment (ABCDEFG + DP)
-- Form<72>t: "ABCDEFG DP"
with bcd select
seg <= "11000000" when "0000", -- 0
"11111001" when "0001", -- 1
"10100100" when "0010", -- 2
"10110000" when "0011", -- 3
"10011001" when "0100", -- 4
"10010010" when "0101", -- 5
"10000010" when "0110", -- 6
"11111000" when "0111", -- 7
"10000000" when "1000", -- 8
"10010000" when "1001", -- 9
"11111111" when others; -- off
end Behavioral;

50
project_6/project_6.srcs/sources_1/new/decoder_bottom.vhd
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@@ -1,50 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 15:39:11
-- Design Name:
-- Module Name: decoder_bottom - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity decoder_an is
Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0);
ANODES : out STD_LOGIC_VECTOR (3 downto 0));
end decoder_an;
architecture Behavioral of decoder_an is
begin
with SEL select
ANODES <= "1110" when "00",
"1101" when "01",
"1011" when "10",
"0111" when "11",
"1111" when others;
end Behavioral;

60
project_6/project_6.srcs/sources_1/new/divider.vhd
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@@ -1,60 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 14:43:21
-- Design Name:
-- Module Name: divider - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity divider is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CLK_1_Hz : out STD_LOGIC);
end divider;
architecture Behavioral of divider is
-- 27 bits is enough for 100 million
signal s_cnt : STD_LOGIC_VECTOR(26 downto 0) := (others => '0');
begin
process(CLK)
begin
if rising_edge(CLK) then
if RST = '1' then
s_cnt <= (others => '0');
CLK_1_Hz <= '0';
elsif s_cnt = 99_999_999 then
s_cnt <= (others => '0');
CLK_1_Hz <= '1'; -- The pulse
else
s_cnt <= s_cnt + 1;
CLK_1_Hz <= '0';
end if;
end if;
end process;
end Behavioral;

60
project_6/project_6.srcs/sources_1/new/divider_400Hz.vhd
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@@ -1,60 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 14:49:47
-- Design Name:
-- Module Name: divider_400Hz - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity divider_400Hz is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CLK_400_Hz : out STD_LOGIC);
end divider_400Hz;
architecture Behavioral of divider_400Hz is
-- 18 bits is enough for 250,000
signal s_cnt : STD_LOGIC_VECTOR(17 downto 0) := (others => '0');
begin
process(CLK)
begin
if rising_edge(CLK) then
if RST = '1' then
s_cnt <= (others => '0');
CLK_400_Hz <= '0';
elsif s_cnt = 249_999 then
s_cnt <= (others => '0');
CLK_400_Hz <= '1';
else
s_cnt <= s_cnt + 1;
CLK_400_Hz <= '0';
end if;
end if;
end process;
end Behavioral;

53
project_6/project_6.srcs/sources_1/new/mux.vhd
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@@ -1,53 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 15:47:51
-- Design Name:
-- Module Name: mux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux is
Port ( I0 : in STD_LOGIC_VECTOR (3 downto 0);
I1 : in STD_LOGIC_VECTOR (3 downto 0);
I2 : in STD_LOGIC_VECTOR (3 downto 0);
I3 : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end mux;
architecture Behavioral of mux is
begin
with S select
Y <= I0 when "00",
I1 when "01",
I2 when "10",
I3 when "11",
"0000" when others;
end Behavioral;

190
project_6/project_6.srcs/sources_1/new/top_modul.vhd
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@@ -1,190 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 14:40:14
-- Design Name:
-- Module Name: top_modul - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_modul is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
START : in STD_LOGIC;
SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
ANODS : out STD_LOGIC_VECTOR (3 downto 0));
end top_modul;
architecture Behavioral of top_modul is
component divider is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CLK_1_Hz : out STD_LOGIC); -- This will be our enable pulse
end component;
component divider_400Hz is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CLK_400_Hz : out STD_LOGIC); -- This will be our enable pulse
end component;
component counter is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CE : in STD_LOGIC;
TC : out STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component counter_2bit is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (1 downto 0));
end component;
component decoder_an is
Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0);
ANODES : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component mux is
Port ( I0 : in STD_LOGIC_VECTOR (3 downto 0);
I1 : in STD_LOGIC_VECTOR (3 downto 0);
I2 : in STD_LOGIC_VECTOR (3 downto 0);
I3 : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component dec_seg is
Port ( bcd : in STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal clk_1_Hz : std_logic;
signal clk_400_Hz : std_logic;
signal s_ce_units : std_logic;
signal s_tc_units : std_logic; -- Wire connecting Top TC to Bottom CE
signal s_tc_tens : std_logic;
signal s_tc_hundreds : std_logic;
signal s_cnt_units : std_logic_vector(3 downto 0); -- To MUX I0
signal s_cnt_tens : std_logic_vector(3 downto 0); -- To MUX I1
signal s_cnt_hundreds : std_logic_vector(3 downto 0);
signal s_cnt_thousands: std_logic_vector(3 downto 0);
signal s_cnt_2bit : std_logic_vector(1 downto 0);
signal s_mux_out : std_logic_vector(3 downto 0);
begin
U_DIV : divider
port map (
CLK => CLK,
RST => RST,
CLK_1_Hz => clk_1_Hz
);
U_DIV_400Hz : divider_400Hz
port map (
CLK => CLK,
RST => RST,
CLK_400_Hz => clk_400_Hz
);
s_ce_units <= clk_1_Hz and START;
-- TOP COUNTER (Units)
U_CNT_TOP : counter
port map (
CLK => CLK,
RST => RST,
CE => s_ce_units,
TC => s_tc_units,
COUNT_OUT => s_cnt_units
);
-- BOTTOM COUNTER (Tens)
U_CNT_BOTTOM : counter
port map (
CLK => CLK,
RST => RST,
CE => s_tc_units, -- Increments only when top counter hits 9
TC => s_tc_tens,
COUNT_OUT => s_cnt_tens
);
-- 3 COUNTER (Stovky)
U_CNT_3 : counter
port map (
CLK => CLK,
RST => RST,
CE => s_tc_tens and s_tc_units,
TC => s_tc_hundreds,
COUNT_OUT => s_cnt_hundreds
);
-- 4 COUNTER (Tisicky)
U_CNT_4 : counter
port map (
CLK => CLK,
RST => RST,
CE => s_tc_tens and s_tc_units and s_tc_hundreds,
TC => open, -- Free TC
COUNT_OUT => s_cnt_thousands
);
U_CNT_2BIT : counter_2bit
port map (
CLK => clk_400_Hz,
RST => RST,
COUNT_OUT => s_cnt_2bit
);
U_DEC_ANODES : decoder_an
port map (
SEL => s_cnt_2bit, -- 2-bitov<6F> sign<67>l
ANODES => ANODS -- V<>stupn<70> port top modulu
);
U_MUX : mux
port map (
I0 => s_cnt_units, -- V<>stup z prv<72>ho <20><>ta<74>a
I1 => s_cnt_tens, -- V<>stup z druh<75>ho <20><>ta<74>a
I2 => s_cnt_hundreds,
I3 => s_cnt_thousands,
S => s_cnt_2bit, -- Sign<67>l zo zelen<65>ho <20><>ta<74>a (v<>ber an<61>dy)
Y => s_mux_out -- Vybran<61> <20><>slica pre segmenty
);
U_DEC_SEG : dec_seg
port map (
BCD => s_mux_out, -- <20><>slica vybran<61> multiplexerom
SEG => SEGMENTS -- V<>stupn<70> port top modulu (8 bitov)
);
end Behavioral;

2
project_7/project_5.srcs/constrs_1/imports/Downloads/Basys-3-Master.xdc
View File

@@ -12,7 +12,7 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {RST}] set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {RST}]
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {START}] set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {START}]
set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {SW_MODE}] #set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {sw[2]}]
#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports {sw[3]}] #set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports {sw[3]}]
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {sw[4]}] #set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {sw[4]}]
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports {sw[5]}] #set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports {sw[5]}]

178
project_7/project_5.srcs/sources_1/new/clock_logic.vhd
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@@ -1,178 +0,0 @@
-- clock_logic.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clock_logic is
Port (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CE_1HZ : in STD_LOGIC; -- Enable signal from the divider
SW_DIN : in STD_LOGIC_VECTOR (3 downto 0);
BTN_LOAD : in STD_LOGIC_VECTOR (3 downto 0);
-- Outputs to the top module/display
S_UNITS : out STD_LOGIC_VECTOR (3 downto 0);
S_TENS : out STD_LOGIC_VECTOR (3 downto 0);
M_UNITS : out STD_LOGIC_VECTOR (3 downto 0);
M_TENS : out STD_LOGIC_VECTOR (3 downto 0);
H_UNITS : out STD_LOGIC_VECTOR (3 downto 0);
H_TENS : out STD_LOGIC_VECTOR (3 downto 0)
);
end clock_logic;
architecture Behavioral of clock_logic is
component counter is
Generic ( MAX_LIMIT : STD_LOGIC_VECTOR(3 downto 0) := "1001" ); -- Default to 9
Port ( CLK : in STD_LOGIC;
CE : in STD_LOGIC;
PE : in STD_LOGIC;
DIN : in STD_LOGIC_VECTOR(3 downto 0);
RST : in STD_LOGIC;
TC : out STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end component;
-- Internal signals to connect the counters
signal sig_s_units, sig_s_tens : std_logic_vector(3 downto 0);
signal sig_m_units, sig_m_tens : std_logic_vector(3 downto 0);
signal sig_h_units, sig_h_tens : std_logic_vector(3 downto 0);
-- Carry signals (TC)
signal tc_su, tc_st, tc_mu, tc_mt, tc_hu : std_logic;
-- Reset for hours (to handle the 24 reset)
signal hour_reset : std_logic;
-- Specific load enable signals that check for boundaries
signal load_h_tens, load_h_units : std_logic;
signal load_m_tens, load_m_units : std_logic;
-- Internal signals for the "Safe" load triggers
signal safe_load_su, safe_load_st : std_logic;
signal safe_load_mu, safe_load_mt : std_logic;
signal safe_load_hu, safe_load_ht : std_logic;
begin
-- MINUTES CONSTRAINTS (Max 59)
load_m_units <= BTN_LOAD(0) when (SW_DIN <= "1001") else '0'; -- 0-9
load_m_tens <= BTN_LOAD(1) when (SW_DIN <= "0101") else '0'; -- 0-5
-- HOURS CONSTRAINTS (Max 23)
-- Rule A: Cannot load Tens > 2.
-- Rule B: If Tens is 2, cannot load Units > 3.
-- Rule C: If Units is > 3, cannot load Tens into 2.
load_h_tens <= BTN_LOAD(3) when (
SW_DIN < "0010" or
(SW_DIN = "0010" and sig_h_units <= "0011")
) else '0';
load_h_units <= BTN_LOAD(2) when (
(sig_h_tens < "0010" and SW_DIN <= "1001") or
(sig_h_tens = "0010" and SW_DIN <= "0011")
) else '0';
-------------------------------------------------------
-- SECONDS SECTION
-- SECONDS UNITS (0-9) - Triggered by the 1Hz pulse
U_CNT_SEC_UNITS : counter
generic map ( MAX_LIMIT => "1001" ) -- do 9
port map (
CLK => CLK, RST => RST, CE => CE_1HZ,
PE => '0', DIN => "0000", -- Seconds usually don't need manual load
TC => tc_su, COUNT_OUT => sig_s_units
);
-- SECONDS TENS (0-5) - Triggered when Sec Units reach 9
U_CNT_SEC_TENS : counter
generic map ( MAX_LIMIT => "0101" ) -- do 5
port map (
CLK => CLK, RST => RST, CE => tc_su,
PE => '0', DIN => "0000",
TC => tc_st, COUNT_OUT => sig_s_tens
);
-------------------------------------------------------
-- MINUTES SECTION
-- MINUTES UNITS (0-9) - When Seconds reach 59
U_CNT_MIN_UNITS : counter
generic map ( MAX_LIMIT => "1001" ) -- do 9
port map (
CLK => CLK,
RST => RST,
CE => tc_st,
PE => load_m_units,
DIN => SW_DIN,
TC => tc_mu,
COUNT_OUT => sig_m_units
);
-- MINUTES TENS (0-5)
U_CNT_MIN_TENS : counter
generic map ( MAX_LIMIT => "0101" ) -- do 5
port map (
CLK => CLK,
RST => RST,
CE => tc_mu,
PE => load_m_tens,
DIN => SW_DIN,
TC => tc_mt,
COUNT_OUT => sig_m_tens
);
-------------------------------------------------------
-- HOURS SECTION
-- If we are at 23:59:59, the next tick should reset hours
process(sig_h_tens, sig_h_units, tc_mt, RST)
begin
if RST = '1' then
hour_reset <= '1';
elsif (sig_h_tens = "0010" and sig_h_units = "0011" and tc_mt = '1') then
hour_reset <= '1';
else
hour_reset <= '0';
end if;
end process;
-- HOURS UNITS (0-9)
U_CNT_HOR_UNITS : counter
generic map ( MAX_LIMIT => "1001" ) -- To 9
port map (
CLK => CLK,
RST => hour_reset,
CE => tc_mt,
PE => load_h_units,
DIN => SW_DIN,
TC => tc_hu,
COUNT_OUT => sig_h_units
);
-- HOURS TENS (0-2)
U_CNT_HOR_TENS : counter
generic map ( MAX_LIMIT => "0010" ) -- To 2
port map (
CLK => CLK,
RST => hour_reset,
CE => tc_hu,
PE => load_h_tens,
DIN => SW_DIN,
TC => open,
COUNT_OUT => sig_h_tens
);
-- Drive output ports
S_UNITS <= sig_s_units;
S_TENS <= sig_s_tens;
M_UNITS <= sig_m_units;
M_TENS <= sig_m_tens;
H_UNITS <= sig_h_units;
H_TENS <= sig_h_tens;
end Behavioral;

13
project_7/project_5.srcs/sources_1/new/counter.vhd
View File

@@ -45,9 +45,7 @@ end counter;
architecture Behavioral of counter is architecture Behavioral of counter is
-- Internal signal to keep track of the current number -- Internal signal to keep track of the current number
signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := (others => '0'); signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
-- (others => '0') je to iste ako "0000" pre 4 bity. Ale narozdiel od hardcode
-- robi nuly cez vsetky bity, takze zalezi na pocte bitov rodica
begin begin
-- Main counting logic -- Main counting logic
@@ -56,18 +54,23 @@ begin
if rising_edge(CLK) then if rising_edge(CLK) then
if RST = '1' then if RST = '1' then
s_cnt <= "0000"; s_cnt <= "0000";
TC <= '0'; -- Reset TC
elsif PE = '1' then elsif PE = '1' then
s_cnt <= DIN; s_cnt <= DIN;
TC <= '0';
elsif CE = '1' then elsif CE = '1' then
if s_cnt = MAX_LIMIT then if s_cnt = MAX_LIMIT then
s_cnt <= (others => '0'); -- Reset to 0 when limit is hit s_cnt <= "0000"; -- Reset to 0 when limit is hit
TC <= '1';
else else
s_cnt <= s_cnt + 1; -- Otherwise increment s_cnt <= s_cnt + 1; -- Otherwise increment
TC <= '0';
end if; end if;
else
TC <= '0';
end if; end if;
end if; end if;
end process; end process;
TC <= '1' when (s_cnt = MAX_LIMIT and CE = '1') else '0';
COUNT_OUT <= s_cnt; COUNT_OUT <= s_cnt;

72
project_7/project_5.srcs/sources_1/new/display_drive.vhd
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@@ -1,72 +0,0 @@
-- display_drive.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity display_driver is
Port (
CLK : in STD_LOGIC; -- Connect to 400Hz signal
RST : in STD_LOGIC;
-- The four BCD digits from your counters
DIGIT_0 : in STD_LOGIC_VECTOR (3 downto 0);
DIGIT_1 : in STD_LOGIC_VECTOR (3 downto 0);
DIGIT_2 : in STD_LOGIC_VECTOR (3 downto 0);
DIGIT_3 : in STD_LOGIC_VECTOR (3 downto 0);
-- Physical outputs to the FPGA pins
SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
ANODES : out STD_LOGIC_VECTOR (3 downto 0)
);
end display_driver;
architecture Behavioral of display_driver is
component counter_2bit is
Port ( CLK : in STD_LOGIC; RST : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (1 downto 0));
end component;
component decoder_an is
Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0);
ANODES : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component mux is
Port ( I0, I1, I2, I3 : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component dec_seg is
Port ( bcd : in STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (7 downto 0));
end component;
-- Internal signals stay here now
signal s_cnt_2bit : std_logic_vector(1 downto 0);
signal s_mux_out : std_logic_vector(3 downto 0);
begin
U_CNT_2BIT : counter_2bit
port map (CLK => CLK, RST => RST, COUNT_OUT => s_cnt_2bit);
U_DEC_ANODES : decoder_an
port map (SEL => s_cnt_2bit, ANODES => ANODES);
U_MUX : mux
port map (I0 => DIGIT_0, I1 => DIGIT_1, I2 => DIGIT_2, I3 => DIGIT_3,
S => s_cnt_2bit, Y => s_mux_out);
U_DEC_SEG : dec_seg
port map (BCD => s_mux_out, SEG => SEGMENTS);
end Behavioral;

215
project_7/project_5.srcs/sources_1/new/top_modul.vhd
View File

@@ -1,94 +1,213 @@
-- top_modul.vhd ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 14:40:14
-- Design Name:
-- Module Name: top_modul - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_modul is entity top_modul is
Port ( CLK : in STD_LOGIC; Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC; RST : in STD_LOGIC;
START : in STD_LOGIC; START : in STD_LOGIC;
SW_MODE : in STD_LOGIC; -- '0' = HH:MM, '1' = MM:SS SW_DIN : in STD_LOGIC_VECTOR (3 downto 0); -- The value to set
SW_DIN : in STD_LOGIC_VECTOR (3 downto 0); -- Value to set
BTN_LOAD : in STD_LOGIC_VECTOR (3 downto 0); -- Which digit to set BTN_LOAD : in STD_LOGIC_VECTOR (3 downto 0); -- Which digit to set
SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0); SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
ANODS : out STD_LOGIC_VECTOR (3 downto 0)); ANODS : out STD_LOGIC_VECTOR (3 downto 0));
end top_modul; end top_modul;
architecture Behavioral of top_modul is architecture Behavioral of top_modul is
component divider is component divider is
Port ( CLK : in STD_LOGIC; Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC; RST : in STD_LOGIC;
CLK_1_Hz : out STD_LOGIC); -- Enable pulse CLK_1_Hz : out STD_LOGIC); -- This will be our enable pulse
end component; end component;
component divider_400Hz is component divider_400Hz is
Port ( CLK : in STD_LOGIC; Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC; RST : in STD_LOGIC;
CLK_400_Hz : out STD_LOGIC); -- Enable pulse CLK_400_Hz : out STD_LOGIC); -- This will be our enable pulse
end component; end component;
component counter is
Generic ( MAX_LIMIT : STD_LOGIC_VECTOR(3 downto 0) := "1001" ); -- Default to 9
Port ( CLK : in STD_LOGIC;
CE : in STD_LOGIC;
PE : in STD_LOGIC;
DIN : in STD_LOGIC_VECTOR(3 downto 0);
RST : in STD_LOGIC;
TC : out STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component counter_2bit is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (1 downto 0));
end component;
component decoder_an is
Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0);
ANODES : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component mux is
Port ( I0 : in STD_LOGIC_VECTOR (3 downto 0);
I1 : in STD_LOGIC_VECTOR (3 downto 0);
I2 : in STD_LOGIC_VECTOR (3 downto 0);
I3 : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component dec_seg is
Port ( bcd : in STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal clk_1_Hz : std_logic; signal clk_1_Hz : std_logic;
signal clk_400_Hz : std_logic; signal clk_400_Hz : std_logic;
signal s_ce_units : std_logic; signal s_ce_units : std_logic;
-- Internal signals to connect the counters
signal sig_m_units : std_logic_vector(3 downto 0);
signal sig_m_tens : std_logic_vector(3 downto 0);
signal sig_h_units : std_logic_vector(3 downto 0);
signal sig_h_tens : std_logic_vector(3 downto 0);
-- Carry signals (TC)
signal tc_mu, tc_mt, tc_hu : std_logic;
-- Reset for hours (to handle the 24 reset)
signal hour_reset : std_logic;
-- You MUST declare these signals so top_modul can carry data between the two submodules signal s_cnt_2bit : std_logic_vector(1 downto 0);
signal sig_s_units, sig_s_tens : std_logic_vector(3 downto 0); signal s_mux_out : std_logic_vector(3 downto 0);
signal sig_m_units, sig_m_tens : std_logic_vector(3 downto 0);
signal sig_h_units, sig_h_tens : std_logic_vector(3 downto 0);
-- Signals to send to the display
signal d0, d1, d2, d3 : std_logic_vector(3 downto 0);
begin begin
U_DIV_1HZ : divider U_DIV : divider
port map ( port map (
CLK => CLK, CLK => CLK,
RST => RST, RST => RST,
CLK_1_Hz => clk_1_Hz CLK_1_Hz => clk_1_Hz
); );
U_DIV_REFRESH : divider_400Hz
U_DIV_400Hz : divider_400Hz
port map ( port map (
CLK => CLK, CLK => CLK,
RST => RST, RST => RST,
CLK_400_Hz => clk_400_Hz CLK_400_Hz => clk_400_Hz
); );
s_ce_units <= clk_1_Hz and START; s_ce_units <= clk_1_Hz and START;
-- MINUTES UNITS (0-9)
-- Clock Engine submodule U_CNT_MIN_UNITS : counter
U_CLOCK_CORE : entity work.clock_logic generic map ( MAX_LIMIT => "1001" ) -- To 9
port map ( port map (
CLK => CLK, CLK => CLK,
RST => RST, RST => RST,
CE_1HZ => s_ce_units, CE => s_ce_units,
SW_DIN => SW_DIN, PE => BTN_LOAD(0),
BTN_LOAD => BTN_LOAD, DIN => SW_DIN,
S_UNITS => sig_s_units, TC => tc_mu,
S_TENS => sig_s_tens, COUNT_OUT => sig_m_units
M_UNITS => sig_m_units,
M_TENS => sig_m_tens,
H_UNITS => sig_h_units,
H_TENS => sig_h_tens
); );
-- Mode Multiplexing -- MINUTES TENS (0-5)
-- If SW_MODE = '1', show MM:SS. If '0', show HH:MM. U_CNT_MIN_TENS : counter
d0 <= sig_s_units when SW_MODE = '1' else sig_m_units; generic map ( MAX_LIMIT => "0101" ) -- To 5
d1 <= sig_s_tens when SW_MODE = '1' else sig_m_tens;
d2 <= sig_m_units when SW_MODE = '1' else sig_h_units;
d3 <= sig_m_tens when SW_MODE = '1' else sig_h_tens;
U_DISPLAY : entity work.display_driver
port map ( port map (
CLK => clk_400_Hz, CLK => CLK,
RST => RST, RST => RST,
DIGIT_0 => d0, CE => tc_mu,
DIGIT_1 => d1, PE => BTN_LOAD(1),
DIGIT_2 => d2, DIN => SW_DIN,
DIGIT_3 => d3, TC => tc_mt,
SEGMENTS => SEGMENTS, COUNT_OUT => sig_m_tens
ANODES => ANODS );
);
-- Logic to reset hours at 24:00
hour_reset <= '1' when (RST = '1' or (sig_h_tens = "0010" and sig_h_units = "0011" and tc_mt = '1')) else '0';
-- HOURS UNITS (0-9)
U_CNT_HOR_UNITS : counter
generic map ( MAX_LIMIT => "1001" ) -- To 9
port map (
CLK => CLK,
RST => hour_reset,
CE => tc_mt,
PE => BTN_LOAD(2),
DIN => SW_DIN,
TC => tc_hu,
COUNT_OUT => sig_h_units
);
-- HOURS TENS (0-2)
U_CNT_HOR_TENS : counter
generic map ( MAX_LIMIT => "0010" ) -- To 2
port map (
CLK => CLK,
RST => hour_reset,
CE => tc_hu,
PE => BTN_LOAD(3),
DIN => SW_DIN,
TC => open,
COUNT_OUT => sig_h_tens
);
U_CNT_2BIT : counter_2bit
port map (
CLK => clk_400_Hz,
RST => RST,
COUNT_OUT => s_cnt_2bit
);
U_DEC_ANODES : decoder_an
port map (
SEL => s_cnt_2bit,
ANODES => ANODS
);
U_MUX : mux
port map (
I0 => sig_m_units,
I1 => sig_m_tens,
I2 => sig_h_units,
I3 => sig_h_tens,
S => s_cnt_2bit,
Y => s_mux_out
);
U_DEC_SEG : dec_seg
port map (
BCD => s_mux_out,
SEG => SEGMENTS
);
end Behavioral; end Behavioral;

12
project_7/project_5.xpr
View File

@@ -92,12 +92,6 @@
<FileSets Version="1" Minor="31"> <FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/clock_logic.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/counter.vhd"> <File Path="$PSRCDIR/sources_1/new/counter.vhd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -122,12 +116,6 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/display_drive.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/divider.vhd"> <File Path="$PSRCDIR/sources_1/new/divider.vhd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>

158
project_7_hodiny/project_6.srcs/constrs_1/imports/Downloads/Basys-3-Master.xdc
View File

@@ -1,158 +0,0 @@
## This file is a general .xdc for the Basys3 rev B board
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
## Clock signal
set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports CLK]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
## Switches
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {RST}]
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {START}]
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {sw[2]}]
#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports {sw[3]}]
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {sw[4]}]
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports {sw[5]}]
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports {sw[6]}]
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports {sw[7]}]
#set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports {sw[8]}]
#set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports {sw[9]}]
#set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports {sw[10]}]
#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {sw[11]}]
#set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports {sw[12]}]
#set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports {sw[13]}]
#set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {sw[14]}]
#set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {sw[15]}]
## LEDs
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports {led[0]}]
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports {led[1]}]
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports {led[2]}]
#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports {led[3]}]
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports {led[4]}]
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports {led[5]}]
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports {led[6]}]
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports {led[7]}]
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports {led[8]}]
#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports {led[9]}]
#set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports {led[10]}]
#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports {led[11]}]
#set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports {led[12]}]
#set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports {led[13]}]
#set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports {led[14]}]
#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports {led[15]}]
##7 Segment Display
set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[0]}]
set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[1]}]
set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[2]}]
set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[3]}]
set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[4]}]
set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[5]}]
set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[6]}]
set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[7]}]
set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports {ANODS[0]}]
set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports {ANODS[1]}]
set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports {ANODS[2]}]
set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports {ANODS[3]}]
##Buttons
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports btnC]
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports btnU]
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports btnL]
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports btnR]
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports btnD]
##Pmod Header JA
#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports {JA[0]}];#Sch name = JA1
#set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports {JA[1]}];#Sch name = JA2
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports {JA[2]}];#Sch name = JA3
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports {JA[3]}];#Sch name = JA4
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports {JA[4]}];#Sch name = JA7
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports {JA[5]}];#Sch name = JA8
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports {JA[6]}];#Sch name = JA9
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports {JA[7]}];#Sch name = JA10
##Pmod Header JB
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports {JB[0]}];#Sch name = JB1
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports {JB[1]}];#Sch name = JB2
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports {JB[2]}];#Sch name = JB3
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports {JB[3]}];#Sch name = JB4
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports {JB[4]}];#Sch name = JB7
#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports {JB[5]}];#Sch name = JB8
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports {JB[6]}];#Sch name = JB9
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports {JB[7]}];#Sch name = JB10
##Pmod Header JC
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports {JC[0]}];#Sch name = JC1
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports {JC[1]}];#Sch name = JC2
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports {JC[2]}];#Sch name = JC3
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports {JC[3]}];#Sch name = JC4
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports {JC[4]}];#Sch name = JC7
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports {JC[5]}];#Sch name = JC8
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports {JC[6]}];#Sch name = JC9
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports {JC[7]}];#Sch name = JC10
##Pmod Header JXADC
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[0]}];#Sch name = XA1_P
#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[1]}];#Sch name = XA2_P
#set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[2]}];#Sch name = XA3_P
#set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[3]}];#Sch name = XA4_P
#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[4]}];#Sch name = XA1_N
#set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[5]}];#Sch name = XA2_N
#set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[6]}];#Sch name = XA3_N
#set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[7]}];#Sch name = XA4_N
##VGA Connector
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[0]}]
#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[1]}]
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[2]}]
#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[3]}]
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[0]}]
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[1]}]
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[2]}]
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[3]}]
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[0]}]
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[1]}]
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[2]}]
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[3]}]
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports Hsync]
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports Vsync]
##USB-RS232 Interface
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports RsRx]
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports RsTx]
##USB HID (PS/2)
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Clk]
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Data]
##Quad SPI Flash
##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
##STARTUPE2 primitive.
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[0]}]
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[1]}]
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[2]}]
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[3]}]
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports QspiCSn]
## Configuration options, can be used for all designs
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
## SPI configuration mode options for QSPI boot, can be used for all designs
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]

55
project_7_hodiny/project_6.srcs/sources_1/new/counter_2bit.vhd
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@@ -1,55 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 15:32:13
-- Design Name:
-- Module Name: counter_2bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter_2bit is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (1 downto 0));
end counter_2bit;
architecture Behavioral of counter_2bit is
signal s_cnt : STD_LOGIC_VECTOR(1 downto 0) := "00";
begin
process(CLK, RST)
begin
if RST = '1' then
s_cnt <= "00";
elsif rising_edge(CLK) then
s_cnt <= s_cnt + 1;
end if;
end process;
COUNT_OUT <= s_cnt;
end Behavioral;

42
project_7_hodiny/project_6.srcs/sources_1/new/counters_hours/counter_hour_tens.vhd
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@@ -1,42 +0,0 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( CLK : in STD_LOGIC;
DIN : in STD_LOGIC_VECTOR (3 downto 0); -- teraz nas nezaujima
PE : in STD_LOGIC; -- teraz nas nezaujima
CE : in STD_LOGIC;
RST : in STD_LOGIC;
TC : out STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (2 downto 0));
end counter;
architecture Behavioral of counter is
-- Internal signal to keep track of the current number
signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin
-- Main counting logic
process(CLK)
begin
if rising_edge(CLK) then
if RST = '1' then
s_cnt <= "0000";
elsif CE = '1' then
-- toto preto, lebo su to desiatky hodin, 24 hod je max, takze
-- iba 0 - 2
if s_cnt = "0010" then
s_cnt <= "0000"; -- Reset to 0
else
s_cnt <= s_cnt + 1;
end if;
end if;
end if;
end process;
-- Drive the output ports
COUNT_OUT <= s_cnt;
end Behavioral;

37
project_7_hodiny/project_6.srcs/sources_1/new/counters_hours/counter_minute_tens.vhd
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@@ -1,37 +0,0 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CE : in STD_LOGIC;
TC : out STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture Behavioral of counter is
-- Internal signal to keep track of the current number
signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin
-- Main counting logic
process(CLK)
begin
if rising_edge(CLK) then
if RST = '1' then
s_cnt <= "0000";
elsif CE = '1' then
if s_cnt = "0110" then -- If we are at 6
s_cnt <= "0000"; -- Reset to 0
else
s_cnt <= s_cnt + 1; -- Increment
end if;
end if;
end if;
end process;
COUNT_OUT <= s_cnt;
end Behavioral;

37
project_7_hodiny/project_6.srcs/sources_1/new/counters_hours/counter_ones.vhd
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@@ -1,37 +0,0 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( CLK : in STD_LOGIC;
CE : in STD_LOGIC;
RST : in STD_LOGIC;
TC : out STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture Behavioral of counter is
-- Internal signal to keep track of the current number
signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin
process(CLK)
begin
if rising_edge(CLK) then
if RST = '1' then
s_cnt <= "0000";
elsif CE = '1' then
if s_cnt = "1001" then -- If we are at 9
s_cnt <= "0000"; -- Reset to 0
else
s_cnt <= s_cnt + 1;
end if;
end if;
end if;
end process;
COUNT_OUT <= s_cnt;
end Behavioral;

58
project_7_hodiny/project_6.srcs/sources_1/new/dec2.vhd
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@@ -1,58 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 15:54:24
-- Design Name:
-- Module Name: dec_seg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dec_seg is
Port ( BCD : in STD_LOGIC_VECTOR (3 downto 0);
SEG : out STD_LOGIC_VECTOR (7 downto 0));
end dec_seg;
architecture Behavioral of dec_seg is
begin
-- Konverzia BCD na 7-segment (ABCDEFG + DP)
-- Form<72>t: "ABCDEFG DP"
with bcd select
seg <= "11000000" when "0000", -- 0
"11111001" when "0001", -- 1
"10100100" when "0010", -- 2
"10110000" when "0011", -- 3
"10011001" when "0100", -- 4
"10010010" when "0101", -- 5
"10000010" when "0110", -- 6
"11111000" when "0111", -- 7
"10000000" when "1000", -- 8
"10010000" when "1001", -- 9
"11111111" when others; -- off
end Behavioral;

50
project_7_hodiny/project_6.srcs/sources_1/new/decoder_bottom.vhd
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@@ -1,50 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 15:39:11
-- Design Name:
-- Module Name: decoder_bottom - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity decoder_an is
Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0);
ANODES : out STD_LOGIC_VECTOR (3 downto 0));
end decoder_an;
architecture Behavioral of decoder_an is
begin
with SEL select
ANODES <= "1110" when "00",
"1101" when "01",
"1011" when "10",
"0111" when "11",
"1111" when others;
end Behavioral;

60
project_7_hodiny/project_6.srcs/sources_1/new/divider.vhd
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@@ -1,60 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 14:43:21
-- Design Name:
-- Module Name: divider - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity divider is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CLK_1_Hz : out STD_LOGIC);
end divider;
architecture Behavioral of divider is
-- 27 bits is enough for 100 million
signal s_cnt : STD_LOGIC_VECTOR(26 downto 0) := (others => '0');
begin
process(CLK)
begin
if rising_edge(CLK) then
if RST = '1' then
s_cnt <= (others => '0');
CLK_1_Hz <= '0';
elsif s_cnt = 99_999_999 then
s_cnt <= (others => '0');
CLK_1_Hz <= '1'; -- The pulse
else
s_cnt <= s_cnt + 1;
CLK_1_Hz <= '0';
end if;
end if;
end process;
end Behavioral;

60
project_7_hodiny/project_6.srcs/sources_1/new/divider_400Hz.vhd
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@@ -1,60 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 14:49:47
-- Design Name:
-- Module Name: divider_400Hz - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity divider_400Hz is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CLK_400_Hz : out STD_LOGIC);
end divider_400Hz;
architecture Behavioral of divider_400Hz is
-- 18 bits is enough for 250,000
signal s_cnt : STD_LOGIC_VECTOR(17 downto 0) := (others => '0');
begin
process(CLK)
begin
if rising_edge(CLK) then
if RST = '1' then
s_cnt <= (others => '0');
CLK_400_Hz <= '0';
elsif s_cnt = 249_999 then
s_cnt <= (others => '0');
CLK_400_Hz <= '1';
else
s_cnt <= s_cnt + 1;
CLK_400_Hz <= '0';
end if;
end if;
end process;
end Behavioral;

53
project_7_hodiny/project_6.srcs/sources_1/new/mux.vhd
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@@ -1,53 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 15:47:51
-- Design Name:
-- Module Name: mux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux is
Port ( I0 : in STD_LOGIC_VECTOR (3 downto 0);
I1 : in STD_LOGIC_VECTOR (3 downto 0);
I2 : in STD_LOGIC_VECTOR (3 downto 0);
I3 : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end mux;
architecture Behavioral of mux is
begin
with S select
Y <= I0 when "00",
I1 when "01",
I2 when "10",
I3 when "11",
"0000" when others;
end Behavioral;

182
project_7_hodiny/project_6.srcs/sources_1/new/top_modul.vhd
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@@ -1,182 +0,0 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top_modul is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
START : in STD_LOGIC;
SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
ANODS : out STD_LOGIC_VECTOR (3 downto 0));
end top_modul;
architecture Behavioral of top_modul is
component divider is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CLK_1_Hz : out STD_LOGIC); -- This will be our enable pulse
end component;
component divider_400Hz is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CLK_400_Hz : out STD_LOGIC); -- This will be our enable pulse
end component;
component cnt_0_9 is
Port ( CLK : in STD_LOGIC;
CE : in STD_LOGIC;
RST : in STD_LOGIC;
TC : out STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component cnt_0_5 is
Port ( CLK : in STD_LOGIC;
CE : in STD_LOGIC;
RST : in STD_LOGIC;
TC : out STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component cnt_0_2 is
Port ( CLK : in STD_LOGIC;
CE : in STD_LOGIC;
RST : in STD_LOGIC;
TC : out STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component counter_2bit is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (1 downto 0));
end component;
component decoder_an is
Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0);
ANODES : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component mux is
Port ( I0 : in STD_LOGIC_VECTOR (3 downto 0);
I1 : in STD_LOGIC_VECTOR (3 downto 0);
I2 : in STD_LOGIC_VECTOR (3 downto 0);
I3 : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component dec_seg is
Port ( bcd : in STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal clk_1_Hz : std_logic;
signal clk_400_Hz : std_logic;
-- Internal signals to connect the counters
signal sig_m_units : std_logic_vector(3 downto 0);
signal sig_m_tens : std_logic_vector(3 downto 0);
signal sig_h_units : std_logic_vector(3 downto 0);
signal sig_h_tens : std_logic_vector(3 downto 0);
-- Carry signals (TC)
signal tc_mu, tc_mt, tc_hu : std_logic;
-- Reset for hours (to handle the 24 reset)
signal hour_reset : std_logic;
signal s_cnt_2bit : std_logic_vector(1 downto 0);
signal s_mux_out : std_logic_vector(3 downto 0);
begin
U_DIV : divider
port map (
CLK => CLK,
RST => RST,
CLK_1_Hz => clk_1_Hz
);
U_DIV_400Hz : divider_400Hz
port map (
CLK => CLK,
RST => RST,
CLK_400_Hz => clk_400_Hz
);
-- MINUTES UNITS (0-9)
U_CNT_MIN_UNITS : cnt_0_9
port map (
CLK => CLK,
RST => RST,
CE => clk_1_Hz and START,
TC => tc_mu,
COUNT_OUT => sig_m_units
);
-- MINUTES TENS (0-5)
U_CNT_MIN_TENS : cnt_0_5
port map (
CLK => CLK,
RST => RST,
CE => tc_mu,
TC => tc_mt,
COUNT_OUT => sig_m_tens
);
-- Logic to reset hours at 24:00
hour_reset <= '1' when (RST = '1' or (sig_h_tens = "0010" and sig_h_units = "0100")) else '0';
-- HOURS UNITS (0-9)
U_CNT_HOR_UNITS : cnt_0_9
port map (
CLK => CLK,
RST => hour_reset,
CE => tc_mt,
TC => tc_hu,
COUNT_OUT => sig_h_units
);
-- HOURS TENS (0-2)
U_CNT_HOR_TENS : cnt_0_2
port map (
CLK => CLK,
RST => hour_reset,
CE => tc_hu,
TC => open,
COUNT_OUT => sig_h_tens
);
U_CNT_2BIT : counter_2bit
port map (
CLK => clk_400_Hz,
RST => RST,
COUNT_OUT => s_cnt_2bit
);
U_DEC_ANODES : decoder_an
port map (
SEL => s_cnt_2bit, -- 2-bitov<6F> sign<67>l
ANODES => ANODS -- V<>stupn<70> port top modulu
);
U_MUX : mux
port map (
I0 => sig_m_units, -- Corrected signal names
I1 => sig_m_tens,
I2 => sig_h_units,
I3 => sig_h_tens,
S => s_cnt_2bit,
Y => s_mux_out
);
U_DEC_SEG : dec_seg
port map (
BCD => s_mux_out,
SEG => SEGMENTS
);
end Behavioral;