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Filipriec
2026-03-23 14:04:42 +01:00
parent 93c5b504fb
commit dd7d083112
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55
project_7_hodiny/project_6.srcs/sources_1/new/counter_2bit.vhd Normal file
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 15:32:13
-- Design Name:
-- Module Name: counter_2bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter_2bit is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (1 downto 0));
end counter_2bit;
architecture Behavioral of counter_2bit is
signal s_cnt : STD_LOGIC_VECTOR(1 downto 0) := "00";
begin
process(CLK, RST)
begin
if RST = '1' then
s_cnt <= "00";
elsif rising_edge(CLK) then
s_cnt <= s_cnt + 1;
end if;
end process;
COUNT_OUT <= s_cnt;
end Behavioral;

42
project_7_hodiny/project_6.srcs/sources_1/new/counters_hours/counter_hour_tens.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( CLK : in STD_LOGIC;
DIN : in STD_LOGIC_VECTOR (3 downto 0); -- teraz nas nezaujima
PE : in STD_LOGIC; -- teraz nas nezaujima
CE : in STD_LOGIC;
RST : in STD_LOGIC;
TC : out STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (2 downto 0));
end counter;
architecture Behavioral of counter is
-- Internal signal to keep track of the current number
signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin
-- Main counting logic
process(CLK)
begin
if rising_edge(CLK) then
if RST = '1' then
s_cnt <= "0000";
elsif CE = '1' then
-- toto preto, lebo su to desiatky hodin, 24 hod je max, takze
-- iba 0 - 2
if s_cnt = "0010" then
s_cnt <= "0000"; -- Reset to 0
else
s_cnt <= s_cnt + 1;
end if;
end if;
end if;
end process;
-- Drive the output ports
COUNT_OUT <= s_cnt;
end Behavioral;

37
project_7_hodiny/project_6.srcs/sources_1/new/counters_hours/counter_minute_tens.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CE : in STD_LOGIC;
TC : out STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture Behavioral of counter is
-- Internal signal to keep track of the current number
signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin
-- Main counting logic
process(CLK)
begin
if rising_edge(CLK) then
if RST = '1' then
s_cnt <= "0000";
elsif CE = '1' then
if s_cnt = "0110" then -- If we are at 6
s_cnt <= "0000"; -- Reset to 0
else
s_cnt <= s_cnt + 1; -- Increment
end if;
end if;
end if;
end process;
COUNT_OUT <= s_cnt;
end Behavioral;

37
project_7_hodiny/project_6.srcs/sources_1/new/counters_hours/counter_ones.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( CLK : in STD_LOGIC;
CE : in STD_LOGIC;
RST : in STD_LOGIC;
TC : out STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture Behavioral of counter is
-- Internal signal to keep track of the current number
signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin
process(CLK)
begin
if rising_edge(CLK) then
if RST = '1' then
s_cnt <= "0000";
elsif CE = '1' then
if s_cnt = "1001" then -- If we are at 9
s_cnt <= "0000"; -- Reset to 0
else
s_cnt <= s_cnt + 1;
end if;
end if;
end if;
end process;
COUNT_OUT <= s_cnt;
end Behavioral;

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project_7_hodiny/project_6.srcs/sources_1/new/dec2.vhd Normal file
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 15:54:24
-- Design Name:
-- Module Name: dec_seg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dec_seg is
Port ( BCD : in STD_LOGIC_VECTOR (3 downto 0);
SEG : out STD_LOGIC_VECTOR (7 downto 0));
end dec_seg;
architecture Behavioral of dec_seg is
begin
-- Konverzia BCD na 7-segment (ABCDEFG + DP)
-- Form<72>t: "ABCDEFG DP"
with bcd select
seg <= "11000000" when "0000", -- 0
"11111001" when "0001", -- 1
"10100100" when "0010", -- 2
"10110000" when "0011", -- 3
"10011001" when "0100", -- 4
"10010010" when "0101", -- 5
"10000010" when "0110", -- 6
"11111000" when "0111", -- 7
"10000000" when "1000", -- 8
"10010000" when "1001", -- 9
"11111111" when others; -- off
end Behavioral;

50
project_7_hodiny/project_6.srcs/sources_1/new/decoder_bottom.vhd Normal file
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 15:39:11
-- Design Name:
-- Module Name: decoder_bottom - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity decoder_an is
Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0);
ANODES : out STD_LOGIC_VECTOR (3 downto 0));
end decoder_an;
architecture Behavioral of decoder_an is
begin
with SEL select
ANODES <= "1110" when "00",
"1101" when "01",
"1011" when "10",
"0111" when "11",
"1111" when others;
end Behavioral;

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project_7_hodiny/project_6.srcs/sources_1/new/divider.vhd Normal file
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 14:43:21
-- Design Name:
-- Module Name: divider - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity divider is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CLK_1_Hz : out STD_LOGIC);
end divider;
architecture Behavioral of divider is
-- 27 bits is enough for 100 million
signal s_cnt : STD_LOGIC_VECTOR(26 downto 0) := (others => '0');
begin
process(CLK)
begin
if rising_edge(CLK) then
if RST = '1' then
s_cnt <= (others => '0');
CLK_1_Hz <= '0';
elsif s_cnt = 99_999_999 then
s_cnt <= (others => '0');
CLK_1_Hz <= '1'; -- The pulse
else
s_cnt <= s_cnt + 1;
CLK_1_Hz <= '0';
end if;
end if;
end process;
end Behavioral;

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project_7_hodiny/project_6.srcs/sources_1/new/divider_400Hz.vhd Normal file
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 14:49:47
-- Design Name:
-- Module Name: divider_400Hz - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity divider_400Hz is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CLK_400_Hz : out STD_LOGIC);
end divider_400Hz;
architecture Behavioral of divider_400Hz is
-- 18 bits is enough for 250,000
signal s_cnt : STD_LOGIC_VECTOR(17 downto 0) := (others => '0');
begin
process(CLK)
begin
if rising_edge(CLK) then
if RST = '1' then
s_cnt <= (others => '0');
CLK_400_Hz <= '0';
elsif s_cnt = 249_999 then
s_cnt <= (others => '0');
CLK_400_Hz <= '1';
else
s_cnt <= s_cnt + 1;
CLK_400_Hz <= '0';
end if;
end if;
end process;
end Behavioral;

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project_7_hodiny/project_6.srcs/sources_1/new/mux.vhd Normal file
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.03.2026 15:47:51
-- Design Name:
-- Module Name: mux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux is
Port ( I0 : in STD_LOGIC_VECTOR (3 downto 0);
I1 : in STD_LOGIC_VECTOR (3 downto 0);
I2 : in STD_LOGIC_VECTOR (3 downto 0);
I3 : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end mux;
architecture Behavioral of mux is
begin
with S select
Y <= I0 when "00",
I1 when "01",
I2 when "10",
I3 when "11",
"0000" when others;
end Behavioral;

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project_7_hodiny/project_6.srcs/sources_1/new/top_modul.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top_modul is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
START : in STD_LOGIC;
SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
ANODS : out STD_LOGIC_VECTOR (3 downto 0));
end top_modul;
architecture Behavioral of top_modul is
component divider is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CLK_1_Hz : out STD_LOGIC); -- This will be our enable pulse
end component;
component divider_400Hz is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CLK_400_Hz : out STD_LOGIC); -- This will be our enable pulse
end component;
component cnt_0_9 is
Port ( CLK : in STD_LOGIC;
CE : in STD_LOGIC;
RST : in STD_LOGIC;
TC : out STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component cnt_0_5 is
Port ( CLK : in STD_LOGIC;
CE : in STD_LOGIC;
RST : in STD_LOGIC;
TC : out STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component cnt_0_2 is
Port ( CLK : in STD_LOGIC;
CE : in STD_LOGIC;
RST : in STD_LOGIC;
TC : out STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component counter_2bit is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (1 downto 0));
end component;
component decoder_an is
Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0);
ANODES : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component mux is
Port ( I0 : in STD_LOGIC_VECTOR (3 downto 0);
I1 : in STD_LOGIC_VECTOR (3 downto 0);
I2 : in STD_LOGIC_VECTOR (3 downto 0);
I3 : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component dec_seg is
Port ( bcd : in STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal clk_1_Hz : std_logic;
signal clk_400_Hz : std_logic;
-- Internal signals to connect the counters
signal sig_m_units : std_logic_vector(3 downto 0);
signal sig_m_tens : std_logic_vector(3 downto 0);
signal sig_h_units : std_logic_vector(3 downto 0);
signal sig_h_tens : std_logic_vector(3 downto 0);
-- Carry signals (TC)
signal tc_mu, tc_mt, tc_hu : std_logic;
-- Reset for hours (to handle the 24 reset)
signal hour_reset : std_logic;
signal s_cnt_2bit : std_logic_vector(1 downto 0);
signal s_mux_out : std_logic_vector(3 downto 0);
begin
U_DIV : divider
port map (
CLK => CLK,
RST => RST,
CLK_1_Hz => clk_1_Hz
);
U_DIV_400Hz : divider_400Hz
port map (
CLK => CLK,
RST => RST,
CLK_400_Hz => clk_400_Hz
);
-- MINUTES UNITS (0-9)
U_CNT_MIN_UNITS : cnt_0_9
port map (
CLK => CLK,
RST => RST,
CE => clk_1_Hz and START,
TC => tc_mu,
COUNT_OUT => sig_m_units
);
-- MINUTES TENS (0-5)
U_CNT_MIN_TENS : cnt_0_5
port map (
CLK => CLK,
RST => RST,
CE => tc_mu,
TC => tc_mt,
COUNT_OUT => sig_m_tens
);
-- Logic to reset hours at 24:00
hour_reset <= '1' when (RST = '1' or (sig_h_tens = "0010" and sig_h_units = "0100")) else '0';
-- HOURS UNITS (0-9)
U_CNT_HOR_UNITS : cnt_0_9
port map (
CLK => CLK,
RST => hour_reset,
CE => tc_mt,
TC => tc_hu,
COUNT_OUT => sig_h_units
);
-- HOURS TENS (0-2)
U_CNT_HOR_TENS : cnt_0_2
port map (
CLK => CLK,
RST => hour_reset,
CE => tc_hu,
TC => open,
COUNT_OUT => sig_h_tens
);
U_CNT_2BIT : counter_2bit
port map (
CLK => clk_400_Hz,
RST => RST,
COUNT_OUT => s_cnt_2bit
);
U_DEC_ANODES : decoder_an
port map (
SEL => s_cnt_2bit, -- 2-bitov<6F> sign<67>l
ANODES => ANODS -- V<>stupn<70> port top modulu
);
U_MUX : mux
port map (
I0 => sig_m_units, -- Corrected signal names
I1 => sig_m_tens,
I2 => sig_h_units,
I3 => sig_h_tens,
S => s_cnt_2bit,
Y => s_mux_out
);
U_DEC_SEG : dec_seg
port map (
BCD => s_mux_out,
SEG => SEGMENTS
);
end Behavioral;