From dd7d0831123a6a5799cffb36f209f8e4ab7c7472 Mon Sep 17 00:00:00 2001 From: Filipriec Date: Mon, 23 Mar 2026 14:04:42 +0100 Subject: [PATCH] clock --- project_6/proj.mermaid | 117 +++++++++++ project_6/proj.mermaid.svg | 1 + project_6/proj2.mermaid | 82 ++++++++ project_6/proj2.mermaid.svg | 1 + .../imports/Downloads/Basys-3-Master.xdc | 158 +++++++++++++++ .../sources_1/new/counter_2bit.vhd | 55 ++++++ .../new/counters_hours/counter_hour_tens.vhd | 42 ++++ .../counters_hours/counter_minute_tens.vhd | 37 ++++ .../new/counters_hours/counter_ones.vhd | 37 ++++ .../project_6.srcs/sources_1/new/dec2.vhd | 58 ++++++ .../sources_1/new/decoder_bottom.vhd | 50 +++++ .../project_6.srcs/sources_1/new/divider.vhd | 60 ++++++ .../sources_1/new/divider_400Hz.vhd | 60 ++++++ .../project_6.srcs/sources_1/new/mux.vhd | 53 +++++ .../sources_1/new/top_modul.vhd | 182 ++++++++++++++++++ 15 files changed, 993 insertions(+) create mode 100644 project_6/proj.mermaid create mode 100644 project_6/proj.mermaid.svg create mode 100644 project_6/proj2.mermaid create mode 100644 project_6/proj2.mermaid.svg create mode 100644 project_7_hodiny/project_6.srcs/constrs_1/imports/Downloads/Basys-3-Master.xdc create mode 100644 project_7_hodiny/project_6.srcs/sources_1/new/counter_2bit.vhd create mode 100644 project_7_hodiny/project_6.srcs/sources_1/new/counters_hours/counter_hour_tens.vhd create mode 100644 project_7_hodiny/project_6.srcs/sources_1/new/counters_hours/counter_minute_tens.vhd create mode 100644 project_7_hodiny/project_6.srcs/sources_1/new/counters_hours/counter_ones.vhd create mode 100644 project_7_hodiny/project_6.srcs/sources_1/new/dec2.vhd create mode 100644 project_7_hodiny/project_6.srcs/sources_1/new/decoder_bottom.vhd create mode 100644 project_7_hodiny/project_6.srcs/sources_1/new/divider.vhd create mode 100644 project_7_hodiny/project_6.srcs/sources_1/new/divider_400Hz.vhd create mode 100644 project_7_hodiny/project_6.srcs/sources_1/new/mux.vhd create mode 100644 project_7_hodiny/project_6.srcs/sources_1/new/top_modul.vhd diff --git a/project_6/proj.mermaid b/project_6/proj.mermaid new file mode 100644 index 0000000..92f7521 --- /dev/null +++ b/project_6/proj.mermaid @@ -0,0 +1,117 @@ +flowchart TD + + %% ── External ports ────────────────────────────────────────── + CLK([CLK]) + RST([RST]) + START([START]) + SEGMENTS([SEGMENTS\nout]) + ANODS([ANODS\nout]) + + %% ════════════════════════════════════════════════════════════ + %% FILE: divider.vhd + %% ════════════════════════════════════════════════════════════ + subgraph FILE_DIV["📄 divider.vhd — entity: divider"] + direction TB + DIV["U_DIV\ndivider\n─────────────\nIN: CLK, RST\nOUT: CLK_1_Hz"] + end + + %% ════════════════════════════════════════════════════════════ + %% FILE: divider_400Hz.vhd + %% ════════════════════════════════════════════════════════════ + subgraph FILE_DIV400["📄 divider_400Hz.vhd — entity: divider_400Hz"] + direction TB + DIV400["U_DIV_400Hz\ndivider_400Hz\n─────────────\nIN: CLK, RST\nOUT: CLK_400_Hz"] + end + + %% ════════════════════════════════════════════════════════════ + %% FILE: counter.vhd + %% ════════════════════════════════════════════════════════════ + subgraph FILE_CNT["📄 counter.vhd — entity: counter (reused 4x)"] + direction TB + CNT_U["U_CNT_TOP\ncounter - Units\n─────────────\nIN: CLK, RST, CE\nOUT: COUNT_OUT, TC"] + CNT_T["U_CNT_BOTTOM\ncounter - Tens\n─────────────\nIN: CLK, RST, CE\nOUT: COUNT_OUT, TC"] + CNT_H["U_CNT_3\ncounter - Hundreds\n─────────────\nIN: CLK, RST, CE\nOUT: COUNT_OUT, TC"] + CNT_K["U_CNT_4\ncounter - Thousands\n─────────────\nIN: CLK, RST, CE\nOUT: COUNT_OUT, TC=open"] + end + + %% ════════════════════════════════════════════════════════════ + %% FILE: counter_2bit.vhd + %% ════════════════════════════════════════════════════════════ + subgraph FILE_CNT2["📄 counter_2bit.vhd — entity: counter_2bit"] + direction TB + CNT2["U_CNT_2BIT\ncounter_2bit\n─────────────\nIN: CLK=clk_400Hz, RST\nOUT: COUNT_OUT 2-bit"] + end + + %% ════════════════════════════════════════════════════════════ + %% FILE: decoder_bottom.vhd + %% ════════════════════════════════════════════════════════════ + subgraph FILE_DEC_AN["📄 decoder_bottom.vhd — entity: decoder_an"] + direction TB + DEC_AN["U_DEC_ANODES\ndecoder_an\n─────────────\nIN: SEL 2-bit\nOUT: ANODES 4-bit"] + end + + %% ════════════════════════════════════════════════════════════ + %% FILE: mux.vhd + %% ════════════════════════════════════════════════════════════ + subgraph FILE_MUX["📄 mux.vhd — entity: mux"] + direction TB + MUX["U_MUX\nmux 4x4-bit\n─────────────\nIN: I0,I1,I2,I3, S 2-bit\nOUT: Y 4-bit"] + end + + %% ════════════════════════════════════════════════════════════ + %% FILE: dec2.vhd + %% ════════════════════════════════════════════════════════════ + subgraph FILE_DEC_SEG["📄 dec2.vhd — entity: dec_seg"] + direction TB + DEC_SEG["U_DEC_SEG\ndec_seg\n─────────────\nIN: BCD 4-bit\nOUT: SEG 8-bit"] + end + + %% ════════════════════════════════════════════════════════════ + %% top_modul.vhd — glue logic defined directly in this file + %% ════════════════════════════════════════════════════════════ + subgraph FILE_TOP["📄 top_modul.vhd — glue signals defined here"] + direction TB + AND_START{"s_ce_units\nclk_1_Hz AND START"} + AND2{"CE for Hundreds\ns_tc_units AND s_tc_tens"} + AND3{"CE for Thousands\ns_tc_units AND s_tc_tens\nAND s_tc_hundreds"} + end + + %% ── Clock / Reset wiring ───────────────────────────────────── + CLK --> DIV + RST --> DIV + CLK --> DIV400 + RST --> DIV400 + CLK --> CNT_U & CNT_T & CNT_H & CNT_K + RST --> CNT_U & CNT_T & CNT_H & CNT_K & CNT2 + + %% ── 1 Hz chain ─────────────────────────────────────────────── + DIV -->|"clk_1_Hz"| AND_START + START --> AND_START + AND_START -->|"s_ce_units (CE)"| CNT_U + + %% ── BCD carry chain ────────────────────────────────────────── + CNT_U -->|"s_tc_units (TC->CE)"| CNT_T + CNT_U -->|"s_tc_units"| AND2 + CNT_T -->|"s_tc_tens"| AND2 + AND2 -->|"CE"| CNT_H + + CNT_U -->|"s_tc_units"| AND3 + CNT_T -->|"s_tc_tens"| AND3 + CNT_H -->|"s_tc_hundreds"| AND3 + AND3 -->|"CE"| CNT_K + + %% ── 400 Hz display scan ────────────────────────────────────── + DIV400 -->|"clk_400_Hz"| CNT2 + CNT2 -->|"s_cnt_2bit (SEL)"| DEC_AN + CNT2 -->|"s_cnt_2bit (S)"| MUX + DEC_AN -->|"ANODES"| ANODS + + %% ── MUX inputs from counters ───────────────────────────────── + CNT_U -->|"s_cnt_units (I0)"| MUX + CNT_T -->|"s_cnt_tens (I1)"| MUX + CNT_H -->|"s_cnt_hundreds (I2)"| MUX + CNT_K -->|"s_cnt_thousands (I3)"| MUX + + %% ── Segment decode ─────────────────────────────────────────── + MUX -->|"s_mux_out (BCD)"| DEC_SEG + DEC_SEG -->|"SEG"| SEGMENTS diff --git a/project_6/proj.mermaid.svg b/project_6/proj.mermaid.svg new file mode 100644 index 0000000..010cda8 --- /dev/null +++ b/project_6/proj.mermaid.svg @@ -0,0 +1 @@ +

📄 top_modul.vhd — glue signals defined here

📄 dec2.vhd — entity: dec_seg

📄 mux.vhd — entity: mux

📄 decoder_bottom.vhd — entity: decoder_an

📄 counter_2bit.vhd — entity: counter_2bit

📄 counter.vhd — entity: counter (reused 4x)

📄 divider_400Hz.vhd — entity: divider_400Hz

📄 divider.vhd — entity: divider

clk_1_Hz

s_ce_units (CE)

s_tc_units (TC->CE)

s_tc_units

s_tc_tens

CE

s_tc_units

s_tc_tens

s_tc_hundreds

CE

clk_400_Hz

s_cnt_2bit (SEL)

s_cnt_2bit (S)

ANODES

s_cnt_units (I0)

s_cnt_tens (I1)

s_cnt_hundreds (I2)

s_cnt_thousands (I3)

s_mux_out (BCD)

SEG

CLK

RST

START

SEGMENTS\nout

ANODS\nout

U_DIV\ndivider\n─────────────\nIN: CLK, RST\nOUT: CLK_1_Hz

U_DIV_400Hz\ndivider_400Hz\n─────────────\nIN: CLK, RST\nOUT: CLK_400_Hz

U_CNT_TOP\ncounter - Units\n─────────────\nIN: CLK, RST, CE\nOUT: COUNT_OUT, TC

U_CNT_BOTTOM\ncounter - Tens\n─────────────\nIN: CLK, RST, CE\nOUT: COUNT_OUT, TC

U_CNT_3\ncounter - Hundreds\n─────────────\nIN: CLK, RST, CE\nOUT: COUNT_OUT, TC

U_CNT_4\ncounter - Thousands\n─────────────\nIN: CLK, RST, CE\nOUT: COUNT_OUT, TC=open

U_CNT_2BIT\ncounter_2bit\n─────────────\nIN: CLK=clk_400Hz, RST\nOUT: COUNT_OUT 2-bit

U_DEC_ANODES\ndecoder_an\n─────────────\nIN: SEL 2-bit\nOUT: ANODES 4-bit

U_MUX\nmux 4x4-bit\n─────────────\nIN: I0,I1,I2,I3, S 2-bit\nOUT: Y 4-bit

U_DEC_SEG\ndec_seg\n─────────────\nIN: BCD 4-bit\nOUT: SEG 8-bit

s_ce_units\nclk_1_Hz AND START

CE for Hundreds\ns_tc_units AND s_tc_tens

CE for Thousands\ns_tc_units AND s_tc_tens\nAND s_tc_hundreds

 \ No newline at end of file diff --git a/project_6/proj2.mermaid b/project_6/proj2.mermaid new file mode 100644 index 0000000..c745c53 --- /dev/null +++ b/project_6/proj2.mermaid @@ -0,0 +1,82 @@ +flowchart LR + + %% ── Inputs ─────────────────────────────────────────────────── + CLK([CLK]) + RST([RST]) + START([START]) + + %% ── Outputs ────────────────────────────────────────────────── + SEGMENTS([SEGMENTS]) + ANODS([ANODS]) + + %% ── Clock dividers ─────────────────────────────────────────── + subgraph FILE_DIV["📄 divider.vhd"] + DIV["divider\n──────────\n100MHz → 1Hz pulse"] + end + + subgraph FILE_DIV400["📄 divider_400Hz.vhd"] + DIV400["divider_400Hz\n──────────\n100MHz → 400Hz pulse"] + end + + %% ── Glue in top_modul ──────────────────────────────────────── + AND_CE(["⚡ top_modul.vhd\ns_ce_units =\nclk_1_Hz AND START"]) + + %% ── BCD counter chain ──────────────────────────────────────── + subgraph FILE_CNT["📄 counter.vhd (entity reused 4×)"] + direction LR + CNT_U["U_CNT_TOP\n── Units ──\nCE=s_ce_units\nTC→s_tc_units"] + CNT_T["U_CNT_BOTTOM\n── Tens ──\nCE=s_tc_units\nTC→s_tc_tens"] + CNT_H["U_CNT_3\n── Hundreds ──\nCE=tc_u AND tc_t\nTC→s_tc_hundreds"] + CNT_K["U_CNT_4\n── Thousands ──\nCE=tc_u AND tc_t\n AND tc_h\nTC=open"] + + CNT_U -->|"s_tc_units"| CNT_T + CNT_T -->|"s_tc_tens"| CNT_H + CNT_H -->|"s_tc_hundreds"| CNT_K + end + + %% ── Display scan chain ─────────────────────────────────────── + subgraph FILE_CNT2["📄 counter_2bit.vhd"] + CNT2["counter_2bit\n──────────\nIN: clk_400Hz\nOUT: s_cnt_2bit"] + end + + subgraph FILE_DEC_AN["📄 decoder_bottom.vhd"] + DEC_AN["decoder_an\n──────────\nIN: SEL 2-bit\nOUT: ANODES 4-bit"] + end + + %% ── Mux + segment decode ───────────────────────────────────── + subgraph FILE_MUX["📄 mux.vhd"] + MUX["mux 4×4-bit\n──────────\nI0–I3: digit values\nS: s_cnt_2bit\nY: s_mux_out"] + end + + subgraph FILE_DEC_SEG["📄 dec2.vhd"] + DEC_SEG["dec_seg\n──────────\nBCD 4-bit\n→ SEG 8-bit"] + end + + %% ═══════════════════════════════════════════════════════ + %% WIRING + %% ═══════════════════════════════════════════════════════ + + %% Clock sources + CLK -->|"100 MHz"| DIV + CLK -->|"100 MHz"| DIV400 + + %% 1 Hz counting path + DIV -->|"clk_1_Hz"| AND_CE + START --> AND_CE + AND_CE -->|"s_ce_units"| CNT_U + + %% 400 Hz display scan path + DIV400 -->|"clk_400_Hz"| CNT2 + CNT2 -->|"s_cnt_2bit"| DEC_AN + CNT2 -->|"s_cnt_2bit (S)"| MUX + DEC_AN -->|"ANODES"| ANODS + + %% Counter digits into mux + CNT_U -->|"s_cnt_units (I0)"| MUX + CNT_T -->|"s_cnt_tens (I1)"| MUX + CNT_H -->|"s_cnt_hundreds (I2)"| MUX + CNT_K -->|"s_cnt_thousands (I3)"| MUX + + %% Segment output + MUX -->|"s_mux_out"| DEC_SEG + DEC_SEG -->|"SEG"| SEGMENTS diff --git a/project_6/proj2.mermaid.svg b/project_6/proj2.mermaid.svg new file mode 100644 index 0000000..efa2a0d --- /dev/null +++ b/project_6/proj2.mermaid.svg @@ -0,0 +1 @@ +

📄 dec2.vhd

📄 mux.vhd

📄 decoder_bottom.vhd

📄 counter_2bit.vhd

📄 counter.vhd (entity reused 4×)

📄 divider_400Hz.vhd

📄 divider.vhd

s_tc_units

s_tc_tens

s_tc_hundreds

100 MHz

100 MHz

clk_1_Hz

s_ce_units

clk_400_Hz

s_cnt_2bit

s_cnt_2bit (S)

ANODES

s_cnt_units (I0)

s_cnt_tens (I1)

s_cnt_hundreds (I2)

s_cnt_thousands (I3)

s_mux_out

SEG

CLK

RST

START

SEGMENTS

ANODS

divider\n──────────\n100MHz → 1Hz pulse

divider_400Hz\n──────────\n100MHz → 400Hz pulse

⚡ top_modul.vhd\ns_ce_units =\nclk_1_Hz AND START

U_CNT_TOP\n── Units ──\nCE=s_ce_units\nTC→s_tc_units

U_CNT_BOTTOM\n── Tens ──\nCE=s_tc_units\nTC→s_tc_tens

U_CNT_3\n── Hundreds ──\nCE=tc_u AND tc_t\nTC→s_tc_hundreds

U_CNT_4\n── Thousands ──\nCE=tc_u AND tc_t\n AND tc_h\nTC=open

counter_2bit\n──────────\nIN: clk_400Hz\nOUT: s_cnt_2bit

decoder_an\n──────────\nIN: SEL 2-bit\nOUT: ANODES 4-bit

mux 4×4-bit\n──────────\nI0–I3: digit values\nS: s_cnt_2bit\nY: s_mux_out

dec_seg\n──────────\nBCD 4-bit\n→ SEG 8-bit

 \ No newline at end of file diff --git a/project_7_hodiny/project_6.srcs/constrs_1/imports/Downloads/Basys-3-Master.xdc b/project_7_hodiny/project_6.srcs/constrs_1/imports/Downloads/Basys-3-Master.xdc new file mode 100644 index 0000000..802c363 --- /dev/null +++ b/project_7_hodiny/project_6.srcs/constrs_1/imports/Downloads/Basys-3-Master.xdc @@ -0,0 +1,158 @@ +## This file is a general .xdc for the Basys3 rev B board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal +set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports CLK] +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK] + + +## Switches +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {RST}] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {START}] +#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {sw[2]}] +#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports {sw[3]}] +#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {sw[4]}] +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports {sw[5]}] +#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports {sw[6]}] +#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports {sw[7]}] +#set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports {sw[8]}] +#set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports {sw[9]}] +#set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports {sw[10]}] +#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {sw[11]}] +#set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports {sw[12]}] +#set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports {sw[13]}] +#set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {sw[14]}] +#set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {sw[15]}] + + +## LEDs +#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports {led[0]}] +#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports {led[1]}] +#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports {led[2]}] +#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports {led[3]}] +#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports {led[4]}] +#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports {led[5]}] +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports {led[6]}] +#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports {led[7]}] +#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports {led[8]}] +#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports {led[9]}] +#set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports {led[10]}] +#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports {led[11]}] +#set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports {led[12]}] +#set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports {led[13]}] +#set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports {led[14]}] +#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports {led[15]}] + + +##7 Segment Display +set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[0]}] +set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[1]}] +set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[2]}] +set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[3]}] +set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[4]}] +set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[5]}] +set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[6]}] + +set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports {SEGMENTS[7]}] + +set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports {ANODS[0]}] +set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports {ANODS[1]}] +set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports {ANODS[2]}] +set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports {ANODS[3]}] + +##Buttons +#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports btnC] +#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports btnU] +#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports btnL] +#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports btnR] +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports btnD] + + +##Pmod Header JA +#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports {JA[0]}];#Sch name = JA1 +#set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports {JA[1]}];#Sch name = JA2 +#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports {JA[2]}];#Sch name = JA3 +#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports {JA[3]}];#Sch name = JA4 +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports {JA[4]}];#Sch name = JA7 +#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports {JA[5]}];#Sch name = JA8 +#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports {JA[6]}];#Sch name = JA9 +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports {JA[7]}];#Sch name = JA10 + +##Pmod Header JB +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports {JB[0]}];#Sch name = JB1 +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports {JB[1]}];#Sch name = JB2 +#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports {JB[2]}];#Sch name = JB3 +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports {JB[3]}];#Sch name = JB4 +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports {JB[4]}];#Sch name = JB7 +#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports {JB[5]}];#Sch name = JB8 +#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports {JB[6]}];#Sch name = JB9 +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports {JB[7]}];#Sch name = JB10 + +##Pmod Header JC +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports {JC[0]}];#Sch name = JC1 +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports {JC[1]}];#Sch name = JC2 +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports {JC[2]}];#Sch name = JC3 +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports {JC[3]}];#Sch name = JC4 +#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports {JC[4]}];#Sch name = JC7 +#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports {JC[5]}];#Sch name = JC8 +#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports {JC[6]}];#Sch name = JC9 +#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports {JC[7]}];#Sch name = JC10 + +##Pmod Header JXADC +#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[0]}];#Sch name = XA1_P +#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[1]}];#Sch name = XA2_P +#set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[2]}];#Sch name = XA3_P +#set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[3]}];#Sch name = XA4_P +#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[4]}];#Sch name = XA1_N +#set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[5]}];#Sch name = XA2_N +#set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[6]}];#Sch name = XA3_N +#set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[7]}];#Sch name = XA4_N + + +##VGA Connector +#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[0]}] +#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[1]}] +#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[2]}] +#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[3]}] +#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[0]}] +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[1]}] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[2]}] +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[3]}] +#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[0]}] +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[1]}] +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[2]}] +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[3]}] +#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports Hsync] +#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports Vsync] + + +##USB-RS232 Interface +#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports RsRx] +#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports RsTx] + + +##USB HID (PS/2) +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Clk] +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Data] + + +##Quad SPI Flash +##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the +##STARTUPE2 primitive. +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[0]}] +#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[1]}] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[2]}] +#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[3]}] +#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports QspiCSn] + + +## Configuration options, can be used for all designs +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] + +## SPI configuration mode options for QSPI boot, can be used for all designs +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] diff --git a/project_7_hodiny/project_6.srcs/sources_1/new/counter_2bit.vhd b/project_7_hodiny/project_6.srcs/sources_1/new/counter_2bit.vhd new file mode 100644 index 0000000..ef0218f --- /dev/null +++ b/project_7_hodiny/project_6.srcs/sources_1/new/counter_2bit.vhd @@ -0,0 +1,55 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09.03.2026 15:32:13 +-- Design Name: +-- Module Name: counter_2bit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity counter_2bit is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + COUNT_OUT : out STD_LOGIC_VECTOR (1 downto 0)); +end counter_2bit; + +architecture Behavioral of counter_2bit is + + signal s_cnt : STD_LOGIC_VECTOR(1 downto 0) := "00"; +begin + process(CLK, RST) + begin + if RST = '1' then + s_cnt <= "00"; + elsif rising_edge(CLK) then + s_cnt <= s_cnt + 1; + end if; + end process; + COUNT_OUT <= s_cnt; + +end Behavioral; diff --git a/project_7_hodiny/project_6.srcs/sources_1/new/counters_hours/counter_hour_tens.vhd b/project_7_hodiny/project_6.srcs/sources_1/new/counters_hours/counter_hour_tens.vhd new file mode 100644 index 0000000..666133f --- /dev/null +++ b/project_7_hodiny/project_6.srcs/sources_1/new/counters_hours/counter_hour_tens.vhd @@ -0,0 +1,42 @@ + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity counter is + Port ( CLK : in STD_LOGIC; + DIN : in STD_LOGIC_VECTOR (3 downto 0); -- teraz nas nezaujima + PE : in STD_LOGIC; -- teraz nas nezaujima + CE : in STD_LOGIC; + RST : in STD_LOGIC; + TC : out STD_LOGIC; + COUNT_OUT : out STD_LOGIC_VECTOR (2 downto 0)); +end counter; + +architecture Behavioral of counter is + -- Internal signal to keep track of the current number + signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000"; +begin + + -- Main counting logic + process(CLK) + begin + if rising_edge(CLK) then + if RST = '1' then + s_cnt <= "0000"; + elsif CE = '1' then + -- toto preto, lebo su to desiatky hodin, 24 hod je max, takze + -- iba 0 - 2 + if s_cnt = "0010" then + s_cnt <= "0000"; -- Reset to 0 + else + s_cnt <= s_cnt + 1; + end if; + end if; + end if; + end process; + + -- Drive the output ports + COUNT_OUT <= s_cnt; + +end Behavioral; diff --git a/project_7_hodiny/project_6.srcs/sources_1/new/counters_hours/counter_minute_tens.vhd b/project_7_hodiny/project_6.srcs/sources_1/new/counters_hours/counter_minute_tens.vhd new file mode 100644 index 0000000..5fe2339 --- /dev/null +++ b/project_7_hodiny/project_6.srcs/sources_1/new/counters_hours/counter_minute_tens.vhd @@ -0,0 +1,37 @@ + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity counter is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + CE : in STD_LOGIC; + TC : out STD_LOGIC; + COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)); +end counter; + +architecture Behavioral of counter is + -- Internal signal to keep track of the current number + signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000"; +begin + + -- Main counting logic + process(CLK) + begin + if rising_edge(CLK) then + if RST = '1' then + s_cnt <= "0000"; + elsif CE = '1' then + if s_cnt = "0110" then -- If we are at 6 + s_cnt <= "0000"; -- Reset to 0 + else + s_cnt <= s_cnt + 1; -- Increment + end if; + end if; + end if; + end process; + + COUNT_OUT <= s_cnt; + +end Behavioral; diff --git a/project_7_hodiny/project_6.srcs/sources_1/new/counters_hours/counter_ones.vhd b/project_7_hodiny/project_6.srcs/sources_1/new/counters_hours/counter_ones.vhd new file mode 100644 index 0000000..40a043c --- /dev/null +++ b/project_7_hodiny/project_6.srcs/sources_1/new/counters_hours/counter_ones.vhd @@ -0,0 +1,37 @@ + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity counter is + Port ( CLK : in STD_LOGIC; + CE : in STD_LOGIC; + RST : in STD_LOGIC; + TC : out STD_LOGIC; + COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)); +end counter; + +architecture Behavioral of counter is + -- Internal signal to keep track of the current number + signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000"; +begin + + process(CLK) + begin + if rising_edge(CLK) then + if RST = '1' then + s_cnt <= "0000"; + elsif CE = '1' then + if s_cnt = "1001" then -- If we are at 9 + s_cnt <= "0000"; -- Reset to 0 + else + s_cnt <= s_cnt + 1; + end if; + end if; + end if; + end process; + + COUNT_OUT <= s_cnt; + +end Behavioral; diff --git a/project_7_hodiny/project_6.srcs/sources_1/new/dec2.vhd b/project_7_hodiny/project_6.srcs/sources_1/new/dec2.vhd new file mode 100644 index 0000000..4c37837 --- /dev/null +++ b/project_7_hodiny/project_6.srcs/sources_1/new/dec2.vhd @@ -0,0 +1,58 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09.03.2026 15:54:24 +-- Design Name: +-- Module Name: dec_seg - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity dec_seg is + Port ( BCD : in STD_LOGIC_VECTOR (3 downto 0); + SEG : out STD_LOGIC_VECTOR (7 downto 0)); +end dec_seg; + +architecture Behavioral of dec_seg is + +begin + -- Konverzia BCD na 7-segment (ABCDEFG + DP) + -- Formt: "ABCDEFG DP" + + with bcd select + seg <= "11000000" when "0000", -- 0 + "11111001" when "0001", -- 1 + "10100100" when "0010", -- 2 + "10110000" when "0011", -- 3 + "10011001" when "0100", -- 4 + "10010010" when "0101", -- 5 + "10000010" when "0110", -- 6 + "11111000" when "0111", -- 7 + "10000000" when "1000", -- 8 + "10010000" when "1001", -- 9 + "11111111" when others; -- off + +end Behavioral; diff --git a/project_7_hodiny/project_6.srcs/sources_1/new/decoder_bottom.vhd b/project_7_hodiny/project_6.srcs/sources_1/new/decoder_bottom.vhd new file mode 100644 index 0000000..886103e --- /dev/null +++ b/project_7_hodiny/project_6.srcs/sources_1/new/decoder_bottom.vhd @@ -0,0 +1,50 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09.03.2026 15:39:11 +-- Design Name: +-- Module Name: decoder_bottom - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity decoder_an is + Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0); + ANODES : out STD_LOGIC_VECTOR (3 downto 0)); +end decoder_an; + +architecture Behavioral of decoder_an is + +begin + with SEL select + ANODES <= "1110" when "00", + "1101" when "01", + "1011" when "10", + "0111" when "11", + "1111" when others; + +end Behavioral; diff --git a/project_7_hodiny/project_6.srcs/sources_1/new/divider.vhd b/project_7_hodiny/project_6.srcs/sources_1/new/divider.vhd new file mode 100644 index 0000000..ab00d12 --- /dev/null +++ b/project_7_hodiny/project_6.srcs/sources_1/new/divider.vhd @@ -0,0 +1,60 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09.03.2026 14:43:21 +-- Design Name: +-- Module Name: divider - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity divider is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + CLK_1_Hz : out STD_LOGIC); +end divider; + +architecture Behavioral of divider is + -- 27 bits is enough for 100 million + signal s_cnt : STD_LOGIC_VECTOR(26 downto 0) := (others => '0'); +begin + process(CLK) + begin + if rising_edge(CLK) then + if RST = '1' then + s_cnt <= (others => '0'); + CLK_1_Hz <= '0'; + elsif s_cnt = 99_999_999 then + s_cnt <= (others => '0'); + CLK_1_Hz <= '1'; -- The pulse + else + s_cnt <= s_cnt + 1; + CLK_1_Hz <= '0'; + end if; + end if; + end process; +end Behavioral; diff --git a/project_7_hodiny/project_6.srcs/sources_1/new/divider_400Hz.vhd b/project_7_hodiny/project_6.srcs/sources_1/new/divider_400Hz.vhd new file mode 100644 index 0000000..4c5706d --- /dev/null +++ b/project_7_hodiny/project_6.srcs/sources_1/new/divider_400Hz.vhd @@ -0,0 +1,60 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09.03.2026 14:49:47 +-- Design Name: +-- Module Name: divider_400Hz - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity divider_400Hz is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + CLK_400_Hz : out STD_LOGIC); +end divider_400Hz; + +architecture Behavioral of divider_400Hz is + -- 18 bits is enough for 250,000 + signal s_cnt : STD_LOGIC_VECTOR(17 downto 0) := (others => '0'); +begin + process(CLK) + begin + if rising_edge(CLK) then + if RST = '1' then + s_cnt <= (others => '0'); + CLK_400_Hz <= '0'; + elsif s_cnt = 249_999 then + s_cnt <= (others => '0'); + CLK_400_Hz <= '1'; + else + s_cnt <= s_cnt + 1; + CLK_400_Hz <= '0'; + end if; + end if; + end process; +end Behavioral; diff --git a/project_7_hodiny/project_6.srcs/sources_1/new/mux.vhd b/project_7_hodiny/project_6.srcs/sources_1/new/mux.vhd new file mode 100644 index 0000000..cc2d848 --- /dev/null +++ b/project_7_hodiny/project_6.srcs/sources_1/new/mux.vhd @@ -0,0 +1,53 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09.03.2026 15:47:51 +-- Design Name: +-- Module Name: mux - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity mux is + Port ( I0 : in STD_LOGIC_VECTOR (3 downto 0); + I1 : in STD_LOGIC_VECTOR (3 downto 0); + I2 : in STD_LOGIC_VECTOR (3 downto 0); + I3 : in STD_LOGIC_VECTOR (3 downto 0); + S : in STD_LOGIC_VECTOR (1 downto 0); + Y : out STD_LOGIC_VECTOR (3 downto 0)); +end mux; + +architecture Behavioral of mux is + +begin + with S select + Y <= I0 when "00", + I1 when "01", + I2 when "10", + I3 when "11", + "0000" when others; + +end Behavioral; diff --git a/project_7_hodiny/project_6.srcs/sources_1/new/top_modul.vhd b/project_7_hodiny/project_6.srcs/sources_1/new/top_modul.vhd new file mode 100644 index 0000000..8db55a8 --- /dev/null +++ b/project_7_hodiny/project_6.srcs/sources_1/new/top_modul.vhd @@ -0,0 +1,182 @@ + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity top_modul is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + START : in STD_LOGIC; + SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0); + ANODS : out STD_LOGIC_VECTOR (3 downto 0)); +end top_modul; + +architecture Behavioral of top_modul is + + component divider is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + CLK_1_Hz : out STD_LOGIC); -- This will be our enable pulse + end component; + + component divider_400Hz is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + CLK_400_Hz : out STD_LOGIC); -- This will be our enable pulse + end component; + + component cnt_0_9 is + Port ( CLK : in STD_LOGIC; + CE : in STD_LOGIC; + RST : in STD_LOGIC; + TC : out STD_LOGIC; + COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)); + end component; + + component cnt_0_5 is + Port ( CLK : in STD_LOGIC; + CE : in STD_LOGIC; + RST : in STD_LOGIC; + TC : out STD_LOGIC; + COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)); + end component; + + component cnt_0_2 is + Port ( CLK : in STD_LOGIC; + CE : in STD_LOGIC; + RST : in STD_LOGIC; + TC : out STD_LOGIC; + COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)); + end component; + + component counter_2bit is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + COUNT_OUT : out STD_LOGIC_VECTOR (1 downto 0)); + end component; + + component decoder_an is + Port ( SEL : in STD_LOGIC_VECTOR (1 downto 0); + ANODES : out STD_LOGIC_VECTOR (3 downto 0)); + end component; + + component mux is + Port ( I0 : in STD_LOGIC_VECTOR (3 downto 0); + I1 : in STD_LOGIC_VECTOR (3 downto 0); + I2 : in STD_LOGIC_VECTOR (3 downto 0); + I3 : in STD_LOGIC_VECTOR (3 downto 0); + S : in STD_LOGIC_VECTOR (1 downto 0); + Y : out STD_LOGIC_VECTOR (3 downto 0)); + end component; + + component dec_seg is + Port ( bcd : in STD_LOGIC_VECTOR (3 downto 0); + seg : out STD_LOGIC_VECTOR (7 downto 0)); + end component; + + signal clk_1_Hz : std_logic; + signal clk_400_Hz : std_logic; + + -- Internal signals to connect the counters + signal sig_m_units : std_logic_vector(3 downto 0); + signal sig_m_tens : std_logic_vector(3 downto 0); + signal sig_h_units : std_logic_vector(3 downto 0); + signal sig_h_tens : std_logic_vector(3 downto 0); + -- Carry signals (TC) + signal tc_mu, tc_mt, tc_hu : std_logic; + -- Reset for hours (to handle the 24 reset) + signal hour_reset : std_logic; + + signal s_cnt_2bit : std_logic_vector(1 downto 0); + signal s_mux_out : std_logic_vector(3 downto 0); + +begin + + U_DIV : divider + port map ( + CLK => CLK, + RST => RST, + CLK_1_Hz => clk_1_Hz + ); + + + U_DIV_400Hz : divider_400Hz + port map ( + CLK => CLK, + RST => RST, + CLK_400_Hz => clk_400_Hz + ); + + -- MINUTES UNITS (0-9) + U_CNT_MIN_UNITS : cnt_0_9 + port map ( + CLK => CLK, + RST => RST, + CE => clk_1_Hz and START, + TC => tc_mu, + COUNT_OUT => sig_m_units + ); + + -- MINUTES TENS (0-5) + U_CNT_MIN_TENS : cnt_0_5 + port map ( + CLK => CLK, + RST => RST, + CE => tc_mu, + TC => tc_mt, + COUNT_OUT => sig_m_tens + ); + + -- Logic to reset hours at 24:00 + hour_reset <= '1' when (RST = '1' or (sig_h_tens = "0010" and sig_h_units = "0100")) else '0'; + + -- HOURS UNITS (0-9) + U_CNT_HOR_UNITS : cnt_0_9 + port map ( + CLK => CLK, + RST => hour_reset, + CE => tc_mt, + TC => tc_hu, + COUNT_OUT => sig_h_units + ); + + -- HOURS TENS (0-2) + U_CNT_HOR_TENS : cnt_0_2 + port map ( + CLK => CLK, + RST => hour_reset, + CE => tc_hu, + TC => open, + COUNT_OUT => sig_h_tens + ); + + U_CNT_2BIT : counter_2bit + port map ( + CLK => clk_400_Hz, + RST => RST, + COUNT_OUT => s_cnt_2bit + ); + + U_DEC_ANODES : decoder_an + port map ( + SEL => s_cnt_2bit, -- 2-bitov signl + ANODES => ANODS -- Vstupn port top modulu + ); + + U_MUX : mux + port map ( + I0 => sig_m_units, -- Corrected signal names + I1 => sig_m_tens, + I2 => sig_h_units, + I3 => sig_h_tens, + S => s_cnt_2bit, + Y => s_mux_out + ); + + U_DEC_SEG : dec_seg + port map ( + BCD => s_mux_out, + SEG => SEGMENTS + ); + +end Behavioral;