clock

project_6/proj.mermaid

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+flowchart TD
+
+    %% ── External ports ──────────────────────────────────────────
+    CLK([CLK])
+    RST([RST])
+    START([START])
+    SEGMENTS([SEGMENTS\nout])
+    ANODS([ANODS\nout])
+
+    %% ════════════════════════════════════════════════════════════
+    %% FILE: divider.vhd
+    %% ════════════════════════════════════════════════════════════
+    subgraph FILE_DIV["📄 divider.vhd — entity: divider"]
+        direction TB
+        DIV["U_DIV\ndivider\n─────────────\nIN:  CLK, RST\nOUT: CLK_1_Hz"]
+    end
+
+    %% ════════════════════════════════════════════════════════════
+    %% FILE: divider_400Hz.vhd
+    %% ════════════════════════════════════════════════════════════
+    subgraph FILE_DIV400["📄 divider_400Hz.vhd — entity: divider_400Hz"]
+        direction TB
+        DIV400["U_DIV_400Hz\ndivider_400Hz\n─────────────\nIN:  CLK, RST\nOUT: CLK_400_Hz"]
+    end
+
+    %% ════════════════════════════════════════════════════════════
+    %% FILE: counter.vhd
+    %% ════════════════════════════════════════════════════════════
+    subgraph FILE_CNT["📄 counter.vhd — entity: counter  (reused 4x)"]
+        direction TB
+        CNT_U["U_CNT_TOP\ncounter - Units\n─────────────\nIN:  CLK, RST, CE\nOUT: COUNT_OUT, TC"]
+        CNT_T["U_CNT_BOTTOM\ncounter - Tens\n─────────────\nIN:  CLK, RST, CE\nOUT: COUNT_OUT, TC"]
+        CNT_H["U_CNT_3\ncounter - Hundreds\n─────────────\nIN:  CLK, RST, CE\nOUT: COUNT_OUT, TC"]
+        CNT_K["U_CNT_4\ncounter - Thousands\n─────────────\nIN:  CLK, RST, CE\nOUT: COUNT_OUT, TC=open"]
+    end
+
+    %% ════════════════════════════════════════════════════════════
+    %% FILE: counter_2bit.vhd
+    %% ════════════════════════════════════════════════════════════
+    subgraph FILE_CNT2["📄 counter_2bit.vhd — entity: counter_2bit"]
+        direction TB
+        CNT2["U_CNT_2BIT\ncounter_2bit\n─────────────\nIN:  CLK=clk_400Hz, RST\nOUT: COUNT_OUT 2-bit"]
+    end
+
+    %% ════════════════════════════════════════════════════════════
+    %% FILE: decoder_bottom.vhd
+    %% ════════════════════════════════════════════════════════════
+    subgraph FILE_DEC_AN["📄 decoder_bottom.vhd — entity: decoder_an"]
+        direction TB
+        DEC_AN["U_DEC_ANODES\ndecoder_an\n─────────────\nIN:  SEL 2-bit\nOUT: ANODES 4-bit"]
+    end
+
+    %% ════════════════════════════════════════════════════════════
+    %% FILE: mux.vhd
+    %% ════════════════════════════════════════════════════════════
+    subgraph FILE_MUX["📄 mux.vhd — entity: mux"]
+        direction TB
+        MUX["U_MUX\nmux 4x4-bit\n─────────────\nIN:  I0,I1,I2,I3, S 2-bit\nOUT: Y 4-bit"]
+    end
+
+    %% ════════════════════════════════════════════════════════════
+    %% FILE: dec2.vhd
+    %% ════════════════════════════════════════════════════════════
+    subgraph FILE_DEC_SEG["📄 dec2.vhd — entity: dec_seg"]
+        direction TB
+        DEC_SEG["U_DEC_SEG\ndec_seg\n─────────────\nIN:  BCD 4-bit\nOUT: SEG 8-bit"]
+    end
+
+    %% ════════════════════════════════════════════════════════════
+    %% top_modul.vhd — glue logic defined directly in this file
+    %% ════════════════════════════════════════════════════════════
+    subgraph FILE_TOP["📄 top_modul.vhd — glue signals defined here"]
+        direction TB
+        AND_START{"s_ce_units\nclk_1_Hz AND START"}
+        AND2{"CE for Hundreds\ns_tc_units AND s_tc_tens"}
+        AND3{"CE for Thousands\ns_tc_units AND s_tc_tens\nAND s_tc_hundreds"}
+    end
+
+    %% ── Clock / Reset wiring ─────────────────────────────────────
+    CLK --> DIV
+    RST --> DIV
+    CLK --> DIV400
+    RST --> DIV400
+    CLK --> CNT_U & CNT_T & CNT_H & CNT_K
+    RST --> CNT_U & CNT_T & CNT_H & CNT_K & CNT2
+
+    %% ── 1 Hz chain ───────────────────────────────────────────────
+    DIV  -->|"clk_1_Hz"| AND_START
+    START --> AND_START
+    AND_START -->|"s_ce_units (CE)"| CNT_U
+
+    %% ── BCD carry chain ──────────────────────────────────────────
+    CNT_U -->|"s_tc_units (TC->CE)"| CNT_T
+    CNT_U -->|"s_tc_units"| AND2
+    CNT_T -->|"s_tc_tens"| AND2
+    AND2  -->|"CE"| CNT_H
+
+    CNT_U -->|"s_tc_units"| AND3
+    CNT_T -->|"s_tc_tens"| AND3
+    CNT_H -->|"s_tc_hundreds"| AND3
+    AND3  -->|"CE"| CNT_K
+
+    %% ── 400 Hz display scan ──────────────────────────────────────
+    DIV400 -->|"clk_400_Hz"| CNT2
+    CNT2   -->|"s_cnt_2bit (SEL)"| DEC_AN
+    CNT2   -->|"s_cnt_2bit (S)"| MUX
+    DEC_AN -->|"ANODES"| ANODS
+
+    %% ── MUX inputs from counters ─────────────────────────────────
+    CNT_U -->|"s_cnt_units (I0)"| MUX
+    CNT_T -->|"s_cnt_tens (I1)"| MUX
+    CNT_H -->|"s_cnt_hundreds (I2)"| MUX
+    CNT_K -->|"s_cnt_thousands (I3)"| MUX
+
+    %% ── Segment decode ───────────────────────────────────────────
+    MUX     -->|"s_mux_out (BCD)"| DEC_SEG
+    DEC_SEG -->|"SEG"| SEGMENTS

project_6/proj2.mermaid

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+flowchart LR
+
+    %% ── Inputs ───────────────────────────────────────────────────
+    CLK([CLK])
+    RST([RST])
+    START([START])
+
+    %% ── Outputs ──────────────────────────────────────────────────
+    SEGMENTS([SEGMENTS])
+    ANODS([ANODS])
+
+    %% ── Clock dividers ───────────────────────────────────────────
+    subgraph FILE_DIV["📄 divider.vhd"]
+        DIV["divider\n──────────\n100MHz → 1Hz pulse"]
+    end
+
+    subgraph FILE_DIV400["📄 divider_400Hz.vhd"]
+        DIV400["divider_400Hz\n──────────\n100MHz → 400Hz pulse"]
+    end
+
+    %% ── Glue in top_modul ────────────────────────────────────────
+    AND_CE(["⚡ top_modul.vhd\ns_ce_units =\nclk_1_Hz AND START"])
+
+    %% ── BCD counter chain ────────────────────────────────────────
+    subgraph FILE_CNT["📄 counter.vhd   (entity reused 4×)"]
+        direction LR
+        CNT_U["U_CNT_TOP\n── Units ──\nCE=s_ce_units\nTC→s_tc_units"]
+        CNT_T["U_CNT_BOTTOM\n── Tens ──\nCE=s_tc_units\nTC→s_tc_tens"]
+        CNT_H["U_CNT_3\n── Hundreds ──\nCE=tc_u AND tc_t\nTC→s_tc_hundreds"]
+        CNT_K["U_CNT_4\n── Thousands ──\nCE=tc_u AND tc_t\n    AND tc_h\nTC=open"]
+
+        CNT_U -->|"s_tc_units"| CNT_T
+        CNT_T -->|"s_tc_tens"| CNT_H
+        CNT_H -->|"s_tc_hundreds"| CNT_K
+    end
+
+    %% ── Display scan chain ───────────────────────────────────────
+    subgraph FILE_CNT2["📄 counter_2bit.vhd"]
+        CNT2["counter_2bit\n──────────\nIN: clk_400Hz\nOUT: s_cnt_2bit"]
+    end
+
+    subgraph FILE_DEC_AN["📄 decoder_bottom.vhd"]
+        DEC_AN["decoder_an\n──────────\nIN: SEL 2-bit\nOUT: ANODES 4-bit"]
+    end
+
+    %% ── Mux + segment decode ─────────────────────────────────────
+    subgraph FILE_MUX["📄 mux.vhd"]
+        MUX["mux  4×4-bit\n──────────\nI0–I3: digit values\nS: s_cnt_2bit\nY: s_mux_out"]
+    end
+
+    subgraph FILE_DEC_SEG["📄 dec2.vhd"]
+        DEC_SEG["dec_seg\n──────────\nBCD 4-bit\n→ SEG 8-bit"]
+    end
+
+    %% ═══════════════════════════════════════════════════════
+    %% WIRING
+    %% ═══════════════════════════════════════════════════════
+
+    %% Clock sources
+    CLK -->|"100 MHz"| DIV
+    CLK -->|"100 MHz"| DIV400
+
+    %% 1 Hz counting path
+    DIV  -->|"clk_1_Hz"| AND_CE
+    START --> AND_CE
+    AND_CE -->|"s_ce_units"| CNT_U
+
+    %% 400 Hz display scan path
+    DIV400 -->|"clk_400_Hz"| CNT2
+    CNT2   -->|"s_cnt_2bit"| DEC_AN
+    CNT2   -->|"s_cnt_2bit (S)"| MUX
+    DEC_AN -->|"ANODES"| ANODS
+
+    %% Counter digits into mux
+    CNT_U -->|"s_cnt_units  (I0)"| MUX
+    CNT_T -->|"s_cnt_tens   (I1)"| MUX
+    CNT_H -->|"s_cnt_hundreds (I2)"| MUX
+    CNT_K -->|"s_cnt_thousands (I3)"| MUX
+
+    %% Segment output
+    MUX     -->|"s_mux_out"| DEC_SEG
+    DEC_SEG -->|"SEG"| SEGMENTS