robime dalsie zadanie
This commit is contained in:
filipriec skolsky PC
47
project_5/project_5.srcs/sources_1/new/counter.vhd
Normal file
47
project_5/project_5.srcs/sources_1/new/counter.vhd
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@@ -0,0 +1,47 @@
|
|||||||
|
----------------------------------------------------------------------------------
|
||||||
|
-- Company:
|
||||||
|
-- Engineer:
|
||||||
|
--
|
||||||
|
-- Create Date: 09.03.2026 15:14:35
|
||||||
|
-- Design Name:
|
||||||
|
-- Module Name: counter - Behavioral
|
||||||
|
-- Project Name:
|
||||||
|
-- Target Devices:
|
||||||
|
-- Tool Versions:
|
||||||
|
-- Description:
|
||||||
|
--
|
||||||
|
-- Dependencies:
|
||||||
|
--
|
||||||
|
-- Revision:
|
||||||
|
-- Revision 0.01 - File Created
|
||||||
|
-- Additional Comments:
|
||||||
|
--
|
||||||
|
----------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
|
||||||
|
library IEEE;
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||||||
|
use IEEE.STD_LOGIC_1164.ALL;
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||||||
|
|
||||||
|
-- Uncomment the following library declaration if using
|
||||||
|
-- arithmetic functions with Signed or Unsigned values
|
||||||
|
--use IEEE.NUMERIC_STD.ALL;
|
||||||
|
|
||||||
|
-- Uncomment the following library declaration if instantiating
|
||||||
|
-- any Xilinx leaf cells in this code.
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||||||
|
--library UNISIM;
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||||||
|
--use UNISIM.VComponents.all;
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||||||
|
|
||||||
|
entity counter is
|
||||||
|
Port ( CLK : in STD_LOGIC;
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||||||
|
RST : in STD_LOGIC;
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||||||
|
CE : in STD_LOGIC;
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||||||
|
TC : out STD_LOGIC;
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||||||
|
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
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||||||
|
end counter;
|
||||||
|
|
||||||
|
architecture Behavioral of counter is
|
||||||
|
|
||||||
|
begin
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||||||
|
|
||||||
|
|
||||||
|
end Behavioral;
|
||||||
60
project_5/project_5.srcs/sources_1/new/divider.vhd
Normal file
60
project_5/project_5.srcs/sources_1/new/divider.vhd
Normal file
@@ -0,0 +1,60 @@
|
|||||||
|
----------------------------------------------------------------------------------
|
||||||
|
-- Company:
|
||||||
|
-- Engineer:
|
||||||
|
--
|
||||||
|
-- Create Date: 09.03.2026 14:43:21
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||||||
|
-- Design Name:
|
||||||
|
-- Module Name: divider - Behavioral
|
||||||
|
-- Project Name:
|
||||||
|
-- Target Devices:
|
||||||
|
-- Tool Versions:
|
||||||
|
-- Description:
|
||||||
|
--
|
||||||
|
-- Dependencies:
|
||||||
|
--
|
||||||
|
-- Revision:
|
||||||
|
-- Revision 0.01 - File Created
|
||||||
|
-- Additional Comments:
|
||||||
|
--
|
||||||
|
----------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||||
|
|
||||||
|
-- Uncomment the following library declaration if using
|
||||||
|
-- arithmetic functions with Signed or Unsigned values
|
||||||
|
--use IEEE.NUMERIC_STD.ALL;
|
||||||
|
|
||||||
|
-- Uncomment the following library declaration if instantiating
|
||||||
|
-- any Xilinx leaf cells in this code.
|
||||||
|
--library UNISIM;
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|
--use UNISIM.VComponents.all;
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||||||
|
|
||||||
|
entity divider is
|
||||||
|
Port ( CLK : in STD_LOGIC;
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|
RST : in STD_LOGIC;
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||||||
|
CLK_1_Hz : out STD_LOGIC);
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||||||
|
end divider;
|
||||||
|
|
||||||
|
architecture Behavioral of divider is
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|
-- 27 bits is enough for 100 million
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|
signal s_cnt : STD_LOGIC_VECTOR(26 downto 0) := (others => '0');
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||||||
|
begin
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||||||
|
process(CLK)
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||||||
|
begin
|
||||||
|
if rising_edge(CLK) then
|
||||||
|
if RST = '1' then
|
||||||
|
s_cnt <= (others => '0');
|
||||||
|
CLK_1_Hz <= '0';
|
||||||
|
elsif s_cnt = 99_999_999 then
|
||||||
|
s_cnt <= (others => '0');
|
||||||
|
CLK_1_Hz <= '1'; -- The pulse
|
||||||
|
else
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||||||
|
s_cnt <= s_cnt + 1;
|
||||||
|
CLK_1_Hz <= '0';
|
||||||
|
end if;
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||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
end Behavioral;
|
||||||
60
project_5/project_5.srcs/sources_1/new/divider_400Hz.vhd
Normal file
60
project_5/project_5.srcs/sources_1/new/divider_400Hz.vhd
Normal file
@@ -0,0 +1,60 @@
|
|||||||
|
----------------------------------------------------------------------------------
|
||||||
|
-- Company:
|
||||||
|
-- Engineer:
|
||||||
|
--
|
||||||
|
-- Create Date: 09.03.2026 14:49:47
|
||||||
|
-- Design Name:
|
||||||
|
-- Module Name: divider_400Hz - Behavioral
|
||||||
|
-- Project Name:
|
||||||
|
-- Target Devices:
|
||||||
|
-- Tool Versions:
|
||||||
|
-- Description:
|
||||||
|
--
|
||||||
|
-- Dependencies:
|
||||||
|
--
|
||||||
|
-- Revision:
|
||||||
|
-- Revision 0.01 - File Created
|
||||||
|
-- Additional Comments:
|
||||||
|
--
|
||||||
|
----------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||||
|
|
||||||
|
-- Uncomment the following library declaration if using
|
||||||
|
-- arithmetic functions with Signed or Unsigned values
|
||||||
|
--use IEEE.NUMERIC_STD.ALL;
|
||||||
|
|
||||||
|
-- Uncomment the following library declaration if instantiating
|
||||||
|
-- any Xilinx leaf cells in this code.
|
||||||
|
--library UNISIM;
|
||||||
|
--use UNISIM.VComponents.all;
|
||||||
|
|
||||||
|
entity divider_400Hz is
|
||||||
|
Port ( CLK : in STD_LOGIC;
|
||||||
|
RST : in STD_LOGIC;
|
||||||
|
CLK_400_Hz : out STD_LOGIC);
|
||||||
|
end divider_400Hz;
|
||||||
|
|
||||||
|
architecture Behavioral of divider_400Hz is
|
||||||
|
-- 18 bits is enough for 250,000
|
||||||
|
signal s_cnt : STD_LOGIC_VECTOR(17 downto 0) := (others => '0');
|
||||||
|
begin
|
||||||
|
process(CLK)
|
||||||
|
begin
|
||||||
|
if rising_edge(CLK) then
|
||||||
|
if RST = '1' then
|
||||||
|
s_cnt <= (others => '0');
|
||||||
|
CLK_400_Hz <= '0';
|
||||||
|
elsif s_cnt = 249_999 then
|
||||||
|
s_cnt <= (others => '0');
|
||||||
|
CLK_400_Hz <= '1';
|
||||||
|
else
|
||||||
|
s_cnt <= s_cnt + 1;
|
||||||
|
CLK_400_Hz <= '0';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
end Behavioral;
|
||||||
75
project_5/project_5.srcs/sources_1/new/top_modul.vhd
Normal file
75
project_5/project_5.srcs/sources_1/new/top_modul.vhd
Normal file
@@ -0,0 +1,75 @@
|
|||||||
|
----------------------------------------------------------------------------------
|
||||||
|
-- Company:
|
||||||
|
-- Engineer:
|
||||||
|
--
|
||||||
|
-- Create Date: 09.03.2026 14:40:14
|
||||||
|
-- Design Name:
|
||||||
|
-- Module Name: top_modul - Behavioral
|
||||||
|
-- Project Name:
|
||||||
|
-- Target Devices:
|
||||||
|
-- Tool Versions:
|
||||||
|
-- Description:
|
||||||
|
--
|
||||||
|
-- Dependencies:
|
||||||
|
--
|
||||||
|
-- Revision:
|
||||||
|
-- Revision 0.01 - File Created
|
||||||
|
-- Additional Comments:
|
||||||
|
--
|
||||||
|
----------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
|
||||||
|
-- Uncomment the following library declaration if using
|
||||||
|
-- arithmetic functions with Signed or Unsigned values
|
||||||
|
--use IEEE.NUMERIC_STD.ALL;
|
||||||
|
|
||||||
|
-- Uncomment the following library declaration if instantiating
|
||||||
|
-- any Xilinx leaf cells in this code.
|
||||||
|
--library UNISIM;
|
||||||
|
--use UNISIM.VComponents.all;
|
||||||
|
|
||||||
|
entity top_modul is
|
||||||
|
Port ( CLK : in STD_LOGIC;
|
||||||
|
RST : in STD_LOGIC;
|
||||||
|
START : in STD_LOGIC;
|
||||||
|
SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
|
||||||
|
ANODS : out STD_LOGIC_VECTOR (3 downto 0));
|
||||||
|
end top_modul;
|
||||||
|
|
||||||
|
architecture Behavioral of top_modul is
|
||||||
|
|
||||||
|
component divider is
|
||||||
|
Port ( CLK : in STD_LOGIC;
|
||||||
|
RST : in STD_LOGIC;
|
||||||
|
CLK_1_Hz : out STD_LOGIC); -- This will be our enable pulse
|
||||||
|
end component;
|
||||||
|
|
||||||
|
component divider_400Hz is
|
||||||
|
Port ( CLK : in STD_LOGIC;
|
||||||
|
RST : in STD_LOGIC;
|
||||||
|
CLK_400_Hz : out STD_LOGIC); -- This will be our enable pulse
|
||||||
|
end component;
|
||||||
|
|
||||||
|
signal clk_1_Hz : std_logic;
|
||||||
|
signal clk_400_Hz : std_logic;
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
U_DIV : divider
|
||||||
|
port map (
|
||||||
|
CLK => CLK,
|
||||||
|
RST => RST,
|
||||||
|
CLK_1_Hz => clk_1_Hz
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
U_DIV_400Hz : divider_400Hz
|
||||||
|
port map (
|
||||||
|
CLK => CLK,
|
||||||
|
RST => RST,
|
||||||
|
CLK_400_Hz => clk_400_Hz
|
||||||
|
);
|
||||||
|
end Behavioral;
|
||||||
243
project_5/project_5.xpr
Normal file
243
project_5/project_5.xpr
Normal file
@@ -0,0 +1,243 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<!-- Product Version: Vivado v2022.2 (64-bit) -->
|
||||||
|
<!-- -->
|
||||||
|
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||||
|
|
||||||
|
<Project Version="7" Minor="61" Path="C:/Users/student/Documents/priecinok/project_5/project_5.xpr">
|
||||||
|
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||||
|
<Configuration>
|
||||||
|
<Option Name="Id" Val="e38d1a4c4a2f4256841e587df17ee164"/>
|
||||||
|
<Option Name="Part" Val="xc7a35tcpg236-1"/>
|
||||||
|
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||||
|
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||||
|
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||||
|
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||||
|
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||||
|
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||||
|
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||||
|
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||||
|
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||||
|
<Option Name="SimulatorVersionXsim" Val="2022.2"/>
|
||||||
|
<Option Name="SimulatorVersionModelSim" Val="2022.2"/>
|
||||||
|
<Option Name="SimulatorVersionQuesta" Val="2022.2"/>
|
||||||
|
<Option Name="SimulatorVersionXcelium" Val="21.09.009"/>
|
||||||
|
<Option Name="SimulatorVersionVCS" Val="S-2021.09"/>
|
||||||
|
<Option Name="SimulatorVersionRiviera" Val="2022.04"/>
|
||||||
|
<Option Name="SimulatorVersionActiveHdl" Val="13.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||||
|
<Option Name="TargetLanguage" Val="VHDL"/>
|
||||||
|
<Option Name="SimulatorLanguage" Val="VHDL"/>
|
||||||
|
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
|
||||||
|
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../AppData/Roaming/Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/>
|
||||||
|
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||||
|
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="ProjectType" Val="Default"/>
|
||||||
|
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||||
|
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||||
|
<Option Name="IPCachePermission" Val="read"/>
|
||||||
|
<Option Name="IPCachePermission" Val="write"/>
|
||||||
|
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||||
|
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||||
|
<Option Name="SimCompileState" Val="TRUE"/>
|
||||||
|
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||||
|
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||||
|
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||||
|
<Option Name="EnableBDX" Val="FALSE"/>
|
||||||
|
<Option Name="DSABoardId" Val="basys3"/>
|
||||||
|
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTXSimExportSim" Val="0"/>
|
||||||
|
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||||
|
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||||
|
<Option Name="WTIesExportSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsExportSim" Val="0"/>
|
||||||
|
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||||
|
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||||
|
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||||
|
<Option Name="XSimRadix" Val="hex"/>
|
||||||
|
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||||
|
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||||
|
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||||
|
<Option Name="SimTypes" Val="rtl"/>
|
||||||
|
<Option Name="SimTypes" Val="bfm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||||
|
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||||
|
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||||
|
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||||
|
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||||
|
</Configuration>
|
||||||
|
<FileSets Version="1" Minor="31">
|
||||||
|
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||||
|
<Filter Type="Srcs"/>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/divider.vhd">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/divider_400Hz.vhd">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/top_modul.vhd">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/counter.vhd">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="AutoDisabled" Val="1"/>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="top_modul"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||||
|
<Filter Type="Constrs"/>
|
||||||
|
<File Path="$PSRCDIR/constrs_1/new/projekt_5.xdc">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="ConstrsType" Val="XDC"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="top_modul"/>
|
||||||
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
<Option Name="TransportPathDelay" Val="0"/>
|
||||||
|
<Option Name="TransportIntDelay" Val="0"/>
|
||||||
|
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||||
|
<Option Name="PamDesignTestbench" Val=""/>
|
||||||
|
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||||
|
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||||
|
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||||
|
<Option Name="SrcSet" Val="sources_1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||||
|
<Filter Type="Utils"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
</FileSets>
|
||||||
|
<Simulators>
|
||||||
|
<Simulator Name="XSim">
|
||||||
|
<Option Name="Description" Val="Vivado Simulator"/>
|
||||||
|
<Option Name="CompiledLib" Val="0"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ModelSim">
|
||||||
|
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Questa">
|
||||||
|
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Riviera">
|
||||||
|
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ActiveHDL">
|
||||||
|
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
</Simulators>
|
||||||
|
<Runs Version="1" Minor="19">
|
||||||
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
</Runs>
|
||||||
|
<Board>
|
||||||
|
<Jumpers/>
|
||||||
|
</Board>
|
||||||
|
<DashboardSummary Version="1" Minor="0">
|
||||||
|
<Dashboards>
|
||||||
|
<Dashboard Name="default_dashboard">
|
||||||
|
<Gadgets>
|
||||||
|
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||||
|
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||||
|
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
</Gadgets>
|
||||||
|
</Dashboard>
|
||||||
|
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||||
|
</Dashboards>
|
||||||
|
</DashboardSummary>
|
||||||
|
</Project>
|
||||||
Reference in New Issue
Block a user