From 8e1bc232ab77e6f8e3ae5055756e4f77bf3725fb Mon Sep 17 00:00:00 2001 From: filipriec skolsky PC Date: Mon, 9 Mar 2026 15:45:31 +0100 Subject: [PATCH] robime dalsie zadanie --- .../constrs_1/new/projekt_5.xdc | 0 .../constrs_1/new/top_module.xdc | 0 .../project_5.srcs/sources_1/new/counter.vhd | 47 ++++ .../project_5.srcs/sources_1/new/divider.vhd | 60 +++++ .../sources_1/new/divider_400Hz.vhd | 60 +++++ .../sources_1/new/top_modul.vhd | 75 ++++++ project_5/project_5.xpr | 243 ++++++++++++++++++ 7 files changed, 485 insertions(+) create mode 100644 project_5/project_5.srcs/constrs_1/new/projekt_5.xdc create mode 100644 project_5/project_5.srcs/constrs_1/new/top_module.xdc create mode 100644 project_5/project_5.srcs/sources_1/new/counter.vhd create mode 100644 project_5/project_5.srcs/sources_1/new/divider.vhd create mode 100644 project_5/project_5.srcs/sources_1/new/divider_400Hz.vhd create mode 100644 project_5/project_5.srcs/sources_1/new/top_modul.vhd create mode 100644 project_5/project_5.xpr diff --git a/project_5/project_5.srcs/constrs_1/new/projekt_5.xdc b/project_5/project_5.srcs/constrs_1/new/projekt_5.xdc new file mode 100644 index 0000000..e69de29 diff --git a/project_5/project_5.srcs/constrs_1/new/top_module.xdc b/project_5/project_5.srcs/constrs_1/new/top_module.xdc new file mode 100644 index 0000000..e69de29 diff --git a/project_5/project_5.srcs/sources_1/new/counter.vhd b/project_5/project_5.srcs/sources_1/new/counter.vhd new file mode 100644 index 0000000..37c930a --- /dev/null +++ b/project_5/project_5.srcs/sources_1/new/counter.vhd @@ -0,0 +1,47 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09.03.2026 15:14:35 +-- Design Name: +-- Module Name: counter - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity counter is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + CE : in STD_LOGIC; + TC : out STD_LOGIC; + COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)); +end counter; + +architecture Behavioral of counter is + +begin + + +end Behavioral; diff --git a/project_5/project_5.srcs/sources_1/new/divider.vhd b/project_5/project_5.srcs/sources_1/new/divider.vhd new file mode 100644 index 0000000..ab00d12 --- /dev/null +++ b/project_5/project_5.srcs/sources_1/new/divider.vhd @@ -0,0 +1,60 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09.03.2026 14:43:21 +-- Design Name: +-- Module Name: divider - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity divider is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + CLK_1_Hz : out STD_LOGIC); +end divider; + +architecture Behavioral of divider is + -- 27 bits is enough for 100 million + signal s_cnt : STD_LOGIC_VECTOR(26 downto 0) := (others => '0'); +begin + process(CLK) + begin + if rising_edge(CLK) then + if RST = '1' then + s_cnt <= (others => '0'); + CLK_1_Hz <= '0'; + elsif s_cnt = 99_999_999 then + s_cnt <= (others => '0'); + CLK_1_Hz <= '1'; -- The pulse + else + s_cnt <= s_cnt + 1; + CLK_1_Hz <= '0'; + end if; + end if; + end process; +end Behavioral; diff --git a/project_5/project_5.srcs/sources_1/new/divider_400Hz.vhd b/project_5/project_5.srcs/sources_1/new/divider_400Hz.vhd new file mode 100644 index 0000000..4c5706d --- /dev/null +++ b/project_5/project_5.srcs/sources_1/new/divider_400Hz.vhd @@ -0,0 +1,60 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09.03.2026 14:49:47 +-- Design Name: +-- Module Name: divider_400Hz - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity divider_400Hz is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + CLK_400_Hz : out STD_LOGIC); +end divider_400Hz; + +architecture Behavioral of divider_400Hz is + -- 18 bits is enough for 250,000 + signal s_cnt : STD_LOGIC_VECTOR(17 downto 0) := (others => '0'); +begin + process(CLK) + begin + if rising_edge(CLK) then + if RST = '1' then + s_cnt <= (others => '0'); + CLK_400_Hz <= '0'; + elsif s_cnt = 249_999 then + s_cnt <= (others => '0'); + CLK_400_Hz <= '1'; + else + s_cnt <= s_cnt + 1; + CLK_400_Hz <= '0'; + end if; + end if; + end process; +end Behavioral; diff --git a/project_5/project_5.srcs/sources_1/new/top_modul.vhd b/project_5/project_5.srcs/sources_1/new/top_modul.vhd new file mode 100644 index 0000000..d769908 --- /dev/null +++ b/project_5/project_5.srcs/sources_1/new/top_modul.vhd @@ -0,0 +1,75 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09.03.2026 14:40:14 +-- Design Name: +-- Module Name: top_modul - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity top_modul is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + START : in STD_LOGIC; + SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0); + ANODS : out STD_LOGIC_VECTOR (3 downto 0)); +end top_modul; + +architecture Behavioral of top_modul is + + component divider is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + CLK_1_Hz : out STD_LOGIC); -- This will be our enable pulse + end component; + + component divider_400Hz is + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + CLK_400_Hz : out STD_LOGIC); -- This will be our enable pulse + end component; + + signal clk_1_Hz : std_logic; + signal clk_400_Hz : std_logic; + +begin + + U_DIV : divider + port map ( + CLK => CLK, + RST => RST, + CLK_1_Hz => clk_1_Hz + ); + + + U_DIV_400Hz : divider_400Hz + port map ( + CLK => CLK, + RST => RST, + CLK_400_Hz => clk_400_Hz + ); +end Behavioral; diff --git a/project_5/project_5.xpr b/project_5/project_5.xpr new file mode 100644 index 0000000..7ae0512 --- /dev/null +++ b/project_5/project_5.xpr @@ -0,0 +1,243 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + +