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working buttons and DIN to control display

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filipriec skolsky PC
2026-03-23 17:22:08 +01:00
parent 07f021abe6
commit 3e2b49671e
3 changed files with 30 additions and 8 deletions
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21
project_7/project_5.srcs/constrs_1/imports/Downloads/Basys-3-Master.xdc
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@@ -11,6 +11,7 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK
## Switches
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {RST}]
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {START}]
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {sw[2]}]
#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports {sw[3]}]
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {sw[4]}]
@@ -21,10 +22,10 @@ set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {START}]
#set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports {sw[9]}]
#set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports {sw[10]}]
#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {sw[11]}]
#set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports {sw[12]}]
#set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports {sw[13]}]
#set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {sw[14]}]
#set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {sw[15]}]
set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[0]}]
set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[1]}]
set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[2]}]
set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {SW_DIN[3]}]
## LEDs
@@ -64,10 +65,14 @@ set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports {ANODS[3]
##Buttons
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports btnC]
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports btnU]
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports btnL]
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports btnR]
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports btnD]
# btnU -> Hours Tens
set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports {BTN_LOAD[3]}]
# btnL -> Hours Units
set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports {BTN_LOAD[2]}]
# btnR -> Minutes Tens
set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports {BTN_LOAD[1]}]
# btnD -> Minutes Units
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports {BTN_LOAD[0]}]
##Pmod Header JA

5
project_7/project_5.srcs/sources_1/new/counter.vhd
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@@ -37,6 +37,8 @@ entity counter is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CE : in STD_LOGIC;
PE : in STD_LOGIC;
DIN : in STD_LOGIC_VECTOR(3 downto 0);
TC : out STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
@@ -53,6 +55,9 @@ begin
if RST = '1' then
s_cnt <= "0000";
TC <= '0'; -- Reset TC
elsif PE = '1' then
s_cnt <= DIN;
TC <= '0';
elsif CE = '1' then
if s_cnt = MAX_LIMIT then
s_cnt <= "0000"; -- Reset to 0 when limit is hit

12
project_7/project_5.srcs/sources_1/new/top_modul.vhd
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@@ -35,6 +35,8 @@ entity top_modul is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
START : in STD_LOGIC;
SW_DIN : in STD_LOGIC_VECTOR (3 downto 0); -- The value to set
BTN_LOAD : in STD_LOGIC_VECTOR (3 downto 0); -- Which digit to set
SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
ANODS : out STD_LOGIC_VECTOR (3 downto 0));
end top_modul;
@@ -57,6 +59,8 @@ architecture Behavioral of top_modul is
Generic ( MAX_LIMIT : STD_LOGIC_VECTOR(3 downto 0) := "1001" ); -- Default to 9
Port ( CLK : in STD_LOGIC;
CE : in STD_LOGIC;
PE : in STD_LOGIC;
DIN : in STD_LOGIC_VECTOR(3 downto 0);
RST : in STD_LOGIC;
TC : out STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
@@ -129,6 +133,8 @@ begin
CLK => CLK,
RST => RST,
CE => s_ce_units,
PE => BTN_LOAD(0),
DIN => SW_DIN,
TC => tc_mu,
COUNT_OUT => sig_m_units
);
@@ -140,6 +146,8 @@ begin
CLK => CLK,
RST => RST,
CE => tc_mu,
PE => BTN_LOAD(1),
DIN => SW_DIN,
TC => tc_mt,
COUNT_OUT => sig_m_tens
);
@@ -154,6 +162,8 @@ begin
CLK => CLK,
RST => hour_reset,
CE => tc_mt,
PE => BTN_LOAD(2),
DIN => SW_DIN,
TC => tc_hu,
COUNT_OUT => sig_h_units
);
@@ -165,6 +175,8 @@ begin
CLK => CLK,
RST => hour_reset,
CE => tc_hu,
PE => BTN_LOAD(3),
DIN => SW_DIN,
TC => open,
COUNT_OUT => sig_h_tens
);