filipriec/FPGA---VHDL
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its now working perfectly well with HH:MM and MM:SS to switch between them via button

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filipriec skolsky PC
2026-04-13 17:29:48 +02:00
parent d2383f0bd5
commit 23eb5ae24c
6 changed files with 315 additions and 175 deletions
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12
project_7/project_5.xpr
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@@ -92,6 +92,12 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/clock_logic.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/counter.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -116,6 +122,12 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/display_drive.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/divider.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>