filipriec/FPGA---VHDL
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its now working perfectly well with HH:MM and MM:SS to switch between them via button

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filipriec skolsky PC
2026-04-13 17:29:48 +02:00
parent d2383f0bd5
commit 23eb5ae24c
6 changed files with 315 additions and 175 deletions
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13
project_7/project_5.srcs/sources_1/new/counter.vhd
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@@ -45,7 +45,9 @@ end counter;
architecture Behavioral of counter is
-- Internal signal to keep track of the current number
signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal s_cnt : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
-- (others => '0') je to iste ako "0000" pre 4 bity. Ale narozdiel od hardcode
-- robi nuly cez vsetky bity, takze zalezi na pocte bitov rodica
begin
-- Main counting logic
@@ -54,23 +56,18 @@ begin
if rising_edge(CLK) then
if RST = '1' then
s_cnt <= "0000";
TC <= '0'; -- Reset TC
elsif PE = '1' then
s_cnt <= DIN;
TC <= '0';
elsif CE = '1' then
if s_cnt = MAX_LIMIT then
s_cnt <= "0000"; -- Reset to 0 when limit is hit
TC <= '1';
s_cnt <= (others => '0'); -- Reset to 0 when limit is hit
else
s_cnt <= s_cnt + 1; -- Otherwise increment
TC <= '0';
end if;
else
TC <= '0';
end if;
end if;
end process;
TC <= '1' when (s_cnt = MAX_LIMIT and CE = '1') else '0';
COUNT_OUT <= s_cnt;