its now working perfectly well with HH:MM and MM:SS to switch between them via button
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filipriec skolsky PC
178
project_7/project_5.srcs/sources_1/new/clock_logic.vhd
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178
project_7/project_5.srcs/sources_1/new/clock_logic.vhd
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-- clock_logic.vhd
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity clock_logic is
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Port (
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CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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CE_1HZ : in STD_LOGIC; -- Enable signal from the divider
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SW_DIN : in STD_LOGIC_VECTOR (3 downto 0);
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BTN_LOAD : in STD_LOGIC_VECTOR (3 downto 0);
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-- Outputs to the top module/display
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S_UNITS : out STD_LOGIC_VECTOR (3 downto 0);
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S_TENS : out STD_LOGIC_VECTOR (3 downto 0);
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M_UNITS : out STD_LOGIC_VECTOR (3 downto 0);
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M_TENS : out STD_LOGIC_VECTOR (3 downto 0);
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H_UNITS : out STD_LOGIC_VECTOR (3 downto 0);
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H_TENS : out STD_LOGIC_VECTOR (3 downto 0)
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);
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end clock_logic;
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architecture Behavioral of clock_logic is
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component counter is
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Generic ( MAX_LIMIT : STD_LOGIC_VECTOR(3 downto 0) := "1001" ); -- Default to 9
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Port ( CLK : in STD_LOGIC;
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CE : in STD_LOGIC;
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PE : in STD_LOGIC;
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DIN : in STD_LOGIC_VECTOR(3 downto 0);
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RST : in STD_LOGIC;
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TC : out STD_LOGIC;
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COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
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end component;
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-- Internal signals to connect the counters
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signal sig_s_units, sig_s_tens : std_logic_vector(3 downto 0);
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signal sig_m_units, sig_m_tens : std_logic_vector(3 downto 0);
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signal sig_h_units, sig_h_tens : std_logic_vector(3 downto 0);
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-- Carry signals (TC)
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signal tc_su, tc_st, tc_mu, tc_mt, tc_hu : std_logic;
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-- Reset for hours (to handle the 24 reset)
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signal hour_reset : std_logic;
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-- Specific load enable signals that check for boundaries
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signal load_h_tens, load_h_units : std_logic;
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signal load_m_tens, load_m_units : std_logic;
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-- Internal signals for the "Safe" load triggers
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signal safe_load_su, safe_load_st : std_logic;
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signal safe_load_mu, safe_load_mt : std_logic;
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signal safe_load_hu, safe_load_ht : std_logic;
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begin
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-- MINUTES CONSTRAINTS (Max 59)
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load_m_units <= BTN_LOAD(0) when (SW_DIN <= "1001") else '0'; -- 0-9
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load_m_tens <= BTN_LOAD(1) when (SW_DIN <= "0101") else '0'; -- 0-5
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-- HOURS CONSTRAINTS (Max 23)
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-- Rule A: Cannot load Tens > 2.
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-- Rule B: If Tens is 2, cannot load Units > 3.
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-- Rule C: If Units is > 3, cannot load Tens into 2.
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load_h_tens <= BTN_LOAD(3) when (
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SW_DIN < "0010" or
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(SW_DIN = "0010" and sig_h_units <= "0011")
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) else '0';
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load_h_units <= BTN_LOAD(2) when (
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(sig_h_tens < "0010" and SW_DIN <= "1001") or
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(sig_h_tens = "0010" and SW_DIN <= "0011")
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) else '0';
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-------------------------------------------------------
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-- SECONDS SECTION
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-- SECONDS UNITS (0-9) - Triggered by the 1Hz pulse
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U_CNT_SEC_UNITS : counter
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generic map ( MAX_LIMIT => "1001" ) -- do 9
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port map (
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CLK => CLK, RST => RST, CE => CE_1HZ,
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PE => '0', DIN => "0000", -- Seconds usually don't need manual load
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TC => tc_su, COUNT_OUT => sig_s_units
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);
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-- SECONDS TENS (0-5) - Triggered when Sec Units reach 9
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U_CNT_SEC_TENS : counter
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generic map ( MAX_LIMIT => "0101" ) -- do 5
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port map (
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CLK => CLK, RST => RST, CE => tc_su,
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PE => '0', DIN => "0000",
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TC => tc_st, COUNT_OUT => sig_s_tens
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);
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-------------------------------------------------------
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-- MINUTES SECTION
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-- MINUTES UNITS (0-9) - When Seconds reach 59
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U_CNT_MIN_UNITS : counter
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generic map ( MAX_LIMIT => "1001" ) -- do 9
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port map (
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CLK => CLK,
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RST => RST,
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CE => tc_st,
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PE => load_m_units,
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DIN => SW_DIN,
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TC => tc_mu,
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COUNT_OUT => sig_m_units
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);
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-- MINUTES TENS (0-5)
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U_CNT_MIN_TENS : counter
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generic map ( MAX_LIMIT => "0101" ) -- do 5
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port map (
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CLK => CLK,
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RST => RST,
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CE => tc_mu,
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PE => load_m_tens,
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DIN => SW_DIN,
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TC => tc_mt,
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COUNT_OUT => sig_m_tens
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);
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-------------------------------------------------------
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-- HOURS SECTION
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-- If we are at 23:59:59, the next tick should reset hours
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process(sig_h_tens, sig_h_units, tc_mt, RST)
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begin
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if RST = '1' then
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hour_reset <= '1';
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elsif (sig_h_tens = "0010" and sig_h_units = "0011" and tc_mt = '1') then
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hour_reset <= '1';
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else
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hour_reset <= '0';
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end if;
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end process;
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-- HOURS UNITS (0-9)
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U_CNT_HOR_UNITS : counter
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generic map ( MAX_LIMIT => "1001" ) -- To 9
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port map (
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CLK => CLK,
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RST => hour_reset,
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CE => tc_mt,
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PE => load_h_units,
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DIN => SW_DIN,
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TC => tc_hu,
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COUNT_OUT => sig_h_units
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);
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-- HOURS TENS (0-2)
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U_CNT_HOR_TENS : counter
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generic map ( MAX_LIMIT => "0010" ) -- To 2
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port map (
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CLK => CLK,
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RST => hour_reset,
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CE => tc_hu,
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PE => load_h_tens,
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DIN => SW_DIN,
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TC => open,
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COUNT_OUT => sig_h_tens
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);
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-- Drive output ports
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S_UNITS <= sig_s_units;
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S_TENS <= sig_s_tens;
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M_UNITS <= sig_m_units;
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M_TENS <= sig_m_tens;
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H_UNITS <= sig_h_units;
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H_TENS <= sig_h_tens;
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end Behavioral;
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