final uml

semestralka_1_final_crate/software_uart/docs/decode_rx_uml.txt

@@ -0,0 +1,82 @@
+@startuml
+title Dekodovanie UART: decode_uart_samples
+
+start
+
+:Inicializacia out (Vec<u8, 256>) a idx = 0;
+
+:nbits = cfg.data_bits;
+:ovs = oversample;
+
+:parity_bits = 0 alebo 1 podla cfg.parity;
+:stop_bits_count = 1 alebo 2 podla cfg.stop_bits;
+
+:frame_bits = 1 + nbits + parity_bits + stop_bits_count;
+:frame_len = frame_bits * ovs;
+
+while (idx + frame_len <= samples.len()?) is (ano)
+  if (Start bit detekovany?\n(samples[idx] != 0 && samples[idx + 1] == 0)) then (ano)
+    :center_offset = ovs / 2;
+    :scan_idx = idx + center_offset;
+
+    if (get_bit(scan_idx) == 0?\nvalidacia START bitu) then (ano)
+      :scan_idx += ovs\n(posun na prvy data bit);
+      :data = 0;
+
+      repeat :Citanie datovych bitov (0..nbits-1, LSB first)
+        if (get_bit(scan_idx) == 1?) then (ano)
+          :data |= 1 << bit;
+        endif
+        :scan_idx += ovs;
+      repeat while (zvysne data bity?) is (ano)
+      ->nie;
+
+      :error_data = false;
+
+      if (cfg.parity != Parity::None?) then (ano)
+        :expected_parity = calculate_parity(data, cfg.parity);
+        :actual_parity = get_bit(scan_idx);
+        if (expected_parity != actual_parity?) then (ano)
+          :error_data = true;
+          note right: Chyba parity
+        endif
+        :scan_idx += ovs;
+      endif
+
+      repeat :Kontrola stop bitov
+        if (get_bit(scan_idx) == 0?) then (ano)
+          :error_data = true;
+          note right: Framing chyba (stop bit = 0)
+          break
+        endif
+        :scan_idx += ovs;
+      repeat while (zvysne stop bity?) is (ano)
+      ->nie;
+
+      if (error_data?) then (ano)
+        :idx += 1;\n(preskoc chybny frame);
+      else (nie)
+        :push data do out;
+        :idx = scan_idx;
+
+        :Preskoc idle HIGH (hladanie dalsieho start bitu);
+        while (idx < samples.len() && samples[idx] != 0?) is (ano)
+          :idx += 1;
+        endwhile (nie)
+
+        if (idx > 0?) then (ano)
+          :idx -= 1;\n("mensi hack");
+        endif
+      endif
+    else (nie)
+      :idx += 1;\n(falosny start);
+    endif
+  else (nie)
+    :idx += 1;
+  endif
+endwhile (nie)
+
+:Navrat (out, idx);
+
+stop
+@enduml

semestralka_1_final_crate/software_uart/docs/encode_tx.txt

@@ -0,0 +1,31 @@
+@startuml
+title Enkodovanie UART: encode_uart_byte_cfg
+
+start
+
+:set_high = 1 << pin_bit;
+:set_low = 1 << (pin_bit + 16);
+:nbits = cfg.data_bits, idx = 0;
+
+:START bit (LOW)\nout[idx++] = set_low;
+
+repeat :Data bity (LSB first)
+  :out[idx++] = ((data >> i) & 1) ?\nset_high : set_low;
+repeat while (i < nbits?) is (ano)
+->nie;
+
+if (cfg.parity != None?) then (ano)
+  :ones = data.count_ones() & 1;
+  :par_bit = (Even) ? ones==1 : ones==0;
+  :out[idx++] = par_bit ? set_high : set_low;
+endif
+
+repeat :STOP bity (HIGH)
+  :out[idx++] = set_high;
+repeat while (zvysne stop bity?) is (ano)
+->nie;
+
+:Return idx;
+
+stop
+@enduml

semestralka_1_final_crate/software_uart/docs/flake.nix

@@ -0,0 +1,18 @@
+{
+  description = "PlantUML dev shell";
+
+  inputs.nixpkgs.url = "github:NixOS/nixpkgs";
+
+  outputs = { self, nixpkgs }:
+    let
+      system = "x86_64-linux";
+      pkgs = nixpkgs.legacyPackages.${system};
+    in {
+      devShells.${system}.default = pkgs.mkShell {
+        buildInputs = [
+          pkgs.plantuml
+          pkgs.graphviz
+        ];
+      };
+    };
+}

semestralka_1_final_crate/software_uart/docs/rx_uml.txt

@@ -0,0 +1,35 @@
+@startuml
+title TIM7 → DMA → ReadableRingBuffer → rx_dma_task
+
+start
+
+:TIM7 tick (oversampling);
+
+:DMA interrupts ON;
+:DMA ringbuffer setup;
+
+repeat
+  :'read_exact' cakanie na byty o velkosti CHUNK_SIZE;
+
+  :Extract Rx z IDR → level_buf;
+
+  :current_end = valid_len + CHUNK_SIZE;
+
+  :Dekodovanie decode_uart_samples(level_buf[0..current_end]);
+
+  if (decoded byty existuju?) then (ano)
+    :pipe_rx.write(decoded);
+  endif
+
+  :Posunutie level_buf vlavo o 'consumed';
+  :valid_len = remaining;
+
+  if (valid_len >= HISTORY_SIZE?) then (ano)
+    :Zmensenie o HISTORY_SIZE/2;
+    :valid_len = HISTORY_SIZE/2;
+  endif
+
+  :yield_now();
+
+repeat while (true)
+@enduml

semestralka_1_final_crate/software_uart/docs/tx_uml.txt

@@ -0,0 +1,29 @@
+@startuml
+title pipe_rx → DMA → GPIOx_BSRR
+
+start
+
+
+
+repeat
+  :n = pipe_rx.read(rx_buf);
+  
+  if (n > 0?) then (ano)
+    :Enkodovanie rx_buf → frame_buf\n(encode_uart_frames);
+    
+    if (used > 0?) then (ano)
+      :TIM6.SR.UIF = false;
+      :Cakanie na TIM6 tick;
+      :TIM6.SR.UIF = false;
+      
+      :DMA Transfer\nframe_buf → GPIOx_BSRR;
+      :Transfer await;
+    endif
+  endif
+  
+  :yield_now();
+
+repeat while (true)
+
+stop
+@enduml