bridge between usart1 and usart2

.gitignore

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+*.pdf

datasheet.txt

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+https://www.st.com/content/ccc/resource/technical/document/reference_manual/group0/f3/60/ca/d2/98/c8/47/88/DM00477635/files/DM00477635.pdf/jcr:content/translations/en.DM00477635.pdf

dma_gpio/Cargo.toml

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+[package]
+authors = ["Priec <filippriec@gmail.com>"]
+name = "dma_gpio"
+edition = "2024"
+version = "0.1.0"
+
+
+[dependencies]
+cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.5"
+panic-halt = "1.0.0"
+
+embassy-executor = { git = "https://github.com/embassy-rs/embassy.git", branch = "main", features = ["arch-cortex-m", "executor-thread"] }
+embassy-futures = { git = "https://github.com/embassy-rs/embassy.git", branch = "main" }
+embassy-sync    = { git = "https://github.com/embassy-rs/embassy.git", branch = "main" }
+embassy-time    = { git = "https://github.com/embassy-rs/embassy.git", branch = "main", features = ["tick-hz-32_768"] }
+embassy-hal-internal = { git = "https://github.com/embassy-rs/embassy.git", branch = "main" }
+embassy-usb = { git = "https://github.com/embassy-rs/embassy.git", branch = "main" }
+embassy-stm32 = { git = "https://github.com/embassy-rs/embassy.git", branch = "main", features = ["unstable-pac", "stm32u575zi", "time-driver-tim2", "memory-x", "defmt"] }
+
+embedded-hal = "1.0.0"
+embedded-graphics = "0.8.1"
+heapless = { version = "0.9.1", default-features = false }
+micromath = "2.1.0"
+tinybmp = "0.6.0"
+panic-probe = { version = "1.0.0", features = ["defmt"] }
+defmt-rtt = "1.1.0"
+defmt = "1.0.1"
+static_cell = "2.1.1"

dma_gpio/src/bin/main.rs

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+// src/bin/main.rs
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::dma::Request;
+use embassy_stm32::gpio::{Input, Output, Level, Pull, Speed};
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use embassy_stm32::dma::{TransferOptions, WritableRingBuffer};
+use dma_gpio::software_uart::{
+    dma_timer::{init_tim6_for_uart, init_tim7_for_uart},
+    gpio_dma_uart_tx::encode_uart_frames,
+    gpio_dma_uart_rx::rx_dma_task,
+    debug::dump_tim6_regs,
+};
+use dma_gpio::config::{BAUD, TX_PIN_BIT, RX_OVERSAMPLE, TX_OVERSAMPLE};
+use dma_gpio::config::{TX_RING_BYTES, RX_RING_BYTES, PIPE_RX_SIZE};
+use static_cell::StaticCell;
+use embassy_futures::yield_now;
+use {defmt_rtt as _, panic_probe as _};
+
+pub const TIM6_UP_REQ: Request = 4;
+
+static PIPE_RX: Pipe<CriticalSectionRawMutex, PIPE_RX_SIZE> = Pipe::new();
+static TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
+static RX_RING: StaticCell<[u8; RX_RING_BYTES]> = StaticCell::new();
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    let p = embassy_stm32::init(Default::default());
+    info!("Hehe");
+
+    let _rx = Input::new(p.PA3, Pull::Up);
+    let _tx = Output::new(p.PA2, Level::High, Speed::VeryHigh);
+
+    init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE);
+    init_tim7_for_uart(p.TIM7, BAUD, RX_OVERSAMPLE);
+
+    dump_tim6_regs();
+
+    // Safe one-time init from StaticCell
+    let rx_ring: &mut [u8; RX_RING_BYTES] = RX_RING.init([0; RX_RING_BYTES]);
+    let tx_ring_mem: &mut [u32; TX_RING_BYTES] = TX_RING.init([0; TX_RING_BYTES]);
+
+    // Spawn tasks
+    spawner.spawn(rx_dma_task(p.GPDMA1_CH1, &PIPE_RX, rx_ring).unwrap());
+
+    // Create and start the TX DMA ring in main.
+    // let bsrr_ptr = embassy_stm32::pac::GPIOA.bsrr().as_ptr() as *mut u32;
+    let odr_ptr = embassy_stm32::pac::GPIOA.odr().as_ptr() as *mut u32;
+    let mut tx_opts = TransferOptions::default();
+    tx_opts.half_transfer_ir = true;
+    tx_opts.complete_transfer_ir = true;
+
+    // SAFETY: tx_ring_mem is exclusive
+    let mut tx_ring = unsafe {
+        WritableRingBuffer::new(
+            p.GPDMA1_CH0,
+            TIM6_UP_REQ,
+            odr_ptr,
+            tx_ring_mem,
+            tx_opts,
+        )
+    };
+    // Start DMA
+    tx_ring.start();
+    info!("TX DMA ring started");
+
+    let mut frame_buf = [0u32; 4096];
+
+    loop {
+        info!("tick start");
+        // Timer::after(Duration::from_millis(100)).await;
+        // info!("tick end");
+        let used = encode_uart_frames(
+            TX_PIN_BIT,
+            b"Hello marshmallow\r\n",
+            &mut frame_buf,
+        )
+        .await;
+
+        if used == 0 {
+            info!("encode_uart_frames() produced 0 words, skipping write");
+            yield_now().await;
+            continue;
+        }
+        let _ = tx_ring.write_exact(&frame_buf[..used]).await;
+        info!("text");
+        yield_now().await;
+    }
+}

dma_gpio/src/config.rs

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+// src/config.rs
+use crate::software_uart::uart_emulation::{Parity, StopBits, UartConfig};
+
+pub const BAUD: u32 = 115_200;
+pub const TX_PIN_BIT: u8 = 2; // PA2
+pub const TX_OVERSAMPLE: u16 = 1;
+pub const RX_OVERSAMPLE: u16 = 16;
+pub const RX_RING_BYTES: usize = 4096;
+pub const TX_RING_BYTES: usize = 4096;
+pub const PIPE_RX_SIZE: usize = 256;
+
+pub const UART_CFG: UartConfig = UartConfig {
+    data_bits: 8,
+    parity: Parity::None,
+    stop_bits: StopBits::One,
+};

dma_gpio/src/lib.rs

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+#![no_std]
+
+pub mod software_uart;
+pub mod config;

dma_gpio/src/software_uart/debug.rs

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+// src/software_uart/debug.rs
+use defmt::info;
+
+pub fn dump_tim6_regs() {
+    use embassy_stm32::pac::timer::TimBasic;
+    let tim = unsafe { TimBasic::from_ptr(0x4000_1000usize as _) };
+    let sr = tim.sr().read();
+    let dier = tim.dier().read();
+    let cr1 = tim.cr1().read();
+    let arr = tim.arr().read().arr();
+    let psc = tim.psc().read();
+    info!(
+        "TIM6: CR1.CEN={} DIER.UDE={} SR.UIF={} PSC={} ARR={}",
+        cr1.cen(),
+        dier.ude(),
+        sr.uif(),
+        psc,
+        arr
+    );
+}
+
+pub fn dump_dma_ch0_regs() {
+    use embassy_stm32::pac::gpdma::Gpdma;
+    let dma = unsafe { Gpdma::from_ptr(0x4002_0000usize as _) };
+    let ch = dma.ch(0);
+    let cr = ch.cr().read();
+    let tr1 = ch.tr1().read();
+    let tr2 = ch.tr2().read();
+    let br1 = ch.br1().read();
+    info!(
+        "GPDMA1_CH0: EN={} PRIO={} SDW={} DDW={} SINC={} DINC={} REQSEL={} SWREQ={} DREQ={} BNDT={}",
+        cr.en(),
+        cr.prio(),
+        tr1.sdw(),
+        tr1.ddw(),
+        tr1.sinc(),
+        tr1.dinc(),
+        tr2.reqsel(),
+        tr2.swreq(),
+        tr2.dreq(),
+        br1.bndt()
+    );
+}

dma_gpio/src/software_uart/dma_timer.rs

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+// src/dma_timer.rs
+
+use embassy_stm32::{
+    peripherals::{TIM6, TIM7},
+    rcc,
+    timer::low_level::Timer,
+    Peri,
+};
+use core::mem;
+use embassy_stm32::timer::BasicInstance;
+use embassy_stm32::pac::timer::vals::Urs;
+
+/// Initializes TIM6 to tick at `baud * oversample` frequency.
+/// Each TIM6 update event triggers one DMA beat.
+pub fn init_tim6_for_uart<'d>(tim6: Peri<'d, TIM6>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM6>();
+    let ll = Timer::new(tim6);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+/// Initializes TIM7 to tick at `baud * oversample` frequency.
+/// Each TIM7 update event triggers one DMA beat.
+pub fn init_tim7_for_uart<'d>(tim7: Peri<'d, TIM7>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM7>();
+    let ll = Timer::new(tim7);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+// Shared internal helper — identical CR1/ARR setup
+fn configure_basic_timer<T: BasicInstance>(ll: &Timer<'_, T>, baud: u32, oversample: u16) {
+    let f_timer = rcc::frequency::<T>().0;
+    let target = baud.saturating_mul(oversample.max(1) as u32).max(1);
+
+    // Compute ARR (prescaler = 0)
+    let mut arr = (f_timer / target).saturating_sub(1) as u16;
+    if arr == 0 { arr = 1; }
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_cen(false);
+        w.set_opm(false);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+
+    ll.regs_basic().psc().write_value(0u16);
+    ll.regs_basic().arr().write(|w| w.set_arr(arr));
+    ll.regs_basic().dier().modify(|w| w.set_ude(true));
+    ll.regs_basic().egr().write(|w| w.set_ug(true));
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_opm(false);
+        w.set_cen(true);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+}

dma_gpio/src/software_uart/gpio_dma_uart_rx.rs

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+// src/software_uart/runtime.rs
+use embassy_executor::task;
+use embassy_stm32::{
+    dma::Request,
+    peripherals::GPDMA1_CH1,
+    Peri,
+};
+use embassy_stm32::dma::{
+    ReadableRingBuffer,
+    TransferOptions,
+};
+use crate::config::{RX_OVERSAMPLE, UART_CFG};
+use crate::software_uart::decode_uart_samples;
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use embassy_futures::yield_now;
+
+// datasheet tabulka 137
+pub const TIM7_UP_REQ: Request = 5;
+
+/// RX DMA task: reads GPIO samples paced by TIM7 and fills PIPE_RX
+#[task]
+pub async fn rx_dma_task(
+    ch: Peri<'static, GPDMA1_CH1>,
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 256>,
+    ring: &'static mut [u8],
+) {
+    let gpioa_idr = embassy_stm32::pac::GPIOA.idr().as_ptr() as *mut u8;
+
+    let mut opts = TransferOptions::default();
+    opts.half_transfer_ir = true;
+    opts.complete_transfer_ir = true;
+
+    // SAFETY: ring is exclusive to this task
+    let mut rx = unsafe { ReadableRingBuffer::new(ch, TIM7_UP_REQ, gpioa_idr, ring, opts) };
+    rx.start();
+
+    let mut chunk = [0u8; 256];
+    loop {
+        let _ = rx.read_exact(&mut chunk).await;
+        let decoded = decode_uart_samples(&chunk, RX_OVERSAMPLE, &UART_CFG);
+        pipe_rx.write(&decoded).await;
+        yield_now().await;
+    }
+}

dma_gpio/src/software_uart/gpio_dma_uart_tx.rs

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+// src/software_uart/gpio_dma_uart_tx.rs
+use embassy_futures::yield_now;
+use crate::software_uart::uart_emulation::encode_uart_byte_cfg;
+use crate::config::UART_CFG;
+
+pub async fn encode_uart_frames<'a>(
+    pin_bit: u8,
+    bytes: &[u8],
+    out_buf: &'a mut [u32],
+) -> usize {
+    let mut offset = 0;
+    for &b in bytes {
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(pin_bit, b, &UART_CFG, &mut frame);
+
+        if offset + used <= out_buf.len() {
+            out_buf[offset..offset + used].copy_from_slice(&frame[..used]);
+            offset += used;
+        } else {
+            break;
+        }
+
+        // cooperative async yield
+        yield_now().await;
+    }
+    offset
+}
+

dma_gpio/src/software_uart/mod.rs

@@ -0,0 +1,13 @@
+// src/software_uart/mod.rs
+
+pub mod gpio_dma_uart_tx;
+pub mod gpio_dma_uart_rx;
+pub mod dma_timer;
+pub mod uart_emulation;
+pub mod debug;
+
+pub use gpio_dma_uart_tx::*;
+pub use gpio_dma_uart_rx::*;
+pub use dma_timer::*;
+pub use uart_emulation::*;
+pub use debug::*;

dma_gpio/src/software_uart/uart_emulation.rs

@@ -0,0 +1,151 @@
+// src/software_uart/uart_emulation.rs
+use heapless::Vec;
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Parity {
+    None,
+    Even,
+    Odd,
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum StopBits {
+    One,
+    Two,
+}
+
+#[derive(Clone, Copy, Debug)]
+pub struct UartConfig {
+    pub data_bits: u8,
+    pub parity: Parity,
+    pub stop_bits: StopBits,
+}
+
+impl Default for UartConfig {
+    fn default() -> Self {
+        Self {
+            data_bits: 8,
+            parity: Parity::None,
+            stop_bits: StopBits::One,
+        }
+    }
+}
+
+/// Encodes one byte into a sequence of GPIO BSRR words
+pub fn encode_uart_byte_cfg(
+    pin_bit: u8,
+    data: u8,
+    cfg: &UartConfig,
+    out: &mut [u32; 12],
+) -> usize {
+    // GPIOx_BSRR register str. 636 kap. 13.4.7
+    let set_high = |bit: u8| -> u32 { 1u32 << bit };
+    let set_low = |bit: u8| -> u32 { 0 };
+    // let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) };
+
+    let mut idx = 0usize;
+
+    // START bit (LOW)
+    out[idx] = set_low(pin_bit);
+    idx += 1;
+
+    // Data bits, LSB-first
+    let nbits = cfg.data_bits.clamp(5, 8);
+    for i in 0..nbits {
+        let one = ((data >> i) & 1) != 0;
+        out[idx] = if one { set_high(pin_bit) } else { set_low(pin_bit) };
+        idx += 1;
+    }
+
+    // Parity
+    match cfg.parity {
+        Parity::None => {}
+        Parity::Even | Parity::Odd => {
+            let mask: u8 = if nbits == 8 { 0xFF } else { (1u16 << nbits) as u8 - 1 };
+            let ones = (data & mask).count_ones() & 1;
+            let par_bit_is_one = match cfg.parity {
+                Parity::Even => ones == 1,
+                Parity::Odd => ones == 0,
+                _ => false,
+            };
+            out[idx] = if par_bit_is_one {
+                set_high(pin_bit)
+            } else {
+                set_low(pin_bit)
+            };
+            idx += 1;
+        }
+    }
+
+    // STOP bits (HIGH)
+    let stop_ticks = match cfg.stop_bits {
+        StopBits::One => 1usize,
+        StopBits::Two => 2usize,
+    };
+    for _ in 0..stop_ticks {
+        out[idx] = set_high(pin_bit);
+        idx += 1;
+    }
+
+    idx
+}
+
+/// Decode an oversampled stream of logic levels into UART bytes.
+pub fn decode_uart_samples(
+    samples: &[u8],
+    oversample: u16,
+    cfg: &UartConfig,
+) -> heapless::Vec<u8, 256> {
+
+    let mut out = Vec::<u8, 256>::new();
+    let mut idx = 0usize;
+    let nbits = cfg.data_bits as usize;
+
+    while idx + (oversample as usize * (nbits + 3)) < samples.len() {
+        // Wait for start bit (falling edge: high -> low)
+        if samples[idx] != 0 && samples[idx + 1] == 0 {
+            // Align to middle of start bit
+            idx += (oversample / 2) as usize;
+
+            // Sanity check start bit really low
+            if samples.get(idx).copied().unwrap_or(1) != 0 {
+                idx += 1;
+                continue;
+            }
+
+            // Sample data bits
+            let mut data: u8 = 0;
+            for bit in 0..nbits {
+                idx += oversample as usize;
+                let bit_val = samples
+                    .get(idx)
+                    .map(|&b| if b != 0 { 1u8 } else { 0u8 })
+                    .unwrap_or(1);
+                data |= bit_val << bit;
+            }
+
+            // Parity: skip / verify
+            match cfg.parity {
+                Parity::None => {}
+                Parity::Even | Parity::Odd => {
+                    idx += oversample as usize;
+                    // You can optionally add parity check here if needed
+                }
+            }
+
+            // Move past stop bits
+            let stop_skip = match cfg.stop_bits {
+                StopBits::One => oversample as usize,
+                StopBits::Two => (oversample * 2) as usize,
+            };
+            idx += stop_skip;
+
+            // Push decoded byte
+            let _ = out.push(data);
+        } else {
+            idx += 1;
+        }
+    }
+
+    out
+}

dma_gpio2/.cargo/config.toml

@@ -0,0 +1,15 @@
+[build]
+target = "thumbv8m.main-none-eabihf"
+
+[target.thumbv8m.main-none-eabihf]
+runner = "probe-rs run --chip STM32U575ZITxQ"
+
+rustflags = [
+  "-C", "linker=rust-lld",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "link-arg=-Tdefmt.x",
+  "-C", "link-arg=--nmagic",
+]
+
+[package.metadata.cargo-flash]
+chip = "STM32U575ZIT"

dma_gpio2/.gitignore

@@ -0,0 +1 @@
+/target

dma_gpio2/Cargo.toml

@@ -0,0 +1,29 @@
+[package]
+authors = ["Priec <filippriec@gmail.com>"]
+name = "dma_gpio"
+edition = "2024"
+version = "0.1.0"
+
+
+[dependencies]
+cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.5"
+panic-halt = "1.0.0"
+
+embassy-executor = { path = "/home/filip/programs/embassy/embassy-executor", features = ["arch-cortex-m", "executor-thread"] }
+embassy-futures = { path = "/home/filip/programs/embassy/embassy-futures" }
+embassy-sync = { path = "/home/filip/programs/embassy/embassy-sync" }
+embassy-time = { path = "/home/filip/programs/embassy/embassy-time", features = ["tick-hz-32_768"] }
+embassy-hal-internal = { path = "/home/filip/programs/embassy/embassy-hal-internal" }
+embassy-usb = { path = "/home/filip/programs/embassy/embassy-usb" }
+embassy-stm32 = { path = "/home/filip/programs/embassy/embassy-stm32", features = ["unstable-pac", "stm32u575zi", "time-driver-tim2", "memory-x", "defmt"] }
+
+embedded-hal = "1.0.0"
+embedded-graphics = "0.8.1"
+heapless = { version = "0.9.1", default-features = false }
+micromath = "2.1.0"
+tinybmp = "0.6.0"
+panic-probe = { version = "1.0.0", features = ["defmt"] }
+defmt-rtt = "1.1.0"
+defmt = "1.0.1"
+static_cell = "2.1.1"

dma_gpio2/LICENSE-APACHE

@@ -0,0 +1,201 @@
+                              Apache License
+                        Version 2.0, January 2004
+                     http://www.apache.org/licenses/
+
+TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+1. Definitions.
+
+   "License" shall mean the terms and conditions for use, reproduction,
+   and distribution as defined by Sections 1 through 9 of this document.
+
+   "Licensor" shall mean the copyright owner or entity authorized by
+   the copyright owner that is granting the License.
+
+   "Legal Entity" shall mean the union of the acting entity and all
+   other entities that control, are controlled by, or are under common
+   control with that entity. For the purposes of this definition,
+   "control" means (i) the power, direct or indirect, to cause the
+   direction or management of such entity, whether by contract or
+   otherwise, or (ii) ownership of fifty percent (50%) or more of the
+   outstanding shares, or (iii) beneficial ownership of such entity.
+
+   "You" (or "Your") shall mean an individual or Legal Entity
+   exercising permissions granted by this License.
+
+   "Source" form shall mean the preferred form for making modifications,
+   including but not limited to software source code, documentation
+   source, and configuration files.
+
+   "Object" form shall mean any form resulting from mechanical
+   transformation or translation of a Source form, including but
+   not limited to compiled object code, generated documentation,
+   and conversions to other media types.
+
+   "Work" shall mean the work of authorship, whether in Source or
+   Object form, made available under the License, as indicated by a
+   copyright notice that is included in or attached to the work
+   (an example is provided in the Appendix below).
+
+   "Derivative Works" shall mean any work, whether in Source or Object
+   form, that is based on (or derived from) the Work and for which the
+   editorial revisions, annotations, elaborations, or other modifications
+   represent, as a whole, an original work of authorship. For the purposes
+   of this License, Derivative Works shall not include works that remain
+   separable from, or merely link (or bind by name) to the interfaces of,
+   the Work and Derivative Works thereof.
+
+   "Contribution" shall mean any work of authorship, including
+   the original version of the Work and any modifications or additions
+   to that Work or Derivative Works thereof, that is intentionally
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+
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+
+   To apply the Apache License to your work, attach the following
+   boilerplate notice, with the fields enclosed by brackets "[]"
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+Copyright [yyyy] [name of copyright owner]
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+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.

dma_gpio2/LICENSE-MIT

@@ -0,0 +1,23 @@
+Permission is hereby granted, free of charge, to any
+person obtaining a copy of this software and associated
+documentation files (the "Software"), to deal in the
+Software without restriction, including without
+limitation the rights to use, copy, modify, merge,
+publish, distribute, sublicense, and/or sell copies of
+the Software, and to permit persons to whom the Software
+is furnished to do so, subject to the following
+conditions:
+
+The above copyright notice and this permission notice
+shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
+ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
+IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.

dma_gpio2/Makefile

@@ -0,0 +1,23 @@
+TARGET = thumbv8m.main-none-eabihf
+CHIP = STM32U575ZI
+BIN = stm32u5-blinky
+MODE ?= release
+TARGET_DIR = target/$(TARGET)/$(MODE)
+ELF = $(TARGET_DIR)/$(BIN)
+PROBE = probe-rs
+
+.PHONY: all build flash clean empty
+
+all: build
+
+build:
+	cargo build --$(MODE)
+
+flash: build
+	$(PROBE) run --chip $(CHIP) $(ELF)
+
+empty:
+	$(PROBE) erase --chip $(CHIP)
+
+clean:
+	cargo clean

dma_gpio2/README.md

@@ -0,0 +1,232 @@
+# `app-template`
+
+> Quickly set up a [`probe-rs`] + [`defmt`] + [`flip-link`] embedded project
+
+[`probe-rs`]: https://crates.io/crates/probe-rs
+[`defmt`]: https://github.com/knurling-rs/defmt
+[`flip-link`]: https://github.com/knurling-rs/flip-link
+
+## Dependencies
+
+### 1. `flip-link`:
+
+```bash
+cargo install flip-link
+```
+
+### 2. `probe-rs`:
+
+Install probe-rs by following the instructions at <https://probe.rs/docs/getting-started/installation/>.
+
+### 3. [`cargo-generate`]:
+
+```bash
+cargo install cargo-generate
+```
+
+[`cargo-generate`]: https://crates.io/crates/cargo-generate
+
+> *Note:* You can also just clone this repository instead of using `cargo-generate`, but this involves additional manual adjustments.
+
+## Setup
+
+### 1. Initialize the project template
+
+```bash
+cargo generate \
+    --git https://github.com/knurling-rs/app-template \
+    --branch main \
+    --name my-app
+```
+
+If you look into your new `my-app` folder, you'll find that there are a few `TODO`s in the files marking the properties you need to set.
+
+Let's walk through them together now.
+
+### 2. Set `probe-rs` chip
+
+Pick a chip from ` probe-rs chip list` and enter it into `.cargo/config.toml`.
+
+If, for example, you have a nRF52840 Development Kit as used in one of [our exercises], replace `{{chip}}` with `nRF52840_xxAA`.
+
+[our workshops]: https://rust-exercises.ferrous-systems.com
+
+```diff
+ # .cargo/config.toml
+-runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format=oneline"]
++runner = ["probe-rs", "run", "--chip", "nRF52840_xxAA", "--log-format=oneline"]
+```
+
+### 3. Adjust the compilation target
+
+In `.cargo/config.toml`, pick the right compilation target for your board.
+
+```diff
+ # .cargo/config.toml
+ [build]
+-target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
+-# target = "thumbv7m-none-eabi"    # Cortex-M3
+-# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
+-# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
++target = "thumbv7em-none-eabihf" # Cortex-M4F (with FPU)
+```
+
+Add the target with `rustup`.
+
+```bash
+rustup target add thumbv7em-none-eabihf
+```
+
+### 4. Add a HAL as a dependency
+
+In `Cargo.toml`, list the Hardware Abstraction Layer (HAL) for your board as a dependency.
+
+For the nRF52840 you'll want to use the [`nrf52840-hal`].
+
+[`nrf52840-hal`]: https://crates.io/crates/nrf52840-hal
+
+```diff
+ # Cargo.toml
+ [dependencies]
+-# some-hal = "1.2.3"
++nrf52840-hal = "0.14.0"
+```
+
+⚠️ Note for RP2040 users ⚠️
+
+You will need to not just specify the `rp-hal` HAL, but a BSP (board support crate) which includes a second stage bootloader. Please find a list of available BSPs [here](https://github.com/rp-rs/rp-hal-boards#packages).
+
+### 5. Import your HAL
+
+Now that you have selected a HAL, fix the HAL import in `src/lib.rs`
+
+```diff
+ // my-app/src/lib.rs
+-// use some_hal as _; // memory layout
++use nrf52840_hal as _; // memory layout
+```
+
+### (6. Get a linker script)
+
+Some HAL crates require that you manually copy over a file called `memory.x` from the HAL to the root of your project. For nrf52840-hal, this is done automatically so no action is needed. For other HAL crates, see their documentation on where to find an example file.
+
+The `memory.x` file should look something like:
+
+```text
+MEMORY
+{
+  FLASH : ORIGIN = 0x00000000, LENGTH = 1024K
+  RAM   : ORIGIN = 0x20000000, LENGTH = 256K
+}
+```
+
+The `memory.x` file is included in the `cortex-m-rt` linker script `link.x`, and so `link.x` is the one you should tell `rustc` to use (see the `.cargo/config.toml` file where we do that).
+
+### 7. Run!
+
+You are now all set to `cargo-run` your first `defmt`-powered application!
+There are some examples in the `src/bin` directory.
+
+Start by `cargo run`-ning `my-app/src/bin/hello.rs`:
+
+```console
+$ # `rb` is an alias for `run --bin`
+$ cargo rb hello
+    Finished `dev` profile [optimized + debuginfo] target(s) in 0.01s
+     Running `probe-rs run --chip nrf52840_xxaa --log-format=oneline target/thumbv6m-none-eabi/debug/hello`
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.79 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+Hello, world!
+
+$ echo $?
+0
+```
+
+If you're running out of memory (`flip-link` bails with an overflow error), you can decrease the size of the device memory buffer by setting the `DEFMT_RTT_BUFFER_SIZE` environment variable. The default value is 1024 bytes, and powers of two should be used for optimal performance:
+
+```console
+$ DEFMT_RTT_BUFFER_SIZE=64 cargo rb hello
+```
+
+### (8. Set `rust-analyzer.linkedProjects`)
+
+If you are using [rust-analyzer] with VS Code for IDE-like features you can add following configuration to your `.vscode/settings.json` to make it work transparently across workspaces. Find the details of this option in the [RA docs].
+
+```json
+{
+    "rust-analyzer.linkedProjects": [
+        "Cargo.toml",
+        "firmware/Cargo.toml",
+    ]
+}
+```
+
+[RA docs]: https://rust-analyzer.github.io/manual.html#configuration
+[rust-analyzer]: https://rust-analyzer.github.io/
+
+## Running tests
+
+The template comes configured for running unit tests and integration tests on the target.
+
+Unit tests reside in the library crate and can test private API; the initial set of unit tests are in `src/lib.rs`.
+`cargo test --lib` will run those unit tests.
+
+```console
+$ cargo test --lib
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.15s
+     Running unittests src/lib.rs (target/thumbv6m-none-eabi/debug/deps/example-2b0d0e25d141bf57)
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.99 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.33 KiB/s (took 1s)                                                                                                                        Finished in 1.10s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Integration tests reside in the `tests` directory; the initial set of integration tests are in `tests/integration.rs`.
+`cargo test --test integration` will run those integration tests.
+Note that the argument of the `--test` flag must match the name of the test file in the `tests` directory.
+
+```console
+$ cargo test --test integration
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.10s
+     Running tests/integration.rs (target/thumbv6m-none-eabi/debug/deps/integration-aaaff41151f6a722)
+      Erasing ✔ 100% [####################]   8.00 KiB @  16.03 KiB/s (took 0s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Note that to add a new test file to the `tests` directory you also need to add a new `[[test]]` section to `Cargo.toml`.
+
+To run all the tests via `cargo test` the tests need to be explicitly disabled for all the existing binary targets.
+See `Cargo.toml` for details on how to do this.
+
+## Support
+
+`app-template` is part of the [Knurling] project, [Ferrous Systems]' effort at
+improving tooling used to develop for embedded systems.
+
+If you think that our work is useful, consider sponsoring it via [GitHub
+Sponsors].
+
+## License
+
+Licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+  http://www.apache.org/licenses/LICENSE-2.0)
+
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+### Contribution
+
+Unless you explicitly state otherwise, any contribution intentionally submitted
+for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
+licensed as above, without any additional terms or conditions.
+
+[Knurling]: https://knurling.ferrous-systems.com
+[Ferrous Systems]: https://ferrous-systems.com/
+[GitHub Sponsors]: https://github.com/sponsors/knurling-rs

dma_gpio2/src/bin/main.rs

@@ -0,0 +1,165 @@
+// src/bin/main.rs
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_futures::yield_now;
+use embassy_stm32::dma::Request;
+use embassy_stm32::gpio::{Input, Output, Level, Pull, Speed};
+use embassy_time::{Duration, Timer};
+use embassy_stm32::dma::{TransferOptions, WritableRingBuffer};
+use dma_gpio::software_uart::{
+    dma_timer::init_tim6_for_uart,
+    gpio_dma_uart_tx::encode_uart_frames,
+    debug::dump_tim6_regs,
+};
+use dma_gpio::config::{BAUD, TX_PIN_BIT, TX_OVERSAMPLE, TX_RING_BYTES};
+use static_cell::StaticCell;
+use {defmt_rtt as _, panic_probe as _};
+
+pub const TIM6_UP_REQ: Request = 4;
+
+static TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_stm32::init(Default::default());
+    info!("Hehe");
+
+    let _rx = Input::new(p.PA3, embassy_stm32::gpio::Pull::Up);
+    let _tx = Output::new(p.PA2, Level::High, Speed::VeryHigh);
+
+    init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE);
+    dump_tim6_regs();
+
+    let idle: u32 = 1u32 << TX_PIN_BIT;
+
+    // Ring initialized to idle (line high).
+    let tx_ring_mem: &mut [u32; TX_RING_BYTES] = TX_RING.init([0; TX_RING_BYTES]);
+
+    let odr_ptr = embassy_stm32::pac::GPIOA.odr().as_ptr() as *mut u32;
+
+    let mut tx_opts = TransferOptions::default();
+    tx_opts.half_transfer_ir = true;
+    tx_opts.complete_transfer_ir = true;
+
+    let mut tx_ring = unsafe {
+        WritableRingBuffer::new(
+            p.GPDMA1_CH0,
+            TIM6_UP_REQ,
+            odr_ptr,
+            tx_ring_mem,
+            tx_opts,
+        )
+    };
+
+    {
+        // Full idle buffer matching ring capacity.
+        let idle_buf = [idle; TX_RING_BYTES];
+
+        let written = tx_ring
+            .write_exact(&idle_buf)
+            .await
+            .expect("Failed to prefill TX ring with idle");
+
+        info!(
+            "TX ring prefilled with idle via write_exact: written={} cap={}",
+            written,
+            tx_ring.capacity()
+        );
+    }
+
+    tx_ring.start();
+    info!(
+        "TX DMA ring started: cap_words={}",
+        tx_ring.capacity()
+    );
+    unsafe {
+        use embassy_stm32::pac::gpdma::Gpdma;
+        let dma = Gpdma::from_ptr(0x4002_0000 as _); // GPDMA1 base for STM32U5
+        let ch = dma.ch(0); // Channel 0
+
+        let cr = ch.cr().read();
+        let tr1 = ch.tr1().read();
+        let tr2 = ch.tr2().read();
+        let br1 = ch.br1().read();
+        let sar = ch.sar().read();
+        let dar = ch.dar().read();
+        let llr = ch.llr().read();
+        let lbar = ch.lbar().read();
+
+        info!(
+            "GPDMA1_CH0: EN={} HTIE={} TCIE={} SDW={:?} DDW={:?} SINC={} DINC={} BNDT={} SAR=0x{:08x} DAR=0x{:08x}",
+            cr.en(),
+            cr.htie(),
+            cr.tcie(),
+            tr1.sdw(),
+            tr1.ddw(),
+            tr1.sinc(),
+            tr1.dinc(),
+            br1.bndt(),
+            sar, // already u32
+            dar, // already u32
+        );
+        info!(
+            "GPDMA1_CH0: LBAR=0x{:08x} LLR=0x{:08x}",
+            lbar.lba(),
+            llr.0
+        );
+    }
+
+    let mut frame_buf = [0u32; 4096];
+
+    loop {
+        info!("tick start");
+        Timer::after(Duration::from_millis(1021)).await;
+        //info!("tick end");
+
+        let used = encode_uart_frames(
+            TX_PIN_BIT,
+            b"H\r\n",
+            &mut frame_buf,
+        )
+        .await;
+
+        if used == 0 {
+            info!("encode_uart_frames() produced 0 words, skipping write");
+            yield_now().await;
+            continue;
+        }
+
+        // Debug: confirm encoded content.
+        let preview = core::cmp::min(used, 32);
+        info!(
+            "TX frame used={} words, head={=[?]}",
+            used,
+            &frame_buf[..preview]
+        );
+
+        // Now it is safe to call write_exact.
+        match tx_ring.write_exact(&frame_buf[..used]).await {
+            Ok(written) => {
+                let len = tx_ring.len().unwrap_or(0);
+                info!(
+                    "write_exact ok: written={} ring_used={} ring_cap={}",
+                    written,
+                    len,
+                    tx_ring.capacity()
+                );
+            }
+            Err(e) => {
+                let len = tx_ring.len().unwrap_or(0);
+                warn!(
+                    "write_exact error: {:?}, ring_used={} ring_cap={}",
+                    e,
+                    len,
+                    tx_ring.capacity()
+                );
+            }
+        }
+
+        info!("tick end");
+        yield_now().await;
+    }
+}

dma_gpio2/src/config.rs

@@ -0,0 +1,16 @@
+// src/config.rs
+use crate::software_uart::uart_emulation::{Parity, StopBits, UartConfig};
+
+pub const BAUD: u32 = 9_600;
+pub const TX_PIN_BIT: u8 = 2; // PA2
+pub const TX_OVERSAMPLE: u16 = 1;
+pub const RX_OVERSAMPLE: u16 = 16;
+pub const RX_RING_BYTES: usize = 4096;
+pub const TX_RING_BYTES: usize = 4096;
+pub const PIPE_RX_SIZE: usize = 256;
+
+pub const UART_CFG: UartConfig = UartConfig {
+    data_bits: 8,
+    parity: Parity::None,
+    stop_bits: StopBits::One,
+};

dma_gpio2/src/lib.rs

@@ -0,0 +1,4 @@
+#![no_std]
+
+pub mod software_uart;
+pub mod config;

dma_gpio2/src/software_uart/debug.rs

@@ -0,0 +1,43 @@
+// src/software_uart/debug.rs
+use defmt::info;
+
+pub fn dump_tim6_regs() {
+    use embassy_stm32::pac::timer::TimBasic;
+    let tim = unsafe { TimBasic::from_ptr(0x4000_1000usize as _) };
+    let sr = tim.sr().read();
+    let dier = tim.dier().read();
+    let cr1 = tim.cr1().read();
+    let arr = tim.arr().read().arr();
+    let psc = tim.psc().read();
+    info!(
+        "TIM6: CR1.CEN={} DIER.UDE={} SR.UIF={} PSC={} ARR={}",
+        cr1.cen(),
+        dier.ude(),
+        sr.uif(),
+        psc,
+        arr
+    );
+}
+
+pub fn dump_dma_ch0_regs() {
+    use embassy_stm32::pac::gpdma::Gpdma;
+    let dma = unsafe { Gpdma::from_ptr(0x4002_0000usize as _) };
+    let ch = dma.ch(0);
+    let cr = ch.cr().read();
+    let tr1 = ch.tr1().read();
+    let tr2 = ch.tr2().read();
+    let br1 = ch.br1().read();
+    info!(
+        "GPDMA1_CH0: EN={} PRIO={} SDW={} DDW={} SINC={} DINC={} REQSEL={} SWREQ={} DREQ={} BNDT={}",
+        cr.en(),
+        cr.prio(),
+        tr1.sdw(),
+        tr1.ddw(),
+        tr1.sinc(),
+        tr1.dinc(),
+        tr2.reqsel(),
+        tr2.swreq(),
+        tr2.dreq(),
+        br1.bndt()
+    );
+}

dma_gpio2/src/software_uart/dma_timer.rs

@@ -0,0 +1,49 @@
+// src/dma_timer.rs
+
+use embassy_stm32::{
+    peripherals::TIM6,
+    rcc,
+    timer::low_level::Timer,
+    Peri,
+};
+use core::mem;
+use embassy_stm32::timer::BasicInstance;
+use embassy_stm32::pac::timer::vals::Urs;
+
+/// Initializes TIM6 to tick at `baud * oversample` frequency.
+/// Each TIM6 update event triggers one DMA beat.
+pub fn init_tim6_for_uart<'d>(tim6: Peri<'d, TIM6>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM6>();
+    let ll = Timer::new(tim6);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+// Shared internal helper — identical CR1/ARR setup
+fn configure_basic_timer<T: BasicInstance>(ll: &Timer<'_, T>, baud: u32, oversample: u16) {
+    let f_timer = rcc::frequency::<T>().0;
+    let target = baud.saturating_mul(oversample.max(1) as u32).max(1);
+
+    // Compute ARR (prescaler = 0)
+    let mut arr = (f_timer / target).saturating_sub(1) as u16;
+    if arr == 0 { arr = 1; }
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_cen(false);
+        w.set_opm(false);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+
+    ll.regs_basic().psc().write_value(0u16);
+    ll.regs_basic().arr().write(|w| w.set_arr(arr));
+    ll.regs_basic().dier().modify(|w| w.set_ude(true));
+    ll.regs_basic().egr().write(|w| w.set_ug(true));
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_opm(false);
+        w.set_cen(true);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+}

dma_gpio2/src/software_uart/gpio_dma_uart_tx.rs

@@ -0,0 +1,27 @@
+// src/software_uart/gpio_dma_uart_tx.rs
+use embassy_futures::yield_now;
+use crate::software_uart::uart_emulation::encode_uart_byte_cfg;
+use crate::config::UART_CFG;
+
+pub async fn encode_uart_frames<'a>(
+    pin_bit: u8,
+    bytes: &[u8],
+    out_buf: &'a mut [u32],
+) -> usize {
+    let mut offset = 0;
+    for &b in bytes {
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(pin_bit, b, &UART_CFG, &mut frame);
+
+        if offset + used <= out_buf.len() {
+            out_buf[offset..offset + used].copy_from_slice(&frame[..used]);
+            offset += used;
+        } else {
+            break;
+        }
+
+        // cooperative async yield
+        yield_now().await;
+    }
+    offset
+}

dma_gpio2/src/software_uart/mod.rs

@@ -0,0 +1,11 @@
+// src/software_uart/mod.rs
+
+pub mod gpio_dma_uart_tx;
+pub mod dma_timer;
+pub mod uart_emulation;
+pub mod debug;
+
+pub use gpio_dma_uart_tx::*;
+pub use dma_timer::*;
+pub use uart_emulation::*;
+pub use debug::*;

dma_gpio2/src/software_uart/uart_emulation.rs

@@ -0,0 +1,151 @@
+// src/software_uart/uart_emulation.rs
+use heapless::Vec;
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Parity {
+    None,
+    Even,
+    Odd,
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum StopBits {
+    One,
+    Two,
+}
+
+#[derive(Clone, Copy, Debug)]
+pub struct UartConfig {
+    pub data_bits: u8,
+    pub parity: Parity,
+    pub stop_bits: StopBits,
+}
+
+impl Default for UartConfig {
+    fn default() -> Self {
+        Self {
+            data_bits: 8,
+            parity: Parity::None,
+            stop_bits: StopBits::One,
+        }
+    }
+}
+
+/// Encodes one byte into a sequence of GPIO BSRR words
+pub fn encode_uart_byte_cfg(
+    pin_bit: u8,
+    data: u8,
+    cfg: &UartConfig,
+    out: &mut [u32; 12],
+) -> usize {
+    // GPIOx_BSRR register str. 636 kap. 13.4.7
+    let set_high = |bit: u8| -> u32 { 1u32 << bit };
+    let set_low = |bit: u8| -> u32 { 0 };
+    // let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) };
+
+    let mut idx = 0usize;
+
+    // START bit (LOW)
+    out[idx] = set_low(pin_bit);
+    idx += 1;
+
+    // Data bits, LSB-first
+    let nbits = cfg.data_bits.clamp(5, 8);
+    for i in 0..nbits {
+        let one = ((data >> i) & 1) != 0;
+        out[idx] = if one { set_high(pin_bit) } else { set_low(pin_bit) };
+        idx += 1;
+    }
+
+    // Parity
+    match cfg.parity {
+        Parity::None => {}
+        Parity::Even | Parity::Odd => {
+            let mask: u8 = if nbits == 8 { 0xFF } else { (1u16 << nbits) as u8 - 1 };
+            let ones = (data & mask).count_ones() & 1;
+            let par_bit_is_one = match cfg.parity {
+                Parity::Even => ones == 1,
+                Parity::Odd => ones == 0,
+                _ => false,
+            };
+            out[idx] = if par_bit_is_one {
+                set_high(pin_bit)
+            } else {
+                set_low(pin_bit)
+            };
+            idx += 1;
+        }
+    }
+
+    // STOP bits (HIGH)
+    let stop_ticks = match cfg.stop_bits {
+        StopBits::One => 1usize,
+        StopBits::Two => 2usize,
+    };
+    for _ in 0..stop_ticks {
+        out[idx] = set_high(pin_bit);
+        idx += 1;
+    }
+
+    idx
+}
+
+/// Decode an oversampled stream of logic levels into UART bytes.
+pub fn decode_uart_samples(
+    samples: &[u8],
+    oversample: u16,
+    cfg: &UartConfig,
+) -> heapless::Vec<u8, 256> {
+
+    let mut out = Vec::<u8, 256>::new();
+    let mut idx = 0usize;
+    let nbits = cfg.data_bits as usize;
+
+    while idx + (oversample as usize * (nbits + 3)) < samples.len() {
+        // Wait for start bit (falling edge: high -> low)
+        if samples[idx] != 0 && samples[idx + 1] == 0 {
+            // Align to middle of start bit
+            idx += (oversample / 2) as usize;
+
+            // Sanity check start bit really low
+            if samples.get(idx).copied().unwrap_or(1) != 0 {
+                idx += 1;
+                continue;
+            }
+
+            // Sample data bits
+            let mut data: u8 = 0;
+            for bit in 0..nbits {
+                idx += oversample as usize;
+                let bit_val = samples
+                    .get(idx)
+                    .map(|&b| if b != 0 { 1u8 } else { 0u8 })
+                    .unwrap_or(1);
+                data |= bit_val << bit;
+            }
+
+            // Parity: skip / verify
+            match cfg.parity {
+                Parity::None => {}
+                Parity::Even | Parity::Odd => {
+                    idx += oversample as usize;
+                    // You can optionally add parity check here if needed
+                }
+            }
+
+            // Move past stop bits
+            let stop_skip = match cfg.stop_bits {
+                StopBits::One => oversample as usize,
+                StopBits::Two => (oversample * 2) as usize,
+            };
+            idx += stop_skip;
+
+            // Push decoded byte
+            let _ = out.push(data);
+        } else {
+            idx += 1;
+        }
+    }
+
+    out
+}

dma_gpio2/tests/integration.rs

@@ -0,0 +1,16 @@
+#![no_std]
+#![no_main]
+
+use stm32u5_blinky as _; // memory layout + panic handler
+
+// See https://crates.io/crates/defmt-test/0.3.0 for more documentation (e.g. about the 'state'
+// feature)
+#[defmt_test::tests]
+mod tests {
+    use defmt::assert;
+
+    #[test]
+    fn it_works() {
+        assert!(true)
+    }
+}

semestralka_1/.cargo/config.toml

@@ -0,0 +1,15 @@
+[build]
+target = "thumbv8m.main-none-eabihf"
+
+[target.thumbv8m.main-none-eabihf]
+runner = "probe-rs run --chip STM32U575ZITxQ"
+
+rustflags = [
+  "-C", "linker=rust-lld",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "link-arg=-Tdefmt.x",
+  "-C", "link-arg=--nmagic",
+]
+
+[package.metadata.cargo-flash]
+chip = "STM32U575ZIT"

semestralka_1/.gitignore

@@ -0,0 +1 @@
+/target

semestralka_1/Cargo.toml

@@ -0,0 +1,46 @@
+[package]
+authors = ["Priec <filippriec@gmail.com>"]
+name = "dma_gpio"
+edition = "2024"
+version = "0.1.0"
+
+
+[dependencies]
+cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.5"
+panic-halt = "1.0.0"
+
+embassy-executor = { git = "https://github.com/embassy-rs/embassy.git", branch = "main", features = ["arch-cortex-m", "executor-thread"] }
+embassy-futures = { git = "https://github.com/embassy-rs/embassy.git", branch = "main" }
+embassy-sync    = { git = "https://github.com/embassy-rs/embassy.git", branch = "main" }
+embassy-time    = { git = "https://github.com/embassy-rs/embassy.git", branch = "main", features = ["tick-hz-32_768"] }
+embassy-hal-internal = { git = "https://github.com/embassy-rs/embassy.git", branch = "main" }
+embassy-usb = { git = "https://github.com/embassy-rs/embassy.git", branch = "main" }
+embassy-stm32 = { git = "https://github.com/embassy-rs/embassy.git", branch = "main", features = ["unstable-pac", "stm32u575zi", "time-driver-tim2", "memory-x", "defmt"] }
+
+embedded-hal = "1.0.0"
+embedded-graphics = "0.8.1"
+heapless = { version = "0.9.1", default-features = false }
+micromath = "2.1.0"
+tinybmp = "0.6.0"
+panic-probe = { version = "1.0.0", features = ["defmt"] }
+defmt-rtt = "1.1.0"
+defmt = "1.0.1"
+static_cell = "2.1.1"
+embedded-io = "0.6.1"
+embedded-io-async = "0.6.1"
+
+[dev-dependencies]
+defmt-test = "0.4.0"
+
+[[test]]
+name = "uart_emulation"
+harness = false
+
+[lib]
+test = false
+
+[[bin]]
+name = "main"
+path = "src/bin/main.rs"
+test = false

semestralka_1/LICENSE-APACHE

@@ -0,0 +1,201 @@
+                              Apache License
+                        Version 2.0, January 2004
+                     http://www.apache.org/licenses/
+
+TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+1. Definitions.
+
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+
+   "You" (or "Your") shall mean an individual or Legal Entity
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+8. Limitation of Liability. In no event and under no legal theory,
+   whether in tort (including negligence), contract, or otherwise,
+   unless required by applicable law (such as deliberate and grossly
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+END OF TERMS AND CONDITIONS
+
+APPENDIX: How to apply the Apache License to your work.
+
+   To apply the Apache License to your work, attach the following
+   boilerplate notice, with the fields enclosed by brackets "[]"
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+
+Unless required by applicable law or agreed to in writing, software
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+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.

semestralka_1/LICENSE-MIT

@@ -0,0 +1,23 @@
+Permission is hereby granted, free of charge, to any
+person obtaining a copy of this software and associated
+documentation files (the "Software"), to deal in the
+Software without restriction, including without
+limitation the rights to use, copy, modify, merge,
+publish, distribute, sublicense, and/or sell copies of
+the Software, and to permit persons to whom the Software
+is furnished to do so, subject to the following
+conditions:
+
+The above copyright notice and this permission notice
+shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
+ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
+IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.

semestralka_1/Makefile

@@ -0,0 +1,23 @@
+TARGET = thumbv8m.main-none-eabihf
+CHIP = STM32U575ZI
+BIN = stm32u5-blinky
+MODE ?= release
+TARGET_DIR = target/$(TARGET)/$(MODE)
+ELF = $(TARGET_DIR)/$(BIN)
+PROBE = probe-rs
+
+.PHONY: all build flash clean empty
+
+all: build
+
+build:
+	cargo build --$(MODE)
+
+flash: build
+	$(PROBE) run --chip $(CHIP) $(ELF)
+
+empty:
+	$(PROBE) erase --chip $(CHIP)
+
+clean:
+	cargo clean

semestralka_1/README.md

@@ -0,0 +1,232 @@
+# `app-template`
+
+> Quickly set up a [`probe-rs`] + [`defmt`] + [`flip-link`] embedded project
+
+[`probe-rs`]: https://crates.io/crates/probe-rs
+[`defmt`]: https://github.com/knurling-rs/defmt
+[`flip-link`]: https://github.com/knurling-rs/flip-link
+
+## Dependencies
+
+### 1. `flip-link`:
+
+```bash
+cargo install flip-link
+```
+
+### 2. `probe-rs`:
+
+Install probe-rs by following the instructions at <https://probe.rs/docs/getting-started/installation/>.
+
+### 3. [`cargo-generate`]:
+
+```bash
+cargo install cargo-generate
+```
+
+[`cargo-generate`]: https://crates.io/crates/cargo-generate
+
+> *Note:* You can also just clone this repository instead of using `cargo-generate`, but this involves additional manual adjustments.
+
+## Setup
+
+### 1. Initialize the project template
+
+```bash
+cargo generate \
+    --git https://github.com/knurling-rs/app-template \
+    --branch main \
+    --name my-app
+```
+
+If you look into your new `my-app` folder, you'll find that there are a few `TODO`s in the files marking the properties you need to set.
+
+Let's walk through them together now.
+
+### 2. Set `probe-rs` chip
+
+Pick a chip from ` probe-rs chip list` and enter it into `.cargo/config.toml`.
+
+If, for example, you have a nRF52840 Development Kit as used in one of [our exercises], replace `{{chip}}` with `nRF52840_xxAA`.
+
+[our workshops]: https://rust-exercises.ferrous-systems.com
+
+```diff
+ # .cargo/config.toml
+-runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format=oneline"]
++runner = ["probe-rs", "run", "--chip", "nRF52840_xxAA", "--log-format=oneline"]
+```
+
+### 3. Adjust the compilation target
+
+In `.cargo/config.toml`, pick the right compilation target for your board.
+
+```diff
+ # .cargo/config.toml
+ [build]
+-target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
+-# target = "thumbv7m-none-eabi"    # Cortex-M3
+-# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
+-# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
++target = "thumbv7em-none-eabihf" # Cortex-M4F (with FPU)
+```
+
+Add the target with `rustup`.
+
+```bash
+rustup target add thumbv7em-none-eabihf
+```
+
+### 4. Add a HAL as a dependency
+
+In `Cargo.toml`, list the Hardware Abstraction Layer (HAL) for your board as a dependency.
+
+For the nRF52840 you'll want to use the [`nrf52840-hal`].
+
+[`nrf52840-hal`]: https://crates.io/crates/nrf52840-hal
+
+```diff
+ # Cargo.toml
+ [dependencies]
+-# some-hal = "1.2.3"
++nrf52840-hal = "0.14.0"
+```
+
+⚠️ Note for RP2040 users ⚠️
+
+You will need to not just specify the `rp-hal` HAL, but a BSP (board support crate) which includes a second stage bootloader. Please find a list of available BSPs [here](https://github.com/rp-rs/rp-hal-boards#packages).
+
+### 5. Import your HAL
+
+Now that you have selected a HAL, fix the HAL import in `src/lib.rs`
+
+```diff
+ // my-app/src/lib.rs
+-// use some_hal as _; // memory layout
++use nrf52840_hal as _; // memory layout
+```
+
+### (6. Get a linker script)
+
+Some HAL crates require that you manually copy over a file called `memory.x` from the HAL to the root of your project. For nrf52840-hal, this is done automatically so no action is needed. For other HAL crates, see their documentation on where to find an example file.
+
+The `memory.x` file should look something like:
+
+```text
+MEMORY
+{
+  FLASH : ORIGIN = 0x00000000, LENGTH = 1024K
+  RAM   : ORIGIN = 0x20000000, LENGTH = 256K
+}
+```
+
+The `memory.x` file is included in the `cortex-m-rt` linker script `link.x`, and so `link.x` is the one you should tell `rustc` to use (see the `.cargo/config.toml` file where we do that).
+
+### 7. Run!
+
+You are now all set to `cargo-run` your first `defmt`-powered application!
+There are some examples in the `src/bin` directory.
+
+Start by `cargo run`-ning `my-app/src/bin/hello.rs`:
+
+```console
+$ # `rb` is an alias for `run --bin`
+$ cargo rb hello
+    Finished `dev` profile [optimized + debuginfo] target(s) in 0.01s
+     Running `probe-rs run --chip nrf52840_xxaa --log-format=oneline target/thumbv6m-none-eabi/debug/hello`
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.79 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+Hello, world!
+
+$ echo $?
+0
+```
+
+If you're running out of memory (`flip-link` bails with an overflow error), you can decrease the size of the device memory buffer by setting the `DEFMT_RTT_BUFFER_SIZE` environment variable. The default value is 1024 bytes, and powers of two should be used for optimal performance:
+
+```console
+$ DEFMT_RTT_BUFFER_SIZE=64 cargo rb hello
+```
+
+### (8. Set `rust-analyzer.linkedProjects`)
+
+If you are using [rust-analyzer] with VS Code for IDE-like features you can add following configuration to your `.vscode/settings.json` to make it work transparently across workspaces. Find the details of this option in the [RA docs].
+
+```json
+{
+    "rust-analyzer.linkedProjects": [
+        "Cargo.toml",
+        "firmware/Cargo.toml",
+    ]
+}
+```
+
+[RA docs]: https://rust-analyzer.github.io/manual.html#configuration
+[rust-analyzer]: https://rust-analyzer.github.io/
+
+## Running tests
+
+The template comes configured for running unit tests and integration tests on the target.
+
+Unit tests reside in the library crate and can test private API; the initial set of unit tests are in `src/lib.rs`.
+`cargo test --lib` will run those unit tests.
+
+```console
+$ cargo test --lib
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.15s
+     Running unittests src/lib.rs (target/thumbv6m-none-eabi/debug/deps/example-2b0d0e25d141bf57)
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.99 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.33 KiB/s (took 1s)                                                                                                                        Finished in 1.10s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Integration tests reside in the `tests` directory; the initial set of integration tests are in `tests/integration.rs`.
+`cargo test --test integration` will run those integration tests.
+Note that the argument of the `--test` flag must match the name of the test file in the `tests` directory.
+
+```console
+$ cargo test --test integration
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.10s
+     Running tests/integration.rs (target/thumbv6m-none-eabi/debug/deps/integration-aaaff41151f6a722)
+      Erasing ✔ 100% [####################]   8.00 KiB @  16.03 KiB/s (took 0s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Note that to add a new test file to the `tests` directory you also need to add a new `[[test]]` section to `Cargo.toml`.
+
+To run all the tests via `cargo test` the tests need to be explicitly disabled for all the existing binary targets.
+See `Cargo.toml` for details on how to do this.
+
+## Support
+
+`app-template` is part of the [Knurling] project, [Ferrous Systems]' effort at
+improving tooling used to develop for embedded systems.
+
+If you think that our work is useful, consider sponsoring it via [GitHub
+Sponsors].
+
+## License
+
+Licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+  http://www.apache.org/licenses/LICENSE-2.0)
+
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+### Contribution
+
+Unless you explicitly state otherwise, any contribution intentionally submitted
+for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
+licensed as above, without any additional terms or conditions.
+
+[Knurling]: https://knurling.ferrous-systems.com
+[Ferrous Systems]: https://ferrous-systems.com/
+[GitHub Sponsors]: https://github.com/sponsors/knurling-rs

semestralka_1/src/bin/main.rs

@@ -0,0 +1,142 @@
+// src/bin/main.rs
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_time::Instant;
+use embassy_executor::task;
+use embassy_stm32::dma::Request;
+use embassy_stm32::gpio::{Input, Output, Level, Pull, Speed};
+use dma_gpio::software_uart::{
+    dma_timer::{init_tim6_for_uart, init_tim7_for_uart},
+    gpio_dma_uart_rx::rx_dma_task,
+    debug::dump_tim6_regs,
+};
+use dma_gpio::config::{BAUD, RX_OVERSAMPLE, TX_OVERSAMPLE};
+use dma_gpio::config::{TX_RING_BYTES, RX_RING_BYTES};
+use dma_gpio::software_uart::gpio_dma_uart_tx::tx_dma_task;
+use static_cell::StaticCell;
+use embassy_futures::yield_now;
+use dma_gpio::hw_uart_pc::usart1;
+use dma_gpio::hw_uart_pc::driver::uart_task;
+use embassy_stm32::usart::{BufferedUart, Config, BufferedInterruptHandler};
+use embassy_stm32::peripherals;
+use embassy_stm32::bind_interrupts;
+use dma_gpio::config::{PIPE_HW_TX, PIPE_HW_RX, PIPE_SW_TX, PIPE_SW_RX};
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    USART1 => BufferedInterruptHandler<peripherals::USART1>;
+});
+
+// Software uart
+pub const TIM6_UP_REQ: Request = 4;
+static SW_TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
+static SW_RX_RING: StaticCell<[u8; RX_RING_BYTES]> = StaticCell::new();
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    info!("boot");
+    let p = embassy_stm32::init(Default::default());
+    info!("init m8");
+
+    // HARDWARE UART to the PC
+    let mut cfg = Config::default();
+    cfg.baudrate = BAUD;
+    static TX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
+    static RX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
+    let uart = BufferedUart::new(
+        p.USART1,
+        p.PA10, // RX pin
+        p.PA9,  // TX pin
+        TX_BUF.init([0; 256]),
+        RX_BUF.init([0; 256]),
+        Irqs,
+        cfg,
+    ).unwrap();
+    let yield_period = usart1::setup_and_spawn(BAUD);
+    spawner.spawn(uart_task(uart, &PIPE_HW_TX, &PIPE_HW_RX).unwrap());
+    // END OF HARDWARE UART to the PC
+
+    // SOFTWARE UART 
+    let _rx = Input::new(p.PA3, Pull::Up);
+    let _tx = Output::new(p.PA2, Level::High, Speed::VeryHigh);
+    init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE);
+    init_tim7_for_uart(p.TIM7, BAUD, RX_OVERSAMPLE);
+    dump_tim6_regs();
+
+    // Safe one-time init from StaticCell
+    let sw_rx_ring: &mut [u8; RX_RING_BYTES] = SW_RX_RING.init([0; RX_RING_BYTES]);
+    let sw_tx_ring: &mut [u32; TX_RING_BYTES] = SW_TX_RING.init([0; TX_RING_BYTES]);
+    spawner.spawn(rx_dma_task(p.GPDMA1_CH1, sw_rx_ring, &PIPE_SW_RX).unwrap());
+
+    // Create and start the TX DMA ring in main.
+    let bsrr_ptr = embassy_stm32::pac::GPIOA.bsrr().as_ptr() as *mut u32;
+    // let odr_ptr = embassy_stm32::pac::GPIOA.odr().as_ptr() as *mut u32; // NEEDS DECODE CHANGE
+    spawner.spawn(tx_dma_task(p.GPDMA1_CH0, bsrr_ptr, sw_tx_ring, &PIPE_SW_TX).unwrap());
+    // EDN OF SOFTWARE UART 
+
+
+    // BRIDGE
+    spawner.spawn(bridge_hw_to_sw(&PIPE_HW_RX, &PIPE_SW_TX).unwrap());
+    spawner.spawn(bridge_sw_to_hw(&PIPE_SW_RX, &PIPE_HW_TX).unwrap());
+    // END OF BRIDGE
+    
+    let mut last_yield = Instant::now();
+    let mut buf = [0u8; 32];
+
+    loop {
+        info!("tick start");
+        // Timer::after(Duration::from_millis(100)).await;
+        // info!("tick end");
+
+        let n1 = PIPE_HW_RX.read(&mut buf).await;
+        if n1 > 0 {
+            info!("PC received: {:a}", &buf[..n1]);
+            let _ = PIPE_SW_TX.write(&buf[..n1]).await;
+            info!("SW UART TX sent echo: {:a}", &buf[..n1]);
+        }
+        yield_now().await;
+
+        let n2 = PIPE_SW_RX.read(&mut buf).await;
+        if n2 > 0 {
+            info!("SW UART RX received: {:a}", &buf[..n2]);
+        }
+
+        if Instant::now().duration_since(last_yield) >= yield_period {
+            yield_now().await;
+            last_yield = Instant::now();
+        }
+
+    }
+}
+
+#[task]
+pub async fn bridge_hw_to_sw(
+    hw_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+    sw_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut buf = [0u8; 64];
+    loop {
+        let n = hw_rx.read(&mut buf).await;
+        if n > 0 {
+            let _ = sw_tx.write(&buf[..n]).await;
+        }
+    }
+}
+
+#[task]
+pub async fn bridge_sw_to_hw(
+    sw_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+    hw_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut buf = [0u8; 64];
+    loop {
+        let n = sw_rx.read(&mut buf).await;
+        if n > 0 {
+            let _ = hw_tx.write(&buf[..n]).await;
+        }
+    }
+}

semestralka_1/src/config.rs

@@ -0,0 +1,29 @@
+// src/config.rs
+use crate::software_uart::uart_emulation::{Parity, StopBits, UartConfig};
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+
+pub const BAUD: u32 = 9_600;
+pub const TX_PIN_BIT: u8 = 2; // PA2
+pub const RX_PIN_BIT: u8 = 3; // PA3
+pub const TX_OVERSAMPLE: u16 = 1;
+pub const RX_OVERSAMPLE: u16 = 16;
+
+pub const RX_RING_BYTES: usize = 4096;
+pub const TX_RING_BYTES: usize = 4096;
+
+pub const PIPE_HW_TX_SIZE: usize = 1024;
+pub const PIPE_HW_RX_SIZE: usize = 1024;
+pub const PIPE_SW_TX_SIZE: usize = 1024;
+pub const PIPE_SW_RX_SIZE: usize = 1024;
+
+pub static PIPE_HW_TX: Pipe<CriticalSectionRawMutex, PIPE_HW_TX_SIZE> = Pipe::new();
+pub static PIPE_HW_RX: Pipe<CriticalSectionRawMutex, PIPE_HW_RX_SIZE> = Pipe::new();
+pub static PIPE_SW_TX: Pipe<CriticalSectionRawMutex, PIPE_SW_TX_SIZE> = Pipe::new();
+pub static PIPE_SW_RX: Pipe<CriticalSectionRawMutex, PIPE_SW_RX_SIZE> = Pipe::new();
+
+pub const UART_CFG: UartConfig = UartConfig {
+    data_bits: 8,
+    parity: Parity::None,
+    stop_bits: StopBits::One,
+};

semestralka_1/src/hw_uart_pc/driver.rs

@@ -0,0 +1,39 @@
+// src/hw_uart_pc/driver.rs
+use defmt::unwrap;
+use embassy_futures::select::{select, Either};
+use embassy_stm32::usart::BufferedUart;
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+use embedded_io_async::{Read, Write};
+use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
+
+#[embassy_executor::task]
+pub async fn uart_task(
+    mut uart: BufferedUart<'static>,
+    tx_pipe: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
+    rx_pipe: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
+) {
+    let mut rx_byte = [0u8; 1];
+    let mut tx_buf = [0u8; 64];
+
+    loop {
+        let rx_fut = uart.read(&mut rx_byte);
+        let tx_fut = async {
+            let n = tx_pipe.read(&mut tx_buf).await;
+            n
+        };
+
+        match select(rx_fut, tx_fut).await {
+            // Incoming data from UART hardware
+            Either::First(res) => {
+                if let Ok(_) = res {
+                    let _ = rx_pipe.write(&rx_byte).await;
+                }
+            }
+            // Outgoing data waiting in TX pipe
+            Either::Second(n) => {
+                unwrap!(uart.write(&tx_buf[..n]).await);
+            }
+        }
+    }
+}

semestralka_1/src/hw_uart_pc/mod.rs

@@ -0,0 +1,4 @@
+// src/uart/mod.rs
+pub mod driver;
+pub mod usart1;
+pub mod safety;

semestralka_1/src/hw_uart_pc/safety.rs

@@ -0,0 +1,57 @@
+// src/safety.rs
+use defmt::info;
+use embassy_time::Duration;
+
+// ISR RX ring capacity = RX_BUF len
+const ISR_RX_BUF_CAP: usize = 256;
+// Yield 1/2 the time it takes to fill ISR RX ring.
+const YIELD_MARGIN_NUM: u32 = 1;
+const YIELD_MARGIN_DEN: u32 = 2;
+// Ensure RX_PIPE_CAP can hold this.
+const WORST_MAIN_LATENCY_MS: u32 = 20;
+
+pub const TX_PIPE_CAP: usize = 1024;
+pub const RX_PIPE_CAP: usize = 1024;
+
+
+
+/// Perform safety checks and compute yield timing to avoid buffer overflow.
+///
+/// # Panics
+/// Panics if pipe capacities are too small for the configured baud.
+pub fn preflight_and_suggest_yield_period(baud: u32) -> Duration {
+    // Approx bytes per second for 8N1 (10 bits per byte on the wire)
+    let bytes_per_sec = (baud / 10).max(1);
+
+    // Time until ISR RX ring fills, in microseconds.
+    let t_fill_us = (ISR_RX_BUF_CAP as u64) * 1_000_000u64 / (bytes_per_sec as u64);
+
+    // Choose a yield period as a fraction of t_fill.
+    let yield_us = (t_fill_us as u64)
+        .saturating_mul(YIELD_MARGIN_NUM as u64)
+        / (YIELD_MARGIN_DEN as u64);
+
+    // Verify RX pipe can absorb a worst-case app latency so uart_task
+    // can always forward without dropping when it runs.
+    let required_rx_pipe = (bytes_per_sec as u64) * (WORST_MAIN_LATENCY_MS as u64) / 1000;
+
+    if (RX_PIPE_CAP as u64) < required_rx_pipe {
+        core::panic!(
+            "RX pipe too small: have {}B, need >= {}B for {}ms at {} bps",
+            RX_PIPE_CAP, required_rx_pipe, WORST_MAIN_LATENCY_MS, baud
+        );
+    }
+
+    info!(
+        "Preflight: baud={}, rx_isr={}B, rx_pipe={}B, bytes/s={}, t_fill_us={}, yield_us={}",
+        baud,
+        ISR_RX_BUF_CAP,
+        RX_PIPE_CAP,
+        bytes_per_sec,
+        t_fill_us,
+        yield_us
+    );
+
+    // Never choose zero.
+    Duration::from_micros(yield_us.max(1) as u64)
+}

semestralka_1/src/hw_uart_pc/usart1.rs

@@ -0,0 +1,12 @@
+// src/uart/usart1.rs
+use defmt::info;
+use embassy_time::Duration;
+
+use crate::hw_uart_pc::safety::preflight_and_suggest_yield_period;
+
+pub fn setup_and_spawn(baudrate: u32,) -> Duration {
+    let yield_period: Duration = preflight_and_suggest_yield_period(baudrate);
+    info!("HW USART1 safe");
+
+    yield_period
+}

semestralka_1/src/lib.rs

@@ -0,0 +1,5 @@
+#![no_std]
+
+pub mod software_uart;
+pub mod config;
+pub mod hw_uart_pc;

semestralka_1/src/software_uart/debug.rs

@@ -0,0 +1,43 @@
+// src/software_uart/debug.rs
+use defmt::info;
+
+pub fn dump_tim6_regs() {
+    use embassy_stm32::pac::timer::TimBasic;
+    let tim = unsafe { TimBasic::from_ptr(0x4000_1000usize as _) };
+    let sr = tim.sr().read();
+    let dier = tim.dier().read();
+    let cr1 = tim.cr1().read();
+    let arr = tim.arr().read().arr();
+    let psc = tim.psc().read();
+    info!(
+        "TIM6: CR1.CEN={} DIER.UDE={} SR.UIF={} PSC={} ARR={}",
+        cr1.cen(),
+        dier.ude(),
+        sr.uif(),
+        psc,
+        arr
+    );
+}
+
+pub fn dump_dma_ch0_regs() {
+    use embassy_stm32::pac::gpdma::Gpdma;
+    let dma = unsafe { Gpdma::from_ptr(0x4002_0000usize as _) };
+    let ch = dma.ch(0);
+    let cr = ch.cr().read();
+    let tr1 = ch.tr1().read();
+    let tr2 = ch.tr2().read();
+    let br1 = ch.br1().read();
+    info!(
+        "GPDMA1_CH0: EN={} PRIO={} SDW={} DDW={} SINC={} DINC={} REQSEL={} SWREQ={} DREQ={} BNDT={}",
+        cr.en(),
+        cr.prio(),
+        tr1.sdw(),
+        tr1.ddw(),
+        tr1.sinc(),
+        tr1.dinc(),
+        tr2.reqsel(),
+        tr2.swreq(),
+        tr2.dreq(),
+        br1.bndt()
+    );
+}

semestralka_1/src/software_uart/dma_timer.rs

@@ -0,0 +1,58 @@
+// src/dma_timer.rs
+
+use embassy_stm32::{
+    peripherals::{TIM6, TIM7},
+    rcc,
+    timer::low_level::Timer,
+    Peri,
+};
+use core::mem;
+use embassy_stm32::timer::BasicInstance;
+use embassy_stm32::pac::timer::vals::Urs;
+
+/// Initializes TIM6 to tick at `baud * oversample` frequency.
+/// Each TIM6 update event triggers one DMA beat.
+pub fn init_tim6_for_uart<'d>(tim6: Peri<'d, TIM6>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM6>();
+    let ll = Timer::new(tim6);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+/// Initializes TIM7 to tick at `baud * oversample` frequency.
+/// Each TIM7 update event triggers one DMA beat.
+pub fn init_tim7_for_uart<'d>(tim7: Peri<'d, TIM7>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM7>();
+    let ll = Timer::new(tim7);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+// Shared internal helper — identical CR1/ARR setup
+fn configure_basic_timer<T: BasicInstance>(ll: &Timer<'_, T>, baud: u32, oversample: u16) {
+    let f_timer = rcc::frequency::<T>().0;
+    let target = baud.saturating_mul(oversample.max(1) as u32).max(1);
+
+    // Compute ARR (prescaler = 0)
+    let mut arr = (f_timer / target).saturating_sub(1) as u16;
+    if arr == 0 { arr = 1; }
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_cen(false);
+        w.set_opm(false);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+
+    ll.regs_basic().psc().write_value(0u16);
+    ll.regs_basic().arr().write(|w| w.set_arr(arr));
+    ll.regs_basic().dier().modify(|w| w.set_ude(true));
+    ll.regs_basic().egr().write(|w| w.set_ug(true));
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_opm(false);
+        w.set_cen(true);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+}

semestralka_1/src/software_uart/gpio_dma_uart_rx.rs

@@ -0,0 +1,61 @@
+// src/software_uart/runtime.rs
+use embassy_executor::task;
+use embassy_stm32::{
+    dma::Request,
+    peripherals::GPDMA1_CH1,
+    Peri,
+};
+use crate::config::RX_PIN_BIT;
+use embassy_stm32::dma::{
+    ReadableRingBuffer,
+    TransferOptions,
+};
+use crate::config::{RX_OVERSAMPLE, UART_CFG};
+use crate::software_uart::decode_uart_samples;
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use embassy_futures::yield_now;
+use defmt::info;
+
+// datasheet tabulka 137
+pub const TIM7_UP_REQ: Request = 5;
+
+/// RX DMA task: reads GPIO samples paced by TIM7 and fills PIPE_RX
+#[task]
+pub async fn rx_dma_task(
+    ch: Peri<'static, GPDMA1_CH1>,
+    ring: &'static mut [u8],
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let gpioa_idr = embassy_stm32::pac::GPIOA.idr().as_ptr() as *mut u8;
+
+    let mut opts = TransferOptions::default();
+    opts.half_transfer_ir = true;
+    opts.complete_transfer_ir = true;
+
+    // SAFETY: ring is exclusive to this task
+    let mut rx = unsafe { ReadableRingBuffer::new(ch, TIM7_UP_REQ, gpioa_idr, ring, opts) };
+    rx.start();
+
+    let mut raw_chunk = [0u8; 256];
+    let mut levels = [0u8; 256];
+    loop {
+        info!("rx_dma_task waiting for DMA data...");
+        let _ = rx.read_exact(&mut raw_chunk).await;
+
+        for (i, b) in raw_chunk.iter().enumerate() {
+            levels[i] = ((*b >> RX_PIN_BIT) & 1) as u8;
+        }
+
+        let decoded = decode_uart_samples(&levels, RX_OVERSAMPLE, &UART_CFG);
+        if !decoded.is_empty() {
+            info!("SW RX raw samples (first 32): {:a}", &levels[..32]);
+            info!(
+                "SW RX decoded {} bytes: {:a}",
+                decoded.len(),
+                decoded.as_slice()
+            );
+        }
+        pipe_rx.write(&decoded).await;
+        yield_now().await;
+    }
+}

semestralka_1/src/software_uart/gpio_dma_uart_tx.rs

@@ -0,0 +1,84 @@
+// src/software_uart/gpio_dma_uart_tx.rs
+use embassy_executor::task;
+use embassy_stm32::{
+    dma::{Request, TransferOptions, WritableRingBuffer},
+    peripherals::GPDMA1_CH0,
+    Peri,
+};
+use embassy_futures::yield_now;
+use defmt::info;
+
+use embassy_sync::pipe::Pipe;
+use crate::config::{TX_PIN_BIT, UART_CFG};
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use crate::software_uart::uart_emulation::encode_uart_byte_cfg;
+
+pub const TIM6_UP_REQ: Request = 4;
+
+pub async fn encode_uart_frames<'a>(
+    pin_bit: u8,
+    bytes: &[u8],
+    out_buf: &'a mut [u32],
+) -> usize {
+    let mut offset = 0;
+    for &b in bytes {
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(pin_bit, b, &UART_CFG, &mut frame);
+
+        if offset + used <= out_buf.len() {
+            out_buf[offset..offset + used].copy_from_slice(&frame[..used]);
+            offset += used;
+        } else {
+            break;
+        }
+
+        // cooperative async yield
+        yield_now().await;
+    }
+    offset
+}
+
+/// TX DMA task: encodes UART frames and sends them via DMA at TIM6 rate
+#[task]
+pub async fn tx_dma_task(
+    ch: Peri<'static, GPDMA1_CH0>,
+    register: *mut u32, // Either odr or bsrr
+    tx_ring_mem: &'static mut [u32],
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut tx_opts = TransferOptions::default();
+    tx_opts.half_transfer_ir = true;
+    tx_opts.complete_transfer_ir = true;
+
+    // SAFETY: tx_ring is exclusive to this task
+    let mut tx_ring = unsafe {
+        WritableRingBuffer::new(
+            ch,
+            TIM6_UP_REQ,
+            register,
+            tx_ring_mem,
+            tx_opts,
+        )
+    };
+
+    tx_ring.start();
+    info!("TX DMA ring started");
+
+    let mut frame_buf = [0u32; 4096];
+    let mut rx_buf = [0u8; 256];
+
+    loop {
+        let n = pipe_rx.read(&mut rx_buf).await;
+        if n == 0 {
+            yield_now().await;
+            continue;
+        }
+
+        let used = encode_uart_frames(TX_PIN_BIT, &rx_buf[..n], &mut frame_buf).await;
+        if used > 0 {
+            let _ = tx_ring.write_exact(&frame_buf[..used]).await;
+        }
+        info!("tx_dma_task wrote {} words", used);
+        yield_now().await;
+    }
+}

semestralka_1/src/software_uart/mod.rs

@@ -0,0 +1,13 @@
+// src/software_uart/mod.rs
+
+pub mod gpio_dma_uart_tx;
+pub mod gpio_dma_uart_rx;
+pub mod dma_timer;
+pub mod uart_emulation;
+pub mod debug;
+
+pub use gpio_dma_uart_tx::*;
+pub use gpio_dma_uart_rx::*;
+pub use dma_timer::*;
+pub use uart_emulation::*;
+pub use debug::*;

semestralka_1/src/software_uart/uart_emulation.rs

@@ -0,0 +1,151 @@
+// src/software_uart/uart_emulation.rs
+use heapless::Vec;
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Parity {
+    None,
+    Even,
+    Odd,
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum StopBits {
+    One,
+    Two,
+}
+
+#[derive(Clone, Copy, Debug)]
+pub struct UartConfig {
+    pub data_bits: u8,
+    pub parity: Parity,
+    pub stop_bits: StopBits,
+}
+
+impl Default for UartConfig {
+    fn default() -> Self {
+        Self {
+            data_bits: 8,
+            parity: Parity::None,
+            stop_bits: StopBits::One,
+        }
+    }
+}
+
+/// Encodes one byte into a sequence of GPIO BSRR words
+pub fn encode_uart_byte_cfg(
+    pin_bit: u8,
+    data: u8,
+    cfg: &UartConfig,
+    out: &mut [u32; 12],
+) -> usize {
+    // GPIOx_BSRR register str. 636 kap. 13.4.7
+    let set_high = |bit: u8| -> u32 { 1u32 << bit };
+    // let set_low = |bit: u8| -> u32 { 0 }; // ODR
+    let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) }; // BSRR
+
+    let mut idx = 0usize;
+
+    // START bit (LOW)
+    out[idx] = set_low(pin_bit);
+    idx += 1;
+
+    // Data bits, LSB-first
+    let nbits = cfg.data_bits.clamp(5, 8);
+    for i in 0..nbits {
+        let one = ((data >> i) & 1) != 0;
+        out[idx] = if one { set_high(pin_bit) } else { set_low(pin_bit) };
+        idx += 1;
+    }
+
+    // Parity
+    match cfg.parity {
+        Parity::None => {}
+        Parity::Even | Parity::Odd => {
+            let mask: u8 = if nbits == 8 { 0xFF } else { (1u16 << nbits) as u8 - 1 };
+            let ones = (data & mask).count_ones() & 1;
+            let par_bit_is_one = match cfg.parity {
+                Parity::Even => ones == 1,
+                Parity::Odd => ones == 0,
+                _ => false,
+            };
+            out[idx] = if par_bit_is_one {
+                set_high(pin_bit)
+            } else {
+                set_low(pin_bit)
+            };
+            idx += 1;
+        }
+    }
+
+    // STOP bits (HIGH)
+    let stop_ticks = match cfg.stop_bits {
+        StopBits::One => 1usize,
+        StopBits::Two => 2usize,
+    };
+    for _ in 0..stop_ticks {
+        out[idx] = set_high(pin_bit);
+        idx += 1;
+    }
+
+    idx
+}
+
+/// Decode an oversampled stream of logic levels into UART bytes.
+pub fn decode_uart_samples(
+    samples: &[u8],
+    oversample: u16,
+    cfg: &UartConfig,
+) -> heapless::Vec<u8, 256> {
+
+    let mut out = Vec::<u8, 256>::new();
+    let mut idx = 0usize;
+    let nbits = cfg.data_bits as usize;
+
+    while idx + (oversample as usize * (nbits + 3)) < samples.len() {
+        // Wait for start bit (falling edge: high -> low)
+        if samples[idx] != 0 && samples[idx + 1] == 0 {
+            // Align to middle of start bit
+            idx += (oversample / 2) as usize;
+
+            // Sanity check start bit really low
+            if samples.get(idx).copied().unwrap_or(1) != 0 {
+                idx += 1;
+                continue;
+            }
+
+            // Sample data bits
+            let mut data: u8 = 0;
+            for bit in 0..nbits {
+                idx += oversample as usize;
+                let bit_val = samples
+                    .get(idx)
+                    .map(|&b| if b != 0 { 1u8 } else { 0u8 })
+                    .unwrap_or(1);
+                data |= bit_val << bit;
+            }
+
+            // Parity: skip / verify
+            match cfg.parity {
+                Parity::None => {}
+                Parity::Even | Parity::Odd => {
+                    idx += oversample as usize;
+                    // You can optionally add parity check here if needed
+                }
+            }
+
+            // Move past stop bits
+            let stop_skip = match cfg.stop_bits {
+                StopBits::One => oversample as usize,
+                StopBits::Two => (oversample * 2) as usize,
+            };
+            idx += stop_skip;
+
+            // Push decoded byte
+            let _ = out.push(data);
+        } else {
+            idx += 1;
+        }
+    }
+
+    out
+}

semestralka_1/tests/uart_emulation.rs

@@ -0,0 +1,41 @@
+#![no_std]
+#![no_main]
+
+use dma_gpio as _;
+use panic_probe as _;
+use defmt_rtt as _;
+
+#[defmt_test::tests]
+mod tests {
+    use defmt::assert_eq;
+    use dma_gpio::software_uart::uart_emulation::{
+        encode_uart_byte_cfg, UartConfig, Parity, StopBits
+    };
+
+    const TX_PIN_BIT: u8 = 2;
+
+    #[test]
+    fn test_encode_8n1() {
+        let cfg = UartConfig::default();
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(TX_PIN_BIT, 0x55, &cfg, &mut frame);
+        
+        assert_eq!(used, 10);
+        assert_eq!(frame[0], 1u32 << 18); // Start LOW
+        assert_eq!(frame[9], 1u32 << 2);  // Stop HIGH
+    }
+
+    #[test]
+    fn test_encode_parity() {
+        let cfg = UartConfig {
+            data_bits: 8,
+            parity: Parity::Even,
+            stop_bits: StopBits::One,
+        };
+        
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(TX_PIN_BIT, 0x00, &cfg, &mut frame);
+        
+        assert_eq!(used, 11);
+    }
+}

semestralka_1b/.cargo/config.toml

@@ -0,0 +1,15 @@
+[build]
+target = "thumbv8m.main-none-eabihf"
+
+[target.thumbv8m.main-none-eabihf]
+runner = "probe-rs run --chip STM32U575ZITxQ"
+
+rustflags = [
+  "-C", "linker=rust-lld",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "link-arg=-Tdefmt.x",
+  "-C", "link-arg=--nmagic",
+]
+
+[package.metadata.cargo-flash]
+chip = "STM32U575ZIT"

semestralka_1b/.gitignore

@@ -0,0 +1 @@
+/target

semestralka_1b/Cargo.toml

@@ -0,0 +1,46 @@
+[package]
+authors = ["Priec <filippriec@gmail.com>"]
+name = "dma_gpio"
+edition = "2024"
+version = "0.1.0"
+
+
+[dependencies]
+cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.5"
+panic-halt = "1.0.0"
+
+embassy-executor = { git = "https://github.com/embassy-rs/embassy.git", branch = "main", features = ["arch-cortex-m", "executor-thread"] }
+embassy-futures = { git = "https://github.com/embassy-rs/embassy.git", branch = "main" }
+embassy-sync    = { git = "https://github.com/embassy-rs/embassy.git", branch = "main" }
+embassy-time    = { git = "https://github.com/embassy-rs/embassy.git", branch = "main", features = ["tick-hz-32_768"] }
+embassy-hal-internal = { git = "https://github.com/embassy-rs/embassy.git", branch = "main" }
+embassy-usb = { git = "https://github.com/embassy-rs/embassy.git", branch = "main" }
+embassy-stm32 = { git = "https://github.com/embassy-rs/embassy.git", branch = "main", features = ["unstable-pac", "stm32u575zi", "time-driver-tim2", "memory-x", "defmt"] }
+
+embedded-hal = "1.0.0"
+embedded-graphics = "0.8.1"
+heapless = { version = "0.9.1", default-features = false }
+micromath = "2.1.0"
+tinybmp = "0.6.0"
+panic-probe = { version = "1.0.0", features = ["defmt"] }
+defmt-rtt = "1.1.0"
+defmt = "1.0.1"
+static_cell = "2.1.1"
+embedded-io = "0.6.1"
+embedded-io-async = "0.6.1"
+
+[dev-dependencies]
+defmt-test = "0.4.0"
+
+[[test]]
+name = "uart_emulation"
+harness = false
+
+[lib]
+test = false
+
+[[bin]]
+name = "main"
+path = "src/bin/main.rs"
+test = false

semestralka_1b/LICENSE-APACHE

@@ -0,0 +1,201 @@
+                              Apache License
+                        Version 2.0, January 2004
+                     http://www.apache.org/licenses/
+
+TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
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+
+   "You" (or "Your") shall mean an individual or Legal Entity
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+See the License for the specific language governing permissions and
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semestralka_1b/LICENSE-MIT

@@ -0,0 +1,23 @@
+Permission is hereby granted, free of charge, to any
+person obtaining a copy of this software and associated
+documentation files (the "Software"), to deal in the
+Software without restriction, including without
+limitation the rights to use, copy, modify, merge,
+publish, distribute, sublicense, and/or sell copies of
+the Software, and to permit persons to whom the Software
+is furnished to do so, subject to the following
+conditions:
+
+The above copyright notice and this permission notice
+shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
+ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
+IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.

semestralka_1b/Makefile

@@ -0,0 +1,23 @@
+TARGET = thumbv8m.main-none-eabihf
+CHIP = STM32U575ZI
+BIN = stm32u5-blinky
+MODE ?= release
+TARGET_DIR = target/$(TARGET)/$(MODE)
+ELF = $(TARGET_DIR)/$(BIN)
+PROBE = probe-rs
+
+.PHONY: all build flash clean empty
+
+all: build
+
+build:
+	cargo build --$(MODE)
+
+flash: build
+	$(PROBE) run --chip $(CHIP) $(ELF)
+
+empty:
+	$(PROBE) erase --chip $(CHIP)
+
+clean:
+	cargo clean

semestralka_1b/README.md

@@ -0,0 +1,232 @@
+# `app-template`
+
+> Quickly set up a [`probe-rs`] + [`defmt`] + [`flip-link`] embedded project
+
+[`probe-rs`]: https://crates.io/crates/probe-rs
+[`defmt`]: https://github.com/knurling-rs/defmt
+[`flip-link`]: https://github.com/knurling-rs/flip-link
+
+## Dependencies
+
+### 1. `flip-link`:
+
+```bash
+cargo install flip-link
+```
+
+### 2. `probe-rs`:
+
+Install probe-rs by following the instructions at <https://probe.rs/docs/getting-started/installation/>.
+
+### 3. [`cargo-generate`]:
+
+```bash
+cargo install cargo-generate
+```
+
+[`cargo-generate`]: https://crates.io/crates/cargo-generate
+
+> *Note:* You can also just clone this repository instead of using `cargo-generate`, but this involves additional manual adjustments.
+
+## Setup
+
+### 1. Initialize the project template
+
+```bash
+cargo generate \
+    --git https://github.com/knurling-rs/app-template \
+    --branch main \
+    --name my-app
+```
+
+If you look into your new `my-app` folder, you'll find that there are a few `TODO`s in the files marking the properties you need to set.
+
+Let's walk through them together now.
+
+### 2. Set `probe-rs` chip
+
+Pick a chip from ` probe-rs chip list` and enter it into `.cargo/config.toml`.
+
+If, for example, you have a nRF52840 Development Kit as used in one of [our exercises], replace `{{chip}}` with `nRF52840_xxAA`.
+
+[our workshops]: https://rust-exercises.ferrous-systems.com
+
+```diff
+ # .cargo/config.toml
+-runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format=oneline"]
++runner = ["probe-rs", "run", "--chip", "nRF52840_xxAA", "--log-format=oneline"]
+```
+
+### 3. Adjust the compilation target
+
+In `.cargo/config.toml`, pick the right compilation target for your board.
+
+```diff
+ # .cargo/config.toml
+ [build]
+-target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
+-# target = "thumbv7m-none-eabi"    # Cortex-M3
+-# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
+-# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
++target = "thumbv7em-none-eabihf" # Cortex-M4F (with FPU)
+```
+
+Add the target with `rustup`.
+
+```bash
+rustup target add thumbv7em-none-eabihf
+```
+
+### 4. Add a HAL as a dependency
+
+In `Cargo.toml`, list the Hardware Abstraction Layer (HAL) for your board as a dependency.
+
+For the nRF52840 you'll want to use the [`nrf52840-hal`].
+
+[`nrf52840-hal`]: https://crates.io/crates/nrf52840-hal
+
+```diff
+ # Cargo.toml
+ [dependencies]
+-# some-hal = "1.2.3"
++nrf52840-hal = "0.14.0"
+```
+
+⚠️ Note for RP2040 users ⚠️
+
+You will need to not just specify the `rp-hal` HAL, but a BSP (board support crate) which includes a second stage bootloader. Please find a list of available BSPs [here](https://github.com/rp-rs/rp-hal-boards#packages).
+
+### 5. Import your HAL
+
+Now that you have selected a HAL, fix the HAL import in `src/lib.rs`
+
+```diff
+ // my-app/src/lib.rs
+-// use some_hal as _; // memory layout
++use nrf52840_hal as _; // memory layout
+```
+
+### (6. Get a linker script)
+
+Some HAL crates require that you manually copy over a file called `memory.x` from the HAL to the root of your project. For nrf52840-hal, this is done automatically so no action is needed. For other HAL crates, see their documentation on where to find an example file.
+
+The `memory.x` file should look something like:
+
+```text
+MEMORY
+{
+  FLASH : ORIGIN = 0x00000000, LENGTH = 1024K
+  RAM   : ORIGIN = 0x20000000, LENGTH = 256K
+}
+```
+
+The `memory.x` file is included in the `cortex-m-rt` linker script `link.x`, and so `link.x` is the one you should tell `rustc` to use (see the `.cargo/config.toml` file where we do that).
+
+### 7. Run!
+
+You are now all set to `cargo-run` your first `defmt`-powered application!
+There are some examples in the `src/bin` directory.
+
+Start by `cargo run`-ning `my-app/src/bin/hello.rs`:
+
+```console
+$ # `rb` is an alias for `run --bin`
+$ cargo rb hello
+    Finished `dev` profile [optimized + debuginfo] target(s) in 0.01s
+     Running `probe-rs run --chip nrf52840_xxaa --log-format=oneline target/thumbv6m-none-eabi/debug/hello`
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.79 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+Hello, world!
+
+$ echo $?
+0
+```
+
+If you're running out of memory (`flip-link` bails with an overflow error), you can decrease the size of the device memory buffer by setting the `DEFMT_RTT_BUFFER_SIZE` environment variable. The default value is 1024 bytes, and powers of two should be used for optimal performance:
+
+```console
+$ DEFMT_RTT_BUFFER_SIZE=64 cargo rb hello
+```
+
+### (8. Set `rust-analyzer.linkedProjects`)
+
+If you are using [rust-analyzer] with VS Code for IDE-like features you can add following configuration to your `.vscode/settings.json` to make it work transparently across workspaces. Find the details of this option in the [RA docs].
+
+```json
+{
+    "rust-analyzer.linkedProjects": [
+        "Cargo.toml",
+        "firmware/Cargo.toml",
+    ]
+}
+```
+
+[RA docs]: https://rust-analyzer.github.io/manual.html#configuration
+[rust-analyzer]: https://rust-analyzer.github.io/
+
+## Running tests
+
+The template comes configured for running unit tests and integration tests on the target.
+
+Unit tests reside in the library crate and can test private API; the initial set of unit tests are in `src/lib.rs`.
+`cargo test --lib` will run those unit tests.
+
+```console
+$ cargo test --lib
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.15s
+     Running unittests src/lib.rs (target/thumbv6m-none-eabi/debug/deps/example-2b0d0e25d141bf57)
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.99 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.33 KiB/s (took 1s)                                                                                                                        Finished in 1.10s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Integration tests reside in the `tests` directory; the initial set of integration tests are in `tests/integration.rs`.
+`cargo test --test integration` will run those integration tests.
+Note that the argument of the `--test` flag must match the name of the test file in the `tests` directory.
+
+```console
+$ cargo test --test integration
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.10s
+     Running tests/integration.rs (target/thumbv6m-none-eabi/debug/deps/integration-aaaff41151f6a722)
+      Erasing ✔ 100% [####################]   8.00 KiB @  16.03 KiB/s (took 0s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Note that to add a new test file to the `tests` directory you also need to add a new `[[test]]` section to `Cargo.toml`.
+
+To run all the tests via `cargo test` the tests need to be explicitly disabled for all the existing binary targets.
+See `Cargo.toml` for details on how to do this.
+
+## Support
+
+`app-template` is part of the [Knurling] project, [Ferrous Systems]' effort at
+improving tooling used to develop for embedded systems.
+
+If you think that our work is useful, consider sponsoring it via [GitHub
+Sponsors].
+
+## License
+
+Licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+  http://www.apache.org/licenses/LICENSE-2.0)
+
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+### Contribution
+
+Unless you explicitly state otherwise, any contribution intentionally submitted
+for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
+licensed as above, without any additional terms or conditions.
+
+[Knurling]: https://knurling.ferrous-systems.com
+[Ferrous Systems]: https://ferrous-systems.com/
+[GitHub Sponsors]: https://github.com/sponsors/knurling-rs

semestralka_1b/src/bin/main.rs

@@ -0,0 +1,174 @@
+// src/bin/main.rs
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_time::Instant;
+use embassy_executor::task;
+use embassy_stm32::dma::Request;
+use embassy_stm32::gpio::{Input, Output, Level, Pull, Speed};
+use dma_gpio::software_uart::{
+    dma_timer::{init_tim6_for_uart, init_tim7_for_uart},
+    gpio_dma_uart_rx::rx_dma_task,
+    debug::dump_tim6_regs,
+};
+use dma_gpio::config::{BAUD, RX_OVERSAMPLE, TX_OVERSAMPLE};
+use dma_gpio::config::{TX_RING_BYTES, RX_RING_BYTES};
+use dma_gpio::software_uart::gpio_dma_uart_tx::tx_dma_task;
+use static_cell::StaticCell;
+use embassy_futures::yield_now;
+use dma_gpio::hw_uart_pc::usart1;
+use dma_gpio::hw_uart_pc::driver::uart_task;
+use embassy_stm32::usart::{BufferedUart, Config, BufferedInterruptHandler};
+use embassy_stm32::peripherals;
+use embassy_stm32::bind_interrupts;
+use dma_gpio::config::{PIPE_HW_TX, PIPE_HW_RX, PIPE_SW_TX, PIPE_SW_RX};
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use dma_gpio::hw_uart_internal::usart2;
+use dma_gpio::hw_uart_internal::driver::uart_task as uart_task_internal;
+use dma_gpio::config::{PIPE_INT_TX, PIPE_INT_RX};
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    USART1 => BufferedInterruptHandler<peripherals::USART1>;
+});
+bind_interrupts!(struct Irqs2 {
+    USART2 => BufferedInterruptHandler<peripherals::USART2>;
+});
+
+// Software uart
+pub const TIM6_UP_REQ: Request = 4;
+static SW_TX_RING: StaticCell<[u32; TX_RING_BYTES]> = StaticCell::new();
+static SW_RX_RING: StaticCell<[u8; RX_RING_BYTES]> = StaticCell::new();
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    info!("boot");
+    let p = embassy_stm32::init(Default::default());
+    info!("init m8");
+
+    // HARDWARE UART to the PC
+    let mut cfg = Config::default();
+    cfg.baudrate = BAUD;
+    static TX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
+    static RX_BUF: StaticCell<[u8; 256]> = StaticCell::new();
+    let uart = BufferedUart::new(
+        p.USART1,
+        p.PA10, // RX pin
+        p.PA9,  // TX pin
+        TX_BUF.init([0; 256]),
+        RX_BUF.init([0; 256]),
+        Irqs,
+        cfg,
+    ).unwrap();
+    let yield_period = usart1::setup_and_spawn(BAUD);
+    spawner.spawn(uart_task(uart, &PIPE_HW_TX, &PIPE_HW_RX).unwrap());
+    // END OF HARDWARE UART to the PC
+
+    // INTERNAL HARDWARE UART (USART2)
+    let mut cfg2 = Config::default();
+    cfg2.baudrate = BAUD;
+    static TX_BUF2: StaticCell<[u8; 256]> = StaticCell::new();
+    static RX_BUF2: StaticCell<[u8; 256]> = StaticCell::new();
+
+    let uart2 = BufferedUart::new(
+        p.USART2,
+        p.PA3, // RX
+        p.PA2, // TX
+        TX_BUF2.init([0; 256]),
+        RX_BUF2.init([0; 256]),
+        Irqs2,
+        cfg2,
+    )
+        .unwrap();
+
+    let _ = usart2::setup_and_spawn(BAUD);
+    spawner
+        .spawn(uart_task_internal(uart2, &PIPE_INT_TX, &PIPE_INT_RX).unwrap());
+    info!("USART2 ready");
+    // END OF INTERNAL HARDWARE UART (USART2)
+    
+    // USART1 <-> USART2 bridge
+    spawner.spawn(bridge_usart1_rx_to_usart2_tx(&PIPE_HW_RX, &PIPE_INT_TX).unwrap());
+    spawner.spawn(bridge_usart2_rx_to_usart1_tx(&PIPE_INT_RX, &PIPE_HW_TX).unwrap());
+    info!("USART1 <-> USART2 bridge active");
+    // END OF USART1 <-> USART2 bridge 
+
+    // SOFTWARE UART 
+    let _rx = Input::new(p.PC3, Pull::Up);
+    let _tx = Output::new(p.PB0, Level::High, Speed::VeryHigh);
+    init_tim6_for_uart(p.TIM6, BAUD, TX_OVERSAMPLE);
+    init_tim7_for_uart(p.TIM7, BAUD, RX_OVERSAMPLE);
+    dump_tim6_regs();
+
+    // Safe one-time init from StaticCell
+    let sw_rx_ring: &mut [u8; RX_RING_BYTES] = SW_RX_RING.init([0; RX_RING_BYTES]);
+    let sw_tx_ring: &mut [u32; TX_RING_BYTES] = SW_TX_RING.init([0; TX_RING_BYTES]);
+    spawner.spawn(rx_dma_task(p.GPDMA1_CH1, sw_rx_ring, &PIPE_SW_RX).unwrap());
+
+    // Create and start the TX DMA ring in main.
+    let bsrr_ptr = embassy_stm32::pac::GPIOA.bsrr().as_ptr() as *mut u32;
+    // let odr_ptr = embassy_stm32::pac::GPIOA.odr().as_ptr() as *mut u32; // NEEDS DECODE CHANGE
+    spawner.spawn(tx_dma_task(p.GPDMA1_CH0, bsrr_ptr, sw_tx_ring, &PIPE_SW_TX).unwrap());
+    // EDN OF SOFTWARE UART 
+
+
+    let mut last_yield = Instant::now();
+    let mut buf = [0u8; 32];
+
+    loop {
+        info!("tick start");
+        // Timer::after(Duration::from_millis(100)).await;
+        // info!("tick end");
+
+        let n1 = PIPE_HW_RX.read(&mut buf).await;
+        if n1 > 0 {
+            info!("PC received: {:a}", &buf[..n1]);
+            let _ = PIPE_SW_TX.write(&buf[..n1]).await;
+            info!("SW UART TX sent echo: {:a}", &buf[..n1]);
+        }
+        yield_now().await;
+
+        let n2 = PIPE_SW_RX.read(&mut buf).await;
+        if n2 > 0 {
+            info!("SW UART RX received: {:a}", &buf[..n2]);
+        }
+
+        if Instant::now().duration_since(last_yield) >= yield_period {
+            yield_now().await;
+            last_yield = Instant::now();
+        }
+
+    }
+}
+
+#[embassy_executor::task]
+pub async fn bridge_usart1_rx_to_usart2_tx(
+    usart1_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+    usart2_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut buf = [0u8; 64];
+    loop {
+        let n = usart1_rx.read(&mut buf).await;
+        if n > 0 {
+            let _ = usart2_tx.write(&buf[..n]).await;
+            info!("bridge: USART1 -> USART2 sent {} bytes", n);
+        }
+    }
+}
+
+#[embassy_executor::task]
+pub async fn bridge_usart2_rx_to_usart1_tx(
+    usart2_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+    usart1_tx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut buf = [0u8; 64];
+    loop {
+        let n = usart2_rx.read(&mut buf).await;
+        if n > 0 {
+            let _ = usart1_tx.write(&buf[..n]).await;
+            info!("bridge: USART2 -> USART1 sent {} bytes", n);
+        }
+    }
+}

semestralka_1b/src/config.rs

@@ -0,0 +1,33 @@
+// src/config.rs
+use crate::software_uart::uart_emulation::{Parity, StopBits, UartConfig};
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+
+pub const BAUD: u32 = 9_600;
+pub const TX_PIN_BIT: u8 = 2; // PA2
+pub const RX_PIN_BIT: u8 = 3; // PA3
+pub const TX_OVERSAMPLE: u16 = 1;
+pub const RX_OVERSAMPLE: u16 = 16;
+
+pub const RX_RING_BYTES: usize = 4096;
+pub const TX_RING_BYTES: usize = 4096;
+
+pub const PIPE_HW_TX_SIZE: usize = 1024;
+pub const PIPE_HW_RX_SIZE: usize = 1024;
+pub const PIPE_SW_TX_SIZE: usize = 1024;
+pub const PIPE_SW_RX_SIZE: usize = 1024;
+pub const PIPE_INT_TX_SIZE: usize = 1024;
+pub const PIPE_INT_RX_SIZE: usize = 1024;
+
+pub static PIPE_HW_TX: Pipe<CriticalSectionRawMutex, PIPE_HW_TX_SIZE> = Pipe::new();
+pub static PIPE_HW_RX: Pipe<CriticalSectionRawMutex, PIPE_HW_RX_SIZE> = Pipe::new();
+pub static PIPE_SW_TX: Pipe<CriticalSectionRawMutex, PIPE_SW_TX_SIZE> = Pipe::new();
+pub static PIPE_SW_RX: Pipe<CriticalSectionRawMutex, PIPE_SW_RX_SIZE> = Pipe::new();
+pub static PIPE_INT_TX: Pipe<CriticalSectionRawMutex, PIPE_INT_TX_SIZE> = Pipe::new();
+pub static PIPE_INT_RX: Pipe<CriticalSectionRawMutex, PIPE_INT_RX_SIZE> = Pipe::new();
+
+pub const UART_CFG: UartConfig = UartConfig {
+    data_bits: 8,
+    parity: Parity::None,
+    stop_bits: StopBits::One,
+};

semestralka_1b/src/hw_uart_internal/driver.rs

@@ -0,0 +1,39 @@
+// src/hw_uart_internal/driver.rs
+use defmt::unwrap;
+use embassy_futures::select::{select, Either};
+use embassy_stm32::usart::BufferedUart;
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+use embedded_io_async::{Read, Write};
+use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
+
+#[embassy_executor::task]
+pub async fn uart_task(
+    mut uart: BufferedUart<'static>,
+    tx_pipe: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
+    rx_pipe: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
+) {
+    let mut rx_byte = [0u8; 1];
+    let mut tx_buf = [0u8; 64];
+
+    loop {
+        let rx_fut = uart.read(&mut rx_byte);
+        let tx_fut = async {
+            let n = tx_pipe.read(&mut tx_buf).await;
+            n
+        };
+
+        match select(rx_fut, tx_fut).await {
+            // Incoming data from UART hardware
+            Either::First(res) => {
+                if let Ok(_) = res {
+                    let _ = rx_pipe.write(&rx_byte).await;
+                }
+            }
+            // Outgoing data waiting in TX pipe
+            Either::Second(n) => {
+                unwrap!(uart.write(&tx_buf[..n]).await);
+            }
+        }
+    }
+}

semestralka_1b/src/hw_uart_internal/mod.rs

@@ -0,0 +1,4 @@
+// src/hw_uart_internal/mod.rs
+
+pub mod driver;
+pub mod usart2;

semestralka_1b/src/hw_uart_internal/usart2.rs

@@ -0,0 +1,11 @@
+// src/hw_uart_internal/usart2.rs
+use defmt::info;
+use embassy_time::Duration;
+
+use crate::hw_uart_pc::safety::preflight_and_suggest_yield_period;
+
+pub fn setup_and_spawn(baudrate: u32) -> Duration {
+    let yield_period = preflight_and_suggest_yield_period(baudrate);
+    info!("HW USART2 safe");
+    yield_period
+}

semestralka_1b/src/hw_uart_pc/driver.rs

@@ -0,0 +1,39 @@
+// src/hw_uart_pc/driver.rs
+use defmt::unwrap;
+use embassy_futures::select::{select, Either};
+use embassy_stm32::usart::BufferedUart;
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::pipe::Pipe;
+use embedded_io_async::{Read, Write};
+use crate::hw_uart_pc::safety::{RX_PIPE_CAP, TX_PIPE_CAP};
+
+#[embassy_executor::task]
+pub async fn uart_task(
+    mut uart: BufferedUart<'static>,
+    tx_pipe: &'static Pipe<CriticalSectionRawMutex, TX_PIPE_CAP>,
+    rx_pipe: &'static Pipe<CriticalSectionRawMutex, RX_PIPE_CAP>,
+) {
+    let mut rx_byte = [0u8; 1];
+    let mut tx_buf = [0u8; 64];
+
+    loop {
+        let rx_fut = uart.read(&mut rx_byte);
+        let tx_fut = async {
+            let n = tx_pipe.read(&mut tx_buf).await;
+            n
+        };
+
+        match select(rx_fut, tx_fut).await {
+            // Incoming data from UART hardware
+            Either::First(res) => {
+                if let Ok(_) = res {
+                    let _ = rx_pipe.write(&rx_byte).await;
+                }
+            }
+            // Outgoing data waiting in TX pipe
+            Either::Second(n) => {
+                unwrap!(uart.write(&tx_buf[..n]).await);
+            }
+        }
+    }
+}

semestralka_1b/src/hw_uart_pc/mod.rs

@@ -0,0 +1,4 @@
+// src/hw_uart_pc/mod.rs
+pub mod driver;
+pub mod usart1;
+pub mod safety;

semestralka_1b/src/hw_uart_pc/safety.rs

@@ -0,0 +1,57 @@
+// src/safety.rs
+use defmt::info;
+use embassy_time::Duration;
+
+// ISR RX ring capacity = RX_BUF len
+const ISR_RX_BUF_CAP: usize = 256;
+// Yield 1/2 the time it takes to fill ISR RX ring.
+const YIELD_MARGIN_NUM: u32 = 1;
+const YIELD_MARGIN_DEN: u32 = 2;
+// Ensure RX_PIPE_CAP can hold this.
+const WORST_MAIN_LATENCY_MS: u32 = 20;
+
+pub const TX_PIPE_CAP: usize = 1024;
+pub const RX_PIPE_CAP: usize = 1024;
+
+
+
+/// Perform safety checks and compute yield timing to avoid buffer overflow.
+///
+/// # Panics
+/// Panics if pipe capacities are too small for the configured baud.
+pub fn preflight_and_suggest_yield_period(baud: u32) -> Duration {
+    // Approx bytes per second for 8N1 (10 bits per byte on the wire)
+    let bytes_per_sec = (baud / 10).max(1);
+
+    // Time until ISR RX ring fills, in microseconds.
+    let t_fill_us = (ISR_RX_BUF_CAP as u64) * 1_000_000u64 / (bytes_per_sec as u64);
+
+    // Choose a yield period as a fraction of t_fill.
+    let yield_us = (t_fill_us as u64)
+        .saturating_mul(YIELD_MARGIN_NUM as u64)
+        / (YIELD_MARGIN_DEN as u64);
+
+    // Verify RX pipe can absorb a worst-case app latency so uart_task
+    // can always forward without dropping when it runs.
+    let required_rx_pipe = (bytes_per_sec as u64) * (WORST_MAIN_LATENCY_MS as u64) / 1000;
+
+    if (RX_PIPE_CAP as u64) < required_rx_pipe {
+        core::panic!(
+            "RX pipe too small: have {}B, need >= {}B for {}ms at {} bps",
+            RX_PIPE_CAP, required_rx_pipe, WORST_MAIN_LATENCY_MS, baud
+        );
+    }
+
+    info!(
+        "Preflight: baud={}, rx_isr={}B, rx_pipe={}B, bytes/s={}, t_fill_us={}, yield_us={}",
+        baud,
+        ISR_RX_BUF_CAP,
+        RX_PIPE_CAP,
+        bytes_per_sec,
+        t_fill_us,
+        yield_us
+    );
+
+    // Never choose zero.
+    Duration::from_micros(yield_us.max(1) as u64)
+}

semestralka_1b/src/hw_uart_pc/usart1.rs

@@ -0,0 +1,12 @@
+// src/uart/usart1.rs
+use defmt::info;
+use embassy_time::Duration;
+
+use crate::hw_uart_pc::safety::preflight_and_suggest_yield_period;
+
+pub fn setup_and_spawn(baudrate: u32,) -> Duration {
+    let yield_period: Duration = preflight_and_suggest_yield_period(baudrate);
+    info!("HW USART1 safe");
+
+    yield_period
+}

semestralka_1b/src/lib.rs

@@ -0,0 +1,6 @@
+#![no_std]
+
+pub mod software_uart;
+pub mod config;
+pub mod hw_uart_pc;
+pub mod hw_uart_internal;

semestralka_1b/src/software_uart/debug.rs

@@ -0,0 +1,43 @@
+// src/software_uart/debug.rs
+use defmt::info;
+
+pub fn dump_tim6_regs() {
+    use embassy_stm32::pac::timer::TimBasic;
+    let tim = unsafe { TimBasic::from_ptr(0x4000_1000usize as _) };
+    let sr = tim.sr().read();
+    let dier = tim.dier().read();
+    let cr1 = tim.cr1().read();
+    let arr = tim.arr().read().arr();
+    let psc = tim.psc().read();
+    info!(
+        "TIM6: CR1.CEN={} DIER.UDE={} SR.UIF={} PSC={} ARR={}",
+        cr1.cen(),
+        dier.ude(),
+        sr.uif(),
+        psc,
+        arr
+    );
+}
+
+pub fn dump_dma_ch0_regs() {
+    use embassy_stm32::pac::gpdma::Gpdma;
+    let dma = unsafe { Gpdma::from_ptr(0x4002_0000usize as _) };
+    let ch = dma.ch(0);
+    let cr = ch.cr().read();
+    let tr1 = ch.tr1().read();
+    let tr2 = ch.tr2().read();
+    let br1 = ch.br1().read();
+    info!(
+        "GPDMA1_CH0: EN={} PRIO={} SDW={} DDW={} SINC={} DINC={} REQSEL={} SWREQ={} DREQ={} BNDT={}",
+        cr.en(),
+        cr.prio(),
+        tr1.sdw(),
+        tr1.ddw(),
+        tr1.sinc(),
+        tr1.dinc(),
+        tr2.reqsel(),
+        tr2.swreq(),
+        tr2.dreq(),
+        br1.bndt()
+    );
+}

semestralka_1b/src/software_uart/dma_timer.rs

@@ -0,0 +1,58 @@
+// src/dma_timer.rs
+
+use embassy_stm32::{
+    peripherals::{TIM6, TIM7},
+    rcc,
+    timer::low_level::Timer,
+    Peri,
+};
+use core::mem;
+use embassy_stm32::timer::BasicInstance;
+use embassy_stm32::pac::timer::vals::Urs;
+
+/// Initializes TIM6 to tick at `baud * oversample` frequency.
+/// Each TIM6 update event triggers one DMA beat.
+pub fn init_tim6_for_uart<'d>(tim6: Peri<'d, TIM6>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM6>();
+    let ll = Timer::new(tim6);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+/// Initializes TIM7 to tick at `baud * oversample` frequency.
+/// Each TIM7 update event triggers one DMA beat.
+pub fn init_tim7_for_uart<'d>(tim7: Peri<'d, TIM7>, baud: u32, oversample: u16) {
+    rcc::enable_and_reset::<TIM7>();
+    let ll = Timer::new(tim7);
+    configure_basic_timer(&ll, baud, oversample);
+    mem::forget(ll);
+}
+
+// Shared internal helper — identical CR1/ARR setup
+fn configure_basic_timer<T: BasicInstance>(ll: &Timer<'_, T>, baud: u32, oversample: u16) {
+    let f_timer = rcc::frequency::<T>().0;
+    let target = baud.saturating_mul(oversample.max(1) as u32).max(1);
+
+    // Compute ARR (prescaler = 0)
+    let mut arr = (f_timer / target).saturating_sub(1) as u16;
+    if arr == 0 { arr = 1; }
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_cen(false);
+        w.set_opm(false);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+
+    ll.regs_basic().psc().write_value(0u16);
+    ll.regs_basic().arr().write(|w| w.set_arr(arr));
+    ll.regs_basic().dier().modify(|w| w.set_ude(true));
+    ll.regs_basic().egr().write(|w| w.set_ug(true));
+
+    ll.regs_basic().cr1().write(|w| {
+        w.set_opm(false);
+        w.set_cen(true);
+        w.set_udis(false);
+        w.set_urs(Urs::ANY_EVENT);
+    });
+}

semestralka_1b/src/software_uart/gpio_dma_uart_rx.rs

@@ -0,0 +1,61 @@
+// src/software_uart/runtime.rs
+use embassy_executor::task;
+use embassy_stm32::{
+    dma::Request,
+    peripherals::GPDMA1_CH1,
+    Peri,
+};
+use crate::config::RX_PIN_BIT;
+use embassy_stm32::dma::{
+    ReadableRingBuffer,
+    TransferOptions,
+};
+use crate::config::{RX_OVERSAMPLE, UART_CFG};
+use crate::software_uart::decode_uart_samples;
+use embassy_sync::{blocking_mutex::raw::CriticalSectionRawMutex, pipe::Pipe};
+use embassy_futures::yield_now;
+use defmt::info;
+
+// datasheet tabulka 137
+pub const TIM7_UP_REQ: Request = 5;
+
+/// RX DMA task: reads GPIO samples paced by TIM7 and fills PIPE_RX
+#[task]
+pub async fn rx_dma_task(
+    ch: Peri<'static, GPDMA1_CH1>,
+    ring: &'static mut [u8],
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let gpioa_idr = embassy_stm32::pac::GPIOA.idr().as_ptr() as *mut u8;
+
+    let mut opts = TransferOptions::default();
+    opts.half_transfer_ir = true;
+    opts.complete_transfer_ir = true;
+
+    // SAFETY: ring is exclusive to this task
+    let mut rx = unsafe { ReadableRingBuffer::new(ch, TIM7_UP_REQ, gpioa_idr, ring, opts) };
+    rx.start();
+
+    let mut raw_chunk = [0u8; 256];
+    let mut levels = [0u8; 256];
+    loop {
+        info!("rx_dma_task waiting for DMA data...");
+        let _ = rx.read_exact(&mut raw_chunk).await;
+
+        for (i, b) in raw_chunk.iter().enumerate() {
+            levels[i] = ((*b >> RX_PIN_BIT) & 1) as u8;
+        }
+
+        let decoded = decode_uart_samples(&levels, RX_OVERSAMPLE, &UART_CFG);
+        if !decoded.is_empty() {
+            info!("SW RX raw samples (first 32): {:a}", &levels[..32]);
+            info!(
+                "SW RX decoded {} bytes: {:a}",
+                decoded.len(),
+                decoded.as_slice()
+            );
+        }
+        pipe_rx.write(&decoded).await;
+        yield_now().await;
+    }
+}

semestralka_1b/src/software_uart/gpio_dma_uart_tx.rs

@@ -0,0 +1,84 @@
+// src/software_uart/gpio_dma_uart_tx.rs
+use embassy_executor::task;
+use embassy_stm32::{
+    dma::{Request, TransferOptions, WritableRingBuffer},
+    peripherals::GPDMA1_CH0,
+    Peri,
+};
+use embassy_futures::yield_now;
+use defmt::info;
+
+use embassy_sync::pipe::Pipe;
+use crate::config::{TX_PIN_BIT, UART_CFG};
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use crate::software_uart::uart_emulation::encode_uart_byte_cfg;
+
+pub const TIM6_UP_REQ: Request = 4;
+
+pub async fn encode_uart_frames<'a>(
+    pin_bit: u8,
+    bytes: &[u8],
+    out_buf: &'a mut [u32],
+) -> usize {
+    let mut offset = 0;
+    for &b in bytes {
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(pin_bit, b, &UART_CFG, &mut frame);
+
+        if offset + used <= out_buf.len() {
+            out_buf[offset..offset + used].copy_from_slice(&frame[..used]);
+            offset += used;
+        } else {
+            break;
+        }
+
+        // cooperative async yield
+        yield_now().await;
+    }
+    offset
+}
+
+/// TX DMA task: encodes UART frames and sends them via DMA at TIM6 rate
+#[task]
+pub async fn tx_dma_task(
+    ch: Peri<'static, GPDMA1_CH0>,
+    register: *mut u32, // Either odr or bsrr
+    tx_ring_mem: &'static mut [u32],
+    pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>,
+) {
+    let mut tx_opts = TransferOptions::default();
+    tx_opts.half_transfer_ir = true;
+    tx_opts.complete_transfer_ir = true;
+
+    // SAFETY: tx_ring is exclusive to this task
+    let mut tx_ring = unsafe {
+        WritableRingBuffer::new(
+            ch,
+            TIM6_UP_REQ,
+            register,
+            tx_ring_mem,
+            tx_opts,
+        )
+    };
+
+    tx_ring.start();
+    info!("TX DMA ring started");
+
+    let mut frame_buf = [0u32; 4096];
+    let mut rx_buf = [0u8; 256];
+
+    loop {
+        let n = pipe_rx.read(&mut rx_buf).await;
+        if n == 0 {
+            yield_now().await;
+            continue;
+        }
+
+        let used = encode_uart_frames(TX_PIN_BIT, &rx_buf[..n], &mut frame_buf).await;
+        if used > 0 {
+            let _ = tx_ring.write_exact(&frame_buf[..used]).await;
+        }
+        info!("tx_dma_task wrote {} words", used);
+        yield_now().await;
+    }
+}

semestralka_1b/src/software_uart/mod.rs

@@ -0,0 +1,13 @@
+// src/software_uart/mod.rs
+
+pub mod gpio_dma_uart_tx;
+pub mod gpio_dma_uart_rx;
+pub mod dma_timer;
+pub mod uart_emulation;
+pub mod debug;
+
+pub use gpio_dma_uart_tx::*;
+pub use gpio_dma_uart_rx::*;
+pub use dma_timer::*;
+pub use uart_emulation::*;
+pub use debug::*;

semestralka_1b/src/software_uart/uart_emulation.rs

@@ -0,0 +1,151 @@
+// src/software_uart/uart_emulation.rs
+use heapless::Vec;
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Parity {
+    None,
+    Even,
+    Odd,
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum StopBits {
+    One,
+    Two,
+}
+
+#[derive(Clone, Copy, Debug)]
+pub struct UartConfig {
+    pub data_bits: u8,
+    pub parity: Parity,
+    pub stop_bits: StopBits,
+}
+
+impl Default for UartConfig {
+    fn default() -> Self {
+        Self {
+            data_bits: 8,
+            parity: Parity::None,
+            stop_bits: StopBits::One,
+        }
+    }
+}
+
+/// Encodes one byte into a sequence of GPIO BSRR words
+pub fn encode_uart_byte_cfg(
+    pin_bit: u8,
+    data: u8,
+    cfg: &UartConfig,
+    out: &mut [u32; 12],
+) -> usize {
+    // GPIOx_BSRR register str. 636 kap. 13.4.7
+    let set_high = |bit: u8| -> u32 { 1u32 << bit };
+    // let set_low = |bit: u8| -> u32 { 0 }; // ODR
+    let set_low = |bit: u8| -> u32 { 1u32 << (bit as u32 + 16) }; // BSRR
+
+    let mut idx = 0usize;
+
+    // START bit (LOW)
+    out[idx] = set_low(pin_bit);
+    idx += 1;
+
+    // Data bits, LSB-first
+    let nbits = cfg.data_bits.clamp(5, 8);
+    for i in 0..nbits {
+        let one = ((data >> i) & 1) != 0;
+        out[idx] = if one { set_high(pin_bit) } else { set_low(pin_bit) };
+        idx += 1;
+    }
+
+    // Parity
+    match cfg.parity {
+        Parity::None => {}
+        Parity::Even | Parity::Odd => {
+            let mask: u8 = if nbits == 8 { 0xFF } else { (1u16 << nbits) as u8 - 1 };
+            let ones = (data & mask).count_ones() & 1;
+            let par_bit_is_one = match cfg.parity {
+                Parity::Even => ones == 1,
+                Parity::Odd => ones == 0,
+                _ => false,
+            };
+            out[idx] = if par_bit_is_one {
+                set_high(pin_bit)
+            } else {
+                set_low(pin_bit)
+            };
+            idx += 1;
+        }
+    }
+
+    // STOP bits (HIGH)
+    let stop_ticks = match cfg.stop_bits {
+        StopBits::One => 1usize,
+        StopBits::Two => 2usize,
+    };
+    for _ in 0..stop_ticks {
+        out[idx] = set_high(pin_bit);
+        idx += 1;
+    }
+
+    idx
+}
+
+/// Decode an oversampled stream of logic levels into UART bytes.
+pub fn decode_uart_samples(
+    samples: &[u8],
+    oversample: u16,
+    cfg: &UartConfig,
+) -> heapless::Vec<u8, 256> {
+
+    let mut out = Vec::<u8, 256>::new();
+    let mut idx = 0usize;
+    let nbits = cfg.data_bits as usize;
+
+    while idx + (oversample as usize * (nbits + 3)) < samples.len() {
+        // Wait for start bit (falling edge: high -> low)
+        if samples[idx] != 0 && samples[idx + 1] == 0 {
+            // Align to middle of start bit
+            idx += (oversample / 2) as usize;
+
+            // Sanity check start bit really low
+            if samples.get(idx).copied().unwrap_or(1) != 0 {
+                idx += 1;
+                continue;
+            }
+
+            // Sample data bits
+            let mut data: u8 = 0;
+            for bit in 0..nbits {
+                idx += oversample as usize;
+                let bit_val = samples
+                    .get(idx)
+                    .map(|&b| if b != 0 { 1u8 } else { 0u8 })
+                    .unwrap_or(1);
+                data |= bit_val << bit;
+            }
+
+            // Parity: skip / verify
+            match cfg.parity {
+                Parity::None => {}
+                Parity::Even | Parity::Odd => {
+                    idx += oversample as usize;
+                    // You can optionally add parity check here if needed
+                }
+            }
+
+            // Move past stop bits
+            let stop_skip = match cfg.stop_bits {
+                StopBits::One => oversample as usize,
+                StopBits::Two => (oversample * 2) as usize,
+            };
+            idx += stop_skip;
+
+            // Push decoded byte
+            let _ = out.push(data);
+        } else {
+            idx += 1;
+        }
+    }
+
+    out
+}

semestralka_1b/tests/uart_emulation.rs

@@ -0,0 +1,41 @@
+#![no_std]
+#![no_main]
+
+use dma_gpio as _;
+use panic_probe as _;
+use defmt_rtt as _;
+
+#[defmt_test::tests]
+mod tests {
+    use defmt::assert_eq;
+    use dma_gpio::software_uart::uart_emulation::{
+        encode_uart_byte_cfg, UartConfig, Parity, StopBits
+    };
+
+    const TX_PIN_BIT: u8 = 2;
+
+    #[test]
+    fn test_encode_8n1() {
+        let cfg = UartConfig::default();
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(TX_PIN_BIT, 0x55, &cfg, &mut frame);
+        
+        assert_eq!(used, 10);
+        assert_eq!(frame[0], 1u32 << 18); // Start LOW
+        assert_eq!(frame[9], 1u32 << 2);  // Stop HIGH
+    }
+
+    #[test]
+    fn test_encode_parity() {
+        let cfg = UartConfig {
+            data_bits: 8,
+            parity: Parity::Even,
+            stop_bits: StopBits::One,
+        };
+        
+        let mut frame = [0u32; 12];
+        let used = encode_uart_byte_cfg(TX_PIN_BIT, 0x00, &cfg, &mut frame);
+        
+        assert_eq!(used, 11);
+    }
+}

time_meas/.cargo/config.toml

@@ -0,0 +1,15 @@
+[build]
+target = "thumbv8m.main-none-eabihf"
+
+[target.thumbv8m.main-none-eabihf]
+runner = "probe-rs run --chip STM32U575ZITxQ"
+
+rustflags = [
+  "-C", "linker=rust-lld",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "link-arg=-Tdefmt.x",
+  "-C", "link-arg=--nmagic",
+]
+
+[package.metadata.cargo-flash]
+chip = "STM32U575ZIT"

time_meas/.gitignore

@@ -0,0 +1 @@
+/target

time_meas/LICENSE-APACHE

@@ -0,0 +1,201 @@
+                              Apache License
+                        Version 2.0, January 2004
+                     http://www.apache.org/licenses/
+
+TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+1. Definitions.
+
+   "License" shall mean the terms and conditions for use, reproduction,
+   and distribution as defined by Sections 1 through 9 of this document.
+
+   "Licensor" shall mean the copyright owner or entity authorized by
+   the copyright owner that is granting the License.
+
+   "Legal Entity" shall mean the union of the acting entity and all
+   other entities that control, are controlled by, or are under common
+   control with that entity. For the purposes of this definition,
+   "control" means (i) the power, direct or indirect, to cause the
+   direction or management of such entity, whether by contract or
+   otherwise, or (ii) ownership of fifty percent (50%) or more of the
+   outstanding shares, or (iii) beneficial ownership of such entity.
+
+   "You" (or "Your") shall mean an individual or Legal Entity
+   exercising permissions granted by this License.
+
+   "Source" form shall mean the preferred form for making modifications,
+   including but not limited to software source code, documentation
+   source, and configuration files.
+
+   "Object" form shall mean any form resulting from mechanical
+   transformation or translation of a Source form, including but
+   not limited to compiled object code, generated documentation,
+   and conversions to other media types.
+
+   "Work" shall mean the work of authorship, whether in Source or
+   Object form, made available under the License, as indicated by a
+   copyright notice that is included in or attached to the work
+   (an example is provided in the Appendix below).
+
+   "Derivative Works" shall mean any work, whether in Source or Object
+   form, that is based on (or derived from) the Work and for which the
+   editorial revisions, annotations, elaborations, or other modifications
+   represent, as a whole, an original work of authorship. For the purposes
+   of this License, Derivative Works shall not include works that remain
+   separable from, or merely link (or bind by name) to the interfaces of,
+   the Work and Derivative Works thereof.
+
+   "Contribution" shall mean any work of authorship, including
+   the original version of the Work and any modifications or additions
+   to that Work or Derivative Works thereof, that is intentionally
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+   Licensor for the purpose of discussing and improving the Work, but
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+   designated in writing by the copyright owner as "Not a Contribution."
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+   "Contributor" shall mean Licensor and any individual or Legal Entity
+   on behalf of whom a Contribution has been received by Licensor and
+   subsequently incorporated within the Work.
+
+2. Grant of Copyright License. Subject to the terms and conditions of
+   this License, each Contributor hereby grants to You a perpetual,
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+
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+
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+
+   To apply the Apache License to your work, attach the following
+   boilerplate notice, with the fields enclosed by brackets "[]"
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+Copyright [yyyy] [name of copyright owner]
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+Unless required by applicable law or agreed to in writing, software
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+See the License for the specific language governing permissions and
+limitations under the License.

time_meas/LICENSE-MIT

@@ -0,0 +1,23 @@
+Permission is hereby granted, free of charge, to any
+person obtaining a copy of this software and associated
+documentation files (the "Software"), to deal in the
+Software without restriction, including without
+limitation the rights to use, copy, modify, merge,
+publish, distribute, sublicense, and/or sell copies of
+the Software, and to permit persons to whom the Software
+is furnished to do so, subject to the following
+conditions:
+
+The above copyright notice and this permission notice
+shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
+ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
+IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.

time_meas/Makefile

@@ -0,0 +1,23 @@
+TARGET = thumbv8m.main-none-eabihf
+CHIP = STM32U575ZI
+BIN = stm32u5-blinky
+MODE ?= release
+TARGET_DIR = target/$(TARGET)/$(MODE)
+ELF = $(TARGET_DIR)/$(BIN)
+PROBE = probe-rs
+
+.PHONY: all build flash clean empty
+
+all: build
+
+build:
+	cargo build --$(MODE)
+
+flash: build
+	$(PROBE) run --chip $(CHIP) $(ELF)
+
+empty:
+	$(PROBE) erase --chip $(CHIP)
+
+clean:
+	cargo clean

time_meas/README.md

@@ -0,0 +1,232 @@
+# `app-template`
+
+> Quickly set up a [`probe-rs`] + [`defmt`] + [`flip-link`] embedded project
+
+[`probe-rs`]: https://crates.io/crates/probe-rs
+[`defmt`]: https://github.com/knurling-rs/defmt
+[`flip-link`]: https://github.com/knurling-rs/flip-link
+
+## Dependencies
+
+### 1. `flip-link`:
+
+```bash
+cargo install flip-link
+```
+
+### 2. `probe-rs`:
+
+Install probe-rs by following the instructions at <https://probe.rs/docs/getting-started/installation/>.
+
+### 3. [`cargo-generate`]:
+
+```bash
+cargo install cargo-generate
+```
+
+[`cargo-generate`]: https://crates.io/crates/cargo-generate
+
+> *Note:* You can also just clone this repository instead of using `cargo-generate`, but this involves additional manual adjustments.
+
+## Setup
+
+### 1. Initialize the project template
+
+```bash
+cargo generate \
+    --git https://github.com/knurling-rs/app-template \
+    --branch main \
+    --name my-app
+```
+
+If you look into your new `my-app` folder, you'll find that there are a few `TODO`s in the files marking the properties you need to set.
+
+Let's walk through them together now.
+
+### 2. Set `probe-rs` chip
+
+Pick a chip from ` probe-rs chip list` and enter it into `.cargo/config.toml`.
+
+If, for example, you have a nRF52840 Development Kit as used in one of [our exercises], replace `{{chip}}` with `nRF52840_xxAA`.
+
+[our workshops]: https://rust-exercises.ferrous-systems.com
+
+```diff
+ # .cargo/config.toml
+-runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format=oneline"]
++runner = ["probe-rs", "run", "--chip", "nRF52840_xxAA", "--log-format=oneline"]
+```
+
+### 3. Adjust the compilation target
+
+In `.cargo/config.toml`, pick the right compilation target for your board.
+
+```diff
+ # .cargo/config.toml
+ [build]
+-target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
+-# target = "thumbv7m-none-eabi"    # Cortex-M3
+-# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
+-# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
++target = "thumbv7em-none-eabihf" # Cortex-M4F (with FPU)
+```
+
+Add the target with `rustup`.
+
+```bash
+rustup target add thumbv7em-none-eabihf
+```
+
+### 4. Add a HAL as a dependency
+
+In `Cargo.toml`, list the Hardware Abstraction Layer (HAL) for your board as a dependency.
+
+For the nRF52840 you'll want to use the [`nrf52840-hal`].
+
+[`nrf52840-hal`]: https://crates.io/crates/nrf52840-hal
+
+```diff
+ # Cargo.toml
+ [dependencies]
+-# some-hal = "1.2.3"
++nrf52840-hal = "0.14.0"
+```
+
+⚠️ Note for RP2040 users ⚠️
+
+You will need to not just specify the `rp-hal` HAL, but a BSP (board support crate) which includes a second stage bootloader. Please find a list of available BSPs [here](https://github.com/rp-rs/rp-hal-boards#packages).
+
+### 5. Import your HAL
+
+Now that you have selected a HAL, fix the HAL import in `src/lib.rs`
+
+```diff
+ // my-app/src/lib.rs
+-// use some_hal as _; // memory layout
++use nrf52840_hal as _; // memory layout
+```
+
+### (6. Get a linker script)
+
+Some HAL crates require that you manually copy over a file called `memory.x` from the HAL to the root of your project. For nrf52840-hal, this is done automatically so no action is needed. For other HAL crates, see their documentation on where to find an example file.
+
+The `memory.x` file should look something like:
+
+```text
+MEMORY
+{
+  FLASH : ORIGIN = 0x00000000, LENGTH = 1024K
+  RAM   : ORIGIN = 0x20000000, LENGTH = 256K
+}
+```
+
+The `memory.x` file is included in the `cortex-m-rt` linker script `link.x`, and so `link.x` is the one you should tell `rustc` to use (see the `.cargo/config.toml` file where we do that).
+
+### 7. Run!
+
+You are now all set to `cargo-run` your first `defmt`-powered application!
+There are some examples in the `src/bin` directory.
+
+Start by `cargo run`-ning `my-app/src/bin/hello.rs`:
+
+```console
+$ # `rb` is an alias for `run --bin`
+$ cargo rb hello
+    Finished `dev` profile [optimized + debuginfo] target(s) in 0.01s
+     Running `probe-rs run --chip nrf52840_xxaa --log-format=oneline target/thumbv6m-none-eabi/debug/hello`
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.79 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+Hello, world!
+
+$ echo $?
+0
+```
+
+If you're running out of memory (`flip-link` bails with an overflow error), you can decrease the size of the device memory buffer by setting the `DEFMT_RTT_BUFFER_SIZE` environment variable. The default value is 1024 bytes, and powers of two should be used for optimal performance:
+
+```console
+$ DEFMT_RTT_BUFFER_SIZE=64 cargo rb hello
+```
+
+### (8. Set `rust-analyzer.linkedProjects`)
+
+If you are using [rust-analyzer] with VS Code for IDE-like features you can add following configuration to your `.vscode/settings.json` to make it work transparently across workspaces. Find the details of this option in the [RA docs].
+
+```json
+{
+    "rust-analyzer.linkedProjects": [
+        "Cargo.toml",
+        "firmware/Cargo.toml",
+    ]
+}
+```
+
+[RA docs]: https://rust-analyzer.github.io/manual.html#configuration
+[rust-analyzer]: https://rust-analyzer.github.io/
+
+## Running tests
+
+The template comes configured for running unit tests and integration tests on the target.
+
+Unit tests reside in the library crate and can test private API; the initial set of unit tests are in `src/lib.rs`.
+`cargo test --lib` will run those unit tests.
+
+```console
+$ cargo test --lib
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.15s
+     Running unittests src/lib.rs (target/thumbv6m-none-eabi/debug/deps/example-2b0d0e25d141bf57)
+      Erasing ✔ 100% [####################]   8.00 KiB @  15.99 KiB/s (took 1s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.33 KiB/s (took 1s)                                                                                                                        Finished in 1.10s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Integration tests reside in the `tests` directory; the initial set of integration tests are in `tests/integration.rs`.
+`cargo test --test integration` will run those integration tests.
+Note that the argument of the `--test` flag must match the name of the test file in the `tests` directory.
+
+```console
+$ cargo test --test integration
+   Compiling example v0.1.0 (./knurling-rs/example)
+    Finished `test` profile [optimized + debuginfo] target(s) in 0.10s
+     Running tests/integration.rs (target/thumbv6m-none-eabi/debug/deps/integration-aaaff41151f6a722)
+      Erasing ✔ 100% [####################]   8.00 KiB @  16.03 KiB/s (took 0s)
+  Programming ✔ 100% [####################]   8.00 KiB @  13.19 KiB/s (took 1s)                                                                                                                        Finished in 1.11s
+(1/1) running `it_works`...
+all tests passed!
+```
+
+Note that to add a new test file to the `tests` directory you also need to add a new `[[test]]` section to `Cargo.toml`.
+
+To run all the tests via `cargo test` the tests need to be explicitly disabled for all the existing binary targets.
+See `Cargo.toml` for details on how to do this.
+
+## Support
+
+`app-template` is part of the [Knurling] project, [Ferrous Systems]' effort at
+improving tooling used to develop for embedded systems.
+
+If you think that our work is useful, consider sponsoring it via [GitHub
+Sponsors].
+
+## License
+
+Licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+  http://www.apache.org/licenses/LICENSE-2.0)
+
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+### Contribution
+
+Unless you explicitly state otherwise, any contribution intentionally submitted
+for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
+licensed as above, without any additional terms or conditions.
+
+[Knurling]: https://knurling.ferrous-systems.com
+[Ferrous Systems]: https://ferrous-systems.com/
+[GitHub Sponsors]: https://github.com/sponsors/knurling-rs

time_meas/src/bin/main.rs

@@ -0,0 +1,84 @@
+// src/bin/main.rs
+#![no_std]
+#![no_main]
+
+use core::sync::atomic::{AtomicUsize, Ordering};
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::pac;
+use embassy_stm32::interrupt::InterruptExt;
+use embassy_stm32::timer::low_level::{CountingMode, Timer as LLTimer};
+use embassy_stm32::time::khz;
+use embassy_stm32::interrupt;
+use {defmt_rtt as _, panic_probe as _};
+
+// Pointer to the local `counter` so the ISR can read it with zero per-iteration overhead.
+static COUNTER_PTR: AtomicUsize = AtomicUsize::new(0);
+
+// NVIC handler for TIM2
+#[interrupt]
+fn TIM2() {
+    // Clear UIF, stop the timer
+    pac::TIM2.sr().modify(|r| r.set_uif(false));
+    pac::TIM2.cr1().modify(|r| r.set_cen(false));
+
+    // Snapshot the counter that the loop has been incrementing
+    let ptr = COUNTER_PTR.load(Ordering::Relaxed) as *const u32;
+    let count = unsafe { core::ptr::read_volatile(ptr) };
+
+    info!("10 seconds elapsed, counter = {}", count);
+
+    // Halt
+    loop {
+        cortex_m::asm::bkpt();
+    }
+}
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    info!("Start");
+    let p = embassy_stm32::init(Default::default());
+
+    // Configure TIM2
+    let mut tim2 = LLTimer::new(p.TIM2);
+    tim2.stop();
+    tim2.set_counting_mode(CountingMode::EdgeAlignedUp);
+
+    // Make the timer tick at 10 kHz. Driver derives PSC from RCC, so timing is exact.
+    tim2.set_tick_freq(khz(10));
+
+    // 10 seconds => 10_000 ticks/s * 10 s = 100_000 ticks. ARR is inclusive: set to 100_000 - 1.
+    tim2.set_max_compare_value(100_000 - 1);
+
+    // One-pulse mode (auto-stop after the first update event)
+    tim2.regs_core().cr1().modify(|r| r.set_opm(true));
+
+    // Ensure no pending UIF from the UG we generated during PSC/ARR programming.
+    // Important: do this BEFORE enabling UIE/NVIC to avoid an immediate ISR.
+    let _ = tim2.clear_update_interrupt();
+
+    // Enable update interrupt, reset counter to 0. Do not start yet.
+    tim2.enable_update_interrupt(true);
+    tim2.reset();
+
+    // Expose the address of the loop counter BEFORE enabling the NVIC so the ISR
+    // never runs before COUNTER_PTR is valid.
+    let mut counter: u32 = 0;
+    COUNTER_PTR.store(&counter as *const u32 as usize, Ordering::Relaxed);
+
+    // Unpend and enable NVIC for TIM2, then start the timer.
+    unsafe {
+        embassy_stm32::interrupt::TIM2.unpend();
+        embassy_stm32::interrupt::TIM2.enable();
+    }
+    tim2.start();
+
+    // Tight CPU loop for benchmarking
+    loop {
+        counter = counter.wrapping_add(1);
+
+        if counter % 10000 == 0 {
+            info!("CPU doing other work: {}", counter);
+        }
+    }
+}

time_meas/tests/integration.rs

@@ -0,0 +1,16 @@
+#![no_std]
+#![no_main]
+
+use stm32u5_blinky as _; // memory layout + panic handler
+
+// See https://crates.io/crates/defmt-test/0.3.0 for more documentation (e.g. about the 'state'
+// feature)
+#[defmt_test::tests]
+mod tests {
+    use defmt::assert;
+
+    #[test]
+    fn it_works() {
+        assert!(true)
+    }
+}

usart_async_buffered/.cargo/config.toml

@@ -0,0 +1,15 @@
+[build]
+target = "thumbv8m.main-none-eabihf"
+
+[target.thumbv8m.main-none-eabihf]
+runner = "probe-rs run --chip STM32U575ZITxQ"
+
+rustflags = [
+  "-C", "linker=rust-lld",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "link-arg=-Tdefmt.x",
+  "-C", "link-arg=--nmagic",
+]
+
+[package.metadata.cargo-flash]
+chip = "STM32U575ZIT"

usart_async_buffered/.gitignore

@@ -0,0 +1 @@
+/target