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tweaked parameters, storing before increasing frequencies

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This commit is contained in:
Priec
2025-11-19 19:43:10 +01:00
parent bf34ff1bcb
commit 78c85c7982
4 changed files with 18 additions and 7 deletions
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4
semestralka_1i_rx_dma/Cargo.toml
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@@ -43,3 +43,7 @@ test = false
name = "main" name = "main"
path = "src/bin/main.rs" path = "src/bin/main.rs"
test = false test = false
[profile.dev]
opt-level = 3
codegen-units = 1

5
semestralka_1i_rx_dma/src/bin/main.rs
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@@ -129,6 +129,9 @@ async fn main(spawner: Spawner) {
info!("SW UART RX DMA started"); info!("SW UART RX DMA started");
let f_tim7 = embassy_stm32::rcc::frequency::<embassy_stm32::peripherals::TIM7>().0;
info!("TIM7 clock = {} Hz", f_tim7);
// Process decoded bytes coming from PIPE_SW_RX // Process decoded bytes coming from PIPE_SW_RX
let mut buf = [0u8; 64]; let mut buf = [0u8; 64];
loop { loop {
@@ -150,7 +153,7 @@ pub async fn bridge_usart1_rx_to_usart2_tx(
let n = usart1_rx.read(&mut buf).await; let n = usart1_rx.read(&mut buf).await;
if n > 0 { if n > 0 {
let _ = usart2_tx.write(&buf[..n]).await; let _ = usart2_tx.write(&buf[..n]).await;
// info!("bridge USART1 - USART2 sent:{} bytes: {}", n, &buf[..n]); info!("bridge USART1 - USART2 sent:{} bytes: {}", n, &buf[..n]);
} }
yield_now().await; yield_now().await;
} }

6
semestralka_1i_rx_dma/src/config.rs
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@@ -9,15 +9,15 @@ pub const BAUD: u32 = 9_600;
pub const TX_PIN_BIT: u8 = 0; // PB2 pub const TX_PIN_BIT: u8 = 0; // PB2
pub const RX_PIN_BIT: u8 = 6; // PC3 pub const RX_PIN_BIT: u8 = 6; // PC3
pub const TX_OVERSAMPLE: u16 = 1; pub const TX_OVERSAMPLE: u16 = 1;
pub const RX_OVERSAMPLE: u16 = 2; pub const RX_OVERSAMPLE: u16 = 16;
pub const RX_RING_BYTES: usize = 4096; pub const RX_RING_BYTES: usize = 32768;
pub const TX_RING_BYTES: usize = 4096; pub const TX_RING_BYTES: usize = 4096;
pub const PIPE_HW_TX_SIZE: usize = 1024; pub const PIPE_HW_TX_SIZE: usize = 1024;
pub const PIPE_HW_RX_SIZE: usize = 1024; pub const PIPE_HW_RX_SIZE: usize = 1024;
pub const PIPE_SW_TX_SIZE: usize = 1024; pub const PIPE_SW_TX_SIZE: usize = 1024;
pub const PIPE_SW_RX_SIZE: usize = 1024; pub const PIPE_SW_RX_SIZE: usize = 4096;
pub const PIPE_INT_TX_SIZE: usize = 1024; pub const PIPE_INT_TX_SIZE: usize = 1024;
pub const PIPE_INT_RX_SIZE: usize = 1024; pub const PIPE_INT_RX_SIZE: usize = 1024;

10
semestralka_1i_rx_dma/src/software_uart/gpio_dma_uart_rx.rs
View File

@@ -25,7 +25,7 @@ pub async fn rx_dma_task(
ch: Peri<'static, GPDMA1_CH1>, ch: Peri<'static, GPDMA1_CH1>,
register: *mut u8, register: *mut u8,
ring: &'static mut [u8], ring: &'static mut [u8],
pipe_rx: &'static Pipe<CriticalSectionRawMutex, 1024>, pipe_rx: &'static Pipe<CriticalSectionRawMutex, 4096>,
) { ) {
let mut opts = TransferOptions::default(); let mut opts = TransferOptions::default();
opts.half_transfer_ir = true; opts.half_transfer_ir = true;
@@ -36,8 +36,8 @@ pub async fn rx_dma_task(
rx.start(); rx.start();
// We read into the second half of a buffer, keeping "leftovers" in the first half. // We read into the second half of a buffer, keeping "leftovers" in the first half.
const CHUNK_SIZE: usize = 256; const CHUNK_SIZE: usize = 4096;
const HISTORY_SIZE: usize = 256; // Enough to hold a potential split frame const HISTORY_SIZE: usize = 512; // Enough to hold a potential split frame
const TOTAL_BUF_SIZE: usize = HISTORY_SIZE + CHUNK_SIZE; const TOTAL_BUF_SIZE: usize = HISTORY_SIZE + CHUNK_SIZE;
// Logic level buffer // Logic level buffer
@@ -63,6 +63,10 @@ pub async fn rx_dma_task(
if !decoded.is_empty() { if !decoded.is_empty() {
pipe_rx.write(decoded.as_slice()).await; pipe_rx.write(decoded.as_slice()).await;
for byte in decoded.as_slice() {
info!("DMA BUFFER CHAR: {} (ASCII: {})", *byte, *byte as char);
}
} }
// 4. Shift remaining data to front // 4. Shift remaining data to front