From 78c85c7982018b9751ab5e9f48eb63252a924a08 Mon Sep 17 00:00:00 2001 From: Priec Date: Wed, 19 Nov 2025 19:43:10 +0100 Subject: [PATCH] tweaked parameters, storing before increasing frequencies --- semestralka_1i_rx_dma/Cargo.toml | 4 ++++ semestralka_1i_rx_dma/src/bin/main.rs | 5 ++++- semestralka_1i_rx_dma/src/config.rs | 6 +++--- .../src/software_uart/gpio_dma_uart_rx.rs | 10 +++++++--- 4 files changed, 18 insertions(+), 7 deletions(-) diff --git a/semestralka_1i_rx_dma/Cargo.toml b/semestralka_1i_rx_dma/Cargo.toml index 8523b9d..725af90 100644 --- a/semestralka_1i_rx_dma/Cargo.toml +++ b/semestralka_1i_rx_dma/Cargo.toml @@ -43,3 +43,7 @@ test = false name = "main" path = "src/bin/main.rs" test = false + +[profile.dev] +opt-level = 3 +codegen-units = 1 diff --git a/semestralka_1i_rx_dma/src/bin/main.rs b/semestralka_1i_rx_dma/src/bin/main.rs index 0a4a135..506cca2 100644 --- a/semestralka_1i_rx_dma/src/bin/main.rs +++ b/semestralka_1i_rx_dma/src/bin/main.rs @@ -129,6 +129,9 @@ async fn main(spawner: Spawner) { info!("SW UART RX DMA started"); + let f_tim7 = embassy_stm32::rcc::frequency::().0; + info!("TIM7 clock = {} Hz", f_tim7); + // Process decoded bytes coming from PIPE_SW_RX let mut buf = [0u8; 64]; loop { @@ -150,7 +153,7 @@ pub async fn bridge_usart1_rx_to_usart2_tx( let n = usart1_rx.read(&mut buf).await; if n > 0 { let _ = usart2_tx.write(&buf[..n]).await; - // info!("bridge USART1 - USART2 sent:{} bytes: {}", n, &buf[..n]); + info!("bridge USART1 - USART2 sent:{} bytes: {}", n, &buf[..n]); } yield_now().await; } diff --git a/semestralka_1i_rx_dma/src/config.rs b/semestralka_1i_rx_dma/src/config.rs index 4812c0c..2946488 100644 --- a/semestralka_1i_rx_dma/src/config.rs +++ b/semestralka_1i_rx_dma/src/config.rs @@ -9,15 +9,15 @@ pub const BAUD: u32 = 9_600; pub const TX_PIN_BIT: u8 = 0; // PB2 pub const RX_PIN_BIT: u8 = 6; // PC3 pub const TX_OVERSAMPLE: u16 = 1; -pub const RX_OVERSAMPLE: u16 = 2; +pub const RX_OVERSAMPLE: u16 = 16; -pub const RX_RING_BYTES: usize = 4096; +pub const RX_RING_BYTES: usize = 32768; pub const TX_RING_BYTES: usize = 4096; pub const PIPE_HW_TX_SIZE: usize = 1024; pub const PIPE_HW_RX_SIZE: usize = 1024; pub const PIPE_SW_TX_SIZE: usize = 1024; -pub const PIPE_SW_RX_SIZE: usize = 1024; +pub const PIPE_SW_RX_SIZE: usize = 4096; pub const PIPE_INT_TX_SIZE: usize = 1024; pub const PIPE_INT_RX_SIZE: usize = 1024; diff --git a/semestralka_1i_rx_dma/src/software_uart/gpio_dma_uart_rx.rs b/semestralka_1i_rx_dma/src/software_uart/gpio_dma_uart_rx.rs index 466f403..d52bd5b 100644 --- a/semestralka_1i_rx_dma/src/software_uart/gpio_dma_uart_rx.rs +++ b/semestralka_1i_rx_dma/src/software_uart/gpio_dma_uart_rx.rs @@ -25,7 +25,7 @@ pub async fn rx_dma_task( ch: Peri<'static, GPDMA1_CH1>, register: *mut u8, ring: &'static mut [u8], - pipe_rx: &'static Pipe, + pipe_rx: &'static Pipe, ) { let mut opts = TransferOptions::default(); opts.half_transfer_ir = true; @@ -36,8 +36,8 @@ pub async fn rx_dma_task( rx.start(); // We read into the second half of a buffer, keeping "leftovers" in the first half. - const CHUNK_SIZE: usize = 256; - const HISTORY_SIZE: usize = 256; // Enough to hold a potential split frame + const CHUNK_SIZE: usize = 4096; + const HISTORY_SIZE: usize = 512; // Enough to hold a potential split frame const TOTAL_BUF_SIZE: usize = HISTORY_SIZE + CHUNK_SIZE; // Logic level buffer @@ -63,6 +63,10 @@ pub async fn rx_dma_task( if !decoded.is_empty() { pipe_rx.write(decoded.as_slice()).await; + + for byte in decoded.as_slice() { + info!("DMA BUFFER CHAR: {} (ASCII: {})", *byte, *byte as char); + } } // 4. Shift remaining data to front