filipriec/stm32_rust
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

dumb changes didnt do anything

Browse Source
This commit is contained in:
Priec
2025-12-13 22:31:49 +01:00
parent f36a9fd9e2
commit 58561ec392
2 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
semestralka_2_uart/src/hw_uart_pc/driver.rs
View File

@@ -33,7 +33,7 @@ pub async fn uart_task(
} }
// Outgoing data waiting in TX pipe // Outgoing data waiting in TX pipe
Either::Second(n) => { Either::Second(n) => {
unwrap!(uart.write(&tx_buf[..n]).await); unwrap!(uart.write_all(&tx_buf[..n]).await);
} }
} }
yield_now().await; yield_now().await;

6
semestralka_2_uart/src/hw_uart_pc/init.rs
View File

@@ -51,11 +51,10 @@ pub static CMD_CH: Channel<CriticalSectionRawMutex, LowPowerCmd, 1> = Channel::n
pub async fn uart_cmd_task() { pub async fn uart_cmd_task() {
async fn print_menu() { async fn print_menu() {
while PIPE_HW_TX.len() > 0 { while PIPE_HW_TX.len() > 0 {
embassy_time::Timer::after(embassy_time::Duration::from_millis(2)).await; embassy_time::Timer::after(embassy_time::Duration::from_millis(8)).await;
} }
let _ = PIPE_HW_TX.write(b"\x1B[2J\x1B[H").await;
let _ = PIPE_HW_TX.write( let _ = PIPE_HW_TX.write(
b"\r\n\ b"\x1B[2J\x1B[H\r\n\
Modes:\r\n\ Modes:\r\n\
[1] Standby + 8 KB SRAM2 retention\r\n\ [1] Standby + 8 KB SRAM2 retention\r\n\
[2] Standby + full SRAM2 retention\r\n\ [2] Standby + full SRAM2 retention\r\n\
@@ -64,6 +63,7 @@ pub async fn uart_cmd_task() {
[5] Stop mode (0-3)\r\n\ [5] Stop mode (0-3)\r\n\
" "
).await; ).await;
embassy_time::Timer::after(embassy_time::Duration::from_millis(8)).await;
} }
print_menu().await; print_menu().await;