diff --git a/semestralka_2_uart/src/hw_uart_pc/driver.rs b/semestralka_2_uart/src/hw_uart_pc/driver.rs
index a8c7728..e3dc364 100644
--- a/semestralka_2_uart/src/hw_uart_pc/driver.rs
+++ b/semestralka_2_uart/src/hw_uart_pc/driver.rs
@@ -33,7 +33,7 @@ pub async fn uart_task(
             }
             // Outgoing data waiting in TX pipe
             Either::Second(n) => {
-                unwrap!(uart.write(&tx_buf[..n]).await);
+                unwrap!(uart.write_all(&tx_buf[..n]).await);
             }
         }
         yield_now().await;
diff --git a/semestralka_2_uart/src/hw_uart_pc/init.rs b/semestralka_2_uart/src/hw_uart_pc/init.rs
index d1c1136..b841c95 100644
--- a/semestralka_2_uart/src/hw_uart_pc/init.rs
+++ b/semestralka_2_uart/src/hw_uart_pc/init.rs
@@ -51,11 +51,10 @@ pub static CMD_CH: Channel<CriticalSectionRawMutex, LowPowerCmd, 1> = Channel::n
 pub async fn uart_cmd_task() {
     async fn print_menu() {
         while PIPE_HW_TX.len() > 0 {
-            embassy_time::Timer::after(embassy_time::Duration::from_millis(2)).await;
+            embassy_time::Timer::after(embassy_time::Duration::from_millis(8)).await;
         }
-        let _ = PIPE_HW_TX.write(b"\x1B[2J\x1B[H").await;
         let _ = PIPE_HW_TX.write(
-            b"\r\n\
+            b"\x1B[2J\x1B[H\r\n\
             Modes:\r\n\
             [1] Standby + 8 KB SRAM2 retention\r\n\
             [2] Standby + full SRAM2 retention\r\n\
@@ -64,6 +63,7 @@ pub async fn uart_cmd_task() {
             [5] Stop mode (0-3)\r\n\
             "
         ).await;
+        embassy_time::Timer::after(embassy_time::Duration::from_millis(8)).await;
     }
 
     print_menu().await;